stats: Match current behaviour

Small changes to the branch predictor and BTB caused stats changes
throughout.

28 files changed, 18275 insertions, 17726 deletions

diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
index 5d753bb44..baaf2995a 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.061241                       # Number of seconds simulated
-sim_ticks                                 61241011500                       # Number of ticks simulated
-final_tick                                61241011500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.061235                       # Number of seconds simulated
+sim_ticks                                 61234797500                       # Number of ticks simulated
+final_tick                                61234797500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 253883                       # Simulator instruction rate (inst/s)
-host_op_rate                                   255147                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              171606317                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 452068                       # Number of bytes of host memory used
-host_seconds                                   356.87                       # Real time elapsed on the host
+host_inst_rate                                 274685                       # Simulator instruction rate (inst/s)
+host_op_rate                                   276053                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              185648704                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 404860                       # Number of bytes of host memory used
+host_seconds                                   329.84                       # Real time elapsed on the host
 sim_insts                                    90602850                       # Number of instructions simulated
 sim_ops                                      91054081                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             49536                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             49472                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            947200                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               996736                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        49536                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           49536                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                774                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               996672                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        49472                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           49472                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                773                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              14800                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 15574                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               808870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             15466760                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                16275629                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          808870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             808870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              808870                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            15466760                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               16275629                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         15574                       # Number of read requests accepted
+system.physmem.num_reads::total                 15573                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst               807907                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             15468329                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                16276236                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          807907                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             807907                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              807907                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            15468329                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               16276236                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         15573                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       15574                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       15573                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   996736                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   996672                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    996736                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    996672                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -44,7 +44,7 @@ system.physmem.neitherReadNorWriteReqs              0                       # Nu
 system.physmem.perBankRdBursts::0                 993                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 890                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 949                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1028                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1027                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                1050                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                1113                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                1087                       # Per bank write bursts
@@ -55,8 +55,8 @@ system.physmem.perBankRdBursts::10                938                       # Pe
 system.physmem.perBankRdBursts::11                899                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                904                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                867                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                877                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                905                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                876                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                906                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     61240917000                       # Total gap between requests
+system.physmem.totGap                     61234703000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   15574                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   15573                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -91,7 +91,7 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                     15454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       110                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       109                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        10                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1543                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      644.935839                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     438.870546                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     402.302511                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            247     16.01%     16.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          187     12.12%     28.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           93      6.03%     34.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           68      4.41%     38.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           69      4.47%     43.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           87      5.64%     48.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           40      2.59%     51.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           47      3.05%     54.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          705     45.69%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1543                       # Bytes accessed per row activation
-system.physmem.totQLat                       73240250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 365252750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     77870000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4702.73                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1535                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      648.213681                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     443.714701                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     401.012846                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            241     15.70%     15.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          186     12.12%     27.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           88      5.73%     33.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           73      4.76%     38.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           71      4.63%     42.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           84      5.47%     48.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           36      2.35%     50.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           51      3.32%     54.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          705     45.93%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1535                       # Bytes accessed per row activation
+system.physmem.totQLat                       72594750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 364588500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     77865000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4661.58                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23452.73                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  23411.58                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                          16.28                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       16.28                       # Average system read bandwidth in MiByte/s
@@ -216,49 +216,53 @@ system.physmem.busUtilRead                       0.13                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14026                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      14028                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   90.06                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   90.08                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3932253.56                       # Average gap between requests
-system.physmem.pageHitRate                      90.06                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6305040                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3440250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  63772800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      3932107.04                       # Average gap between requests
+system.physmem.pageHitRate                      90.08                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6282360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3427875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  63679200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3999824400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2491483680                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34557957750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41122783920                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.511714                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57480384250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2044900000                       # Time in different power states
+system.physmem_0.refreshEnergy             3999315840                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2519893620                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            34528365000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              41120963895                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.567381                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    57430990750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2044640000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1713932750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1755713000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5360040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2924625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  57509400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    5314680                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2899875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  57462600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3999824400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2555148690                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34502111250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41122878405                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.513257                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57387653250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2044900000                       # Time in different power states
+system.physmem_1.refreshEnergy             3999315840                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2548962765                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            34502857500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              41116813260                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.499745                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    57389143250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2044640000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1806576750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1797845750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                20752188                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          17062075                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            757746                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8939036                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 8856390                       # Number of BTB hits
+system.cpu.branchPred.lookups                20750031                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          17060378                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            756798                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8954908                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 8830467                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.075448                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   61984                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             98.610360                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   61988                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 17                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           26205                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              24795                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             1410                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          665                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -377,67 +381,102 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        122482023                       # number of cpu cycles simulated
+system.cpu.numCycles                        122469595                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    90602850                       # Number of instructions committed
 system.cpu.committedOps                      91054081                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2176623                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2175024                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.351856                       # CPI: cycles per instruction
-system.cpu.ipc                               0.739724                       # IPC: instructions per cycle
-system.cpu.tickCycles                       109255161                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        13226862                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.351719                       # CPI: cycles per instruction
+system.cpu.ipc                               0.739799                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                63822829     70.09%     70.09% # Class of committed instruction
+system.cpu.op_class_0::IntMult                  10474      0.01%     70.10% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 6      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc               15      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             2      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     70.10% # Class of committed instruction
+system.cpu.op_class_0::MemRead               22475911     24.68%     94.79% # Class of committed instruction
+system.cpu.op_class_0::MemWrite               4744844      5.21%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                 91054081                       # Class of committed instruction
+system.cpu.tickCycles                       109245506                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        13224089                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            946097                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3616.872758                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26263183                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3616.804007                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26262686                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            950193                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             27.639841                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       20511562500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3616.872758                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.883026                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.883026                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs             27.639317                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       20511782500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  3616.804007                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.883009                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.883009                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          255                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2247                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1594                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          260                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2253                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1583                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          55455001                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         55455001                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21594211                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21594211                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4660690                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4660690                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          55454003                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         55454003                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21593712                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21593712                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4660692                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4660692                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          508                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           508                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      26254901                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26254901                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26255409                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26255409                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      26254404                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26254404                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26254912                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26254912                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       914926                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        914926                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        74291                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        74291                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        74289                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        74289                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            4                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            4                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       989217                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         989217                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       989221                       # number of overall misses
-system.cpu.dcache.overall_misses::total        989221                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11919046000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11919046000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2542633500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2542633500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14461679500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14461679500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14461679500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14461679500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22509137                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22509137                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       989215                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         989215                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       989219                       # number of overall misses
+system.cpu.dcache.overall_misses::total        989219                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11919140000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11919140000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2539899500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2539899500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  14459039500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  14459039500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  14459039500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  14459039500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22508638                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22508638                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          512                       # number of SoftPFReq accesses(hits+misses)
@@ -446,28 +485,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     27244118                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     27244118                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     27244630                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     27244630                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040647                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040647                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015690                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.015690                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     27243619                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27243619                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27244131                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27244131                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040648                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040648                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.015689                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.015689                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.007812                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.007812                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.036309                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.036309                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036310                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.036310                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.036309                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.036309                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.333358                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.333358                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34225.323390                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34225.323390                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.319624                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14619.319624                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.260509                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14619.260509                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.436099                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.436099                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34189.442582                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 34189.442582                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14616.680398                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14616.680398                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14616.621294                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14616.621294                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -478,107 +517,108 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       943278                       # number of writebacks
 system.cpu.dcache.writebacks::total            943278                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11501                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        11501                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27526                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        27526                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        39027                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        39027                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        39027                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        39027                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903425                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       903425                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46765                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        46765                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        11500                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        11500                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        27525                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        27525                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        39025                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39025                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39025                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39025                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903426                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       903426                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46764                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46764                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.demand_mshr_misses::cpu.data       950190                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total       950190                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       950193                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       950193                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10865349000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  10865349000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1481625500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1481625500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  10865506000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  10865506000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1480423500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1480423500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       156500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       156500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12346974500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  12346974500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12347131000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  12347131000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040136                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040136                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  12345929500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  12345929500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  12346086000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  12346086000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.040137                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.040137                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009876                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009876                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.005859                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.005859                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034877                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.034877                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034876                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.034876                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.841188                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.841188                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31682.358602                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31682.358602                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034878                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.034878                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034877                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.034877                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12027.001658                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12027.001658                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31657.332564                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31657.332564                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.216420                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.216420                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.340097                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.340097                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12993.116640                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12993.116640                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12993.240321                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12993.240321                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 5                       # number of replacements
-system.cpu.icache.tags.tagsinuse           689.439811                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27770468                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               802                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          34626.518703                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           689.102041                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            27766889                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               801                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          34665.279650                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   689.439811                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.336641                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.336641                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          797                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   689.102041                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.336476                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.336476                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          796                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           42                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           15                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           13                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          740                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.389160                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          55543342                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         55543342                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27770468                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27770468                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27770468                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27770468                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27770468                       # number of overall hits
-system.cpu.icache.overall_hits::total        27770468                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          802                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           802                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          802                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
-system.cpu.icache.overall_misses::total           802                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     59898000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     59898000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     59898000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     59898000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     59898000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     59898000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27771270                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27771270                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27771270                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27771270                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27771270                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27771270                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_task_id_percent::1024     0.388672                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          55536181                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         55536181                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     27766889                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27766889                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27766889                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27766889                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27766889                       # number of overall hits
+system.cpu.icache.overall_hits::total        27766889                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          801                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           801                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          801                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            801                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          801                       # number of overall misses
+system.cpu.icache.overall_misses::total           801                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     60228000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     60228000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     60228000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     60228000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     60228000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     60228000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27767690                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27767690                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27767690                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27767690                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27767690                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27767690                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000029                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000029                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000029                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000029                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000029                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74685.785536                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74685.785536                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74685.785536                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74685.785536                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74685.785536                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74685.785536                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75191.011236                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75191.011236                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75191.011236                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75191.011236                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75191.011236                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75191.011236                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -589,63 +629,63 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            5                       # number of writebacks
 system.cpu.icache.writebacks::total                 5                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          802                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          802                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     59096000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     59096000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     59096000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     59096000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     59096000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     59096000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          801                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          801                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          801                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          801                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          801                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          801                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     59427000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     59427000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     59427000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     59427000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     59427000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     59427000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000029                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000029                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000029                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000029                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73685.785536                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73685.785536                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73685.785536                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 73685.785536                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73685.785536                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 73685.785536                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74191.011236                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74191.011236                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74191.011236                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 74191.011236                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74191.011236                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 74191.011236                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        10245.556296                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1833992                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            15557                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           117.888539                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse        10244.686315                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1833993                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            15556                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           117.896182                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9355.655409                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.444539                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   215.456347                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.285512                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020582                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  9355.125797                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.107024                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   215.453494                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.285496                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020572                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.006575                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.312670                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15557                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::total     0.312643                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15556                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          526                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1095                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          524                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1096                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        13876                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474762                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         15237898                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        15237898                       # Number of data accesses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.474731                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         15237888                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        15237888                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks       943278                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       943278                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            4                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            4                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        32221                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        32221                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        32220                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32220                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           26                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total           26                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       903166                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       903166                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       903167                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       903167                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst           26                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data       935387                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total          935413                       # number of demand (read+write) hits
@@ -654,68 +694,68 @@ system.cpu.l2cache.overall_hits::cpu.data       935387                       # n
 system.cpu.l2cache.overall_hits::total         935413                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        14544                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        14544                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          776                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          776                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          775                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          775                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          262                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total          262                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          776                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          775                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data        14806                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         15582                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          776                       # number of overall misses
+system.cpu.l2cache.demand_misses::total         15581                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          775                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        14806                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        15582                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1067670500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1067670500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     57597000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     57597000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     21897000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     21897000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     57597000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1089567500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1147164500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     57597000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1089567500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1147164500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total        15581                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1066480500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1066480500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     57929500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     57929500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     22043500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     22043500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     57929500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1088524000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1146453500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     57929500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1088524000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1146453500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks       943278                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total       943278                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks            4                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            4                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        46765                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        46765                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          802                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          802                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       903428                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       903428                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          802                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        46764                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46764                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          801                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          801                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       903429                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       903429                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          801                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       950193                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       950995                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          802                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       950994                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          801                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       950193                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       950995                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.311002                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.311002                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.967581                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.967581                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.overall_accesses::total       950994                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.311008                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.311008                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.967541                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.967541                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000290                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000290                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.967581                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.967541                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.015582                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.016385                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967581                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.016384                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.967541                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.015582                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.016385                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73409.687844                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73409.687844                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74222.938144                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74222.938144                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83576.335878                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83576.335878                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74222.938144                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73589.592057                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73621.133359                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74222.938144                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73589.592057                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73621.133359                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.016384                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73327.867162                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73327.867162                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74747.741935                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74747.741935                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84135.496183                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84135.496183                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74747.741935                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73519.113873                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73580.225916                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74747.741935                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73519.113873                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73580.225916                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -736,54 +776,54 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data            6
 system.cpu.l2cache.overall_mshr_hits::total            8                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14544                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        14544                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          774                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          774                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          773                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          773                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          256                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total          256                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          774                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          773                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data        14800                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        15574                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          774                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15573                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          773                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        14800                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        15574                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    922230500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    922230500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     49710000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     49710000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     18946000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     18946000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     49710000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    941176500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    990886500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     49710000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    941176500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    990886500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311002                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311002                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.965087                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.overall_mshr_misses::total        15573                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    921040500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    921040500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     50052500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     50052500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     19092500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     19092500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     50052500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    940133000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    990185500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     50052500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    940133000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    990185500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311008                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.311008                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.965044                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000283                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000283                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.016377                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965087                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.016375                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965044                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015576                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.016377                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63409.687844                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63409.687844                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64224.806202                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64224.806202                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74007.812500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74007.812500                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64224.806202                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63593.006757                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63624.406061                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64224.806202                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63593.006757                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63624.406061                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.016375                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63327.867162                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63327.867162                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64750.970246                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64750.970246                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74580.078125                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74580.078125                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64750.970246                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63522.500000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63583.477814                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64750.970246                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63522.500000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63583.477814                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1897097                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1897096                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       946118                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          150                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
@@ -793,56 +833,56 @@ system.cpu.toL2Bus.trans_dist::ReadResp        904230                       # Tr
 system.cpu.toL2Bus.trans_dist::WritebackDirty       943278                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            5                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict         2819                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        46765                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        46765                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          802                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       903428                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1609                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq        46764                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        46764                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          801                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       903429                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1607                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2846483                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2848092                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2848090                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        51584                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    121182144                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          121233792                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          121233728                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       950995                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples       950994                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000175                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.013211                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             950829     99.98%     99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             950828     99.98%     99.98% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                166      0.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         950995                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1891831500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         950994                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1891831000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          3.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1203998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1202498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1425292494                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               1030                       # Transaction distribution
+system.membus.trans_dist::ReadResp               1029                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             14544                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            14544                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          1030                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  31148                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996736                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  996736                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          1029                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        31146                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  31146                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       996672                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  996672                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             15574                       # Request fanout histogram
+system.membus.snoop_fanout::samples             15573                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   15574    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   15573    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               15574                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            21739000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               15573                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            21737000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           82131250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           82128750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 00e478cc7..fd8ec81c4 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,114 +1,114 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.058179                       # Number of seconds simulated
-sim_ticks                                 58178990500                       # Number of ticks simulated
-final_tick                                58178990500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.058199                       # Number of seconds simulated
+sim_ticks                                 58199030500                       # Number of ticks simulated
+final_tick                                58199030500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60429                       # Simulator instruction rate (inst/s)
-host_op_rate                                    60730                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               38808737                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 520460                       # Number of bytes of host memory used
-host_seconds                                  1499.12                       # Real time elapsed on the host
+host_inst_rate                                 158181                       # Simulator instruction rate (inst/s)
+host_op_rate                                   158969                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              101622775                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 491528                       # Number of bytes of host memory used
+host_seconds                                   572.70                       # Real time elapsed on the host
 sim_insts                                    90589799                       # Number of instructions simulated
 sim_ops                                      91041030                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             44864                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             57344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       923968                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1026176                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        44864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           44864                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        10880                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             10880                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                701                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                896                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        14437                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 16034                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             170                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  170                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               771137                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               985648                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     15881472                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                17638257                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          771137                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             771137                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            187009                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 187009                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            187009                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              771137                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              985648                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     15881472                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               17825266                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         16035                       # Number of read requests accepted
-system.physmem.writeReqs                          170                       # Number of write requests accepted
-system.physmem.readBursts                       16035                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        170                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1017600                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      8576                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                      9088                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1026240                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  10880                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      134                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             44352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             87616                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       925056                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1057024                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        44352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           44352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        11200                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             11200                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                693                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1369                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        14454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 16516                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             175                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  175                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               762075                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1505455                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     15894698                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                18162227                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          762075                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             762075                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            192443                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 192443                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            192443                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              762075                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1505455                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     15894698                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18354670                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         16517                       # Number of read requests accepted
+system.physmem.writeReqs                          175                       # Number of write requests accepted
+system.physmem.readBursts                       16517                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        175                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1048320                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      8768                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                      9216                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1057088                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  11200                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      137                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       4                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                1166                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 919                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 920                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 953                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1033                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1062                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1116                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1091                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1031                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1061                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1122                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1094                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                1089                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1024                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1025                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 962                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                937                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                933                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                900                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                906                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                899                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                910                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                933                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                   7                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                903                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                900                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1411                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                910                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                   2                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                  12                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                   4                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                   6                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                   1                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                   3                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                  12                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                  37                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                   2                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                  16                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                  40                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                   7                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   2                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
-system.physmem.perBankWrBursts::10                  6                       # Per bank write bursts
-system.physmem.perBankWrBursts::11                  4                       # Per bank write bursts
-system.physmem.perBankWrBursts::12                  7                       # Per bank write bursts
-system.physmem.perBankWrBursts::13                 12                       # Per bank write bursts
-system.physmem.perBankWrBursts::14                 33                       # Per bank write bursts
-system.physmem.perBankWrBursts::15                  1                       # Per bank write bursts
+system.physmem.perBankWrBursts::10                  2                       # Per bank write bursts
+system.physmem.perBankWrBursts::11                  2                       # Per bank write bursts
+system.physmem.perBankWrBursts::12                  2                       # Per bank write bursts
+system.physmem.perBankWrBursts::13                 17                       # Per bank write bursts
+system.physmem.perBankWrBursts::14                 37                       # Per bank write bursts
+system.physmem.perBankWrBursts::15                  7                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     58178982000                       # Total gap between requests
+system.physmem.totGap                     58199022000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   16035                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   16517                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    170                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10985                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      2530                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       456                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       393                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       293                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       292                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       315                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       291                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    175                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     11454                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      2521                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       462                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       296                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       296                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       316                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       292                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                       292                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        54                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
@@ -148,8 +148,8 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::17                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::19                        9                       # What write queue length does an incoming req see
@@ -157,9 +157,9 @@ system.physmem.wrQLenPdf::20                        9                       # Wh
 system.physmem.wrQLenPdf::21                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                        9                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::27                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::28                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::29                        8                       # What write queue length does an incoming req see
@@ -197,93 +197,95 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1792                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      572.928571                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     339.689561                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     430.205419                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            476     26.56%     26.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          210     11.72%     38.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           97      5.41%     43.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           63      3.52%     47.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           46      2.57%     49.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           57      3.18%     52.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           50      2.79%     55.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           48      2.68%     58.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          745     41.57%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1792                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples         1812                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      582.746137                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     353.648277                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     424.722034                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            448     24.72%     24.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          213     11.75%     36.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           96      5.30%     41.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           72      3.97%     45.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           56      3.09%     48.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           67      3.70%     52.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           61      3.37%     55.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           48      2.65%     58.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          751     41.45%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1812                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples             8                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      1980.250000                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       75.328493                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     5451.280656                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2016.250000                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       98.342741                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     5441.040729                       # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::0-511               7     87.50%     87.50% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-15871            1     12.50%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total               8                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples             8                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.750000                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.736929                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.707107                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  1     12.50%     12.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                  7     87.50%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean               18                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       18.000000                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                  8    100.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total               8                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      173529353                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 471654353                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     79500000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10913.11                       # Average queueing delay per DRAM burst
-system.physmem.avgBusLat                      4999.69                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29661.93                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          17.49                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.totQLat                      175730624                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 482855624                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     81900000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10728.37                       # Average queueing delay per DRAM burst
+system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat                  29478.37                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          18.01                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.16                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       17.64                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       18.16                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.19                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.14                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.14                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        20.26                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      14205                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                        45                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   89.33                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  27.11                       # Row buffer hit rate for writes
-system.physmem.avgGap                      3590187.10                       # Average gap between requests
-system.physmem.pageHitRate                      88.69                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    7794360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    4252875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  65746200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                   498960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3799960320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2649738195                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            32583140250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              39111131160                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              672.253743                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    54193285294                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1942460000                       # Time in different power states
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        14.75                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      14651                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                        51                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   89.44                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  29.82                       # Row buffer hit rate for writes
+system.physmem.avgGap                      3486641.62                       # Average gap between requests
+system.physmem.pageHitRate                      88.83                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    7658280                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    4178625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  65512200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                   486000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3800977440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             2714701095                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            32535498750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              39129012390                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              672.381118                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    54114607553                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1943240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      2043128456                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      2137743447                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    5753160                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3139125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  58273800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                   421200                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3799960320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2342596545                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            32852562750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              39062706900                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.421412                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    54644034494                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1942460000                       # Time in different power states
+system.physmem_1.actEnergy                    6017760                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3283500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  61916400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                   447120                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3800977440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2480426820                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            32741002500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              39094071540                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.780705                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    54458056984                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1943240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1592379256                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1793992016                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                28257760                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          23279733                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            837848                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             11842330                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                11784674                       # Number of BTB hits
+system.cpu.branchPred.lookups                28233538                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          23266052                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            835390                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             11829354                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                11747655                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.513136                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                   75804                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 88                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             99.309354                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                   74541                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 92                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           27216                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              25478                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             1738                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          245                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -402,83 +404,83 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  442                       # Number of system calls
-system.cpu.numCycles                        116357982                       # number of cpu cycles simulated
+system.cpu.numCycles                        116398062                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles             748703                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      134988401                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    28257760                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           11860478                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     114715121                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1679113                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  977                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          833                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  32302514                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   574                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          116305190                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.165894                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.319044                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles             746143                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      134906479                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    28233538                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           11847674                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     114760827                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1674187                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  911                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          805                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  32275055                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   562                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          116345779                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.164712                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.318875                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58733287     50.50%     50.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 13942631     11.99%     62.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9230901      7.94%     70.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 34398371     29.58%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 58810972     50.55%     50.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 13933527     11.98%     62.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9228064      7.93%     70.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 34373216     29.54%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            116305190                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.242852                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.160113                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8839704                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              64044923                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  33035218                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9558027                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 827318                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              4101316                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 12341                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              114430969                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               1996281                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 827318                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15281065                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                49888125                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         109559                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  35425090                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              14774033                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110899108                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               1414941                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              11132282                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1143663                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1527047                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 487517                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           129956871                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             483273963                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        119474159                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               431                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            116345779                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.242560                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.159010                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8834252                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              64111694                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  33013656                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9560800                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 825377                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              4097950                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11817                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              114395383                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               1985420                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 825377                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15270485                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                49952350                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         109536                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  35410349                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              14777682                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110872417                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1412237                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              11132933                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1144918                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1526969                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 486977                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           129945519                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             483153288                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        119447216                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               432                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             107312919                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 22643952                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               4364                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           4359                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  21508074                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26812702                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             5350076                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads            518927                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           253927                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  109691489                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                8248                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 101389067                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1075877                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        18658707                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     41691247                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             30                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     116305190                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.871750                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        0.989327                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 22632600                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               4409                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           4401                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  21510749                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26805153                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             5347343                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads            519410                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           254099                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  109667150                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                8283                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 101366848                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1074801                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        18634403                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     41667299                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             65                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     116345779                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.871255                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        0.989200                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            54664640     47.00%     47.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            31360805     26.96%     73.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22009670     18.92%     92.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7071691      6.08%     98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1198071      1.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            54714850     47.03%     47.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            31358235     26.95%     73.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22007860     18.92%     92.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7066756      6.07%     98.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1197765      1.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::5                 313      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
@@ -486,44 +488,44 @@ system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Nu
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       116305190                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       116345779                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9787073     48.68%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     50      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9614641     47.82%     96.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                704123      3.50%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9784213     48.67%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     50      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                13      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     48.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                9614548     47.83%     96.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                702998      3.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              71985140     71.00%     71.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                10711      0.01%     71.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              71970791     71.00%     71.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                10698      0.01%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     71.01% # Type of FU issued
@@ -551,82 +553,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc            124      0.00%     71.01% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            2      0.00%     71.01% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     71.01% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24343416     24.01%     95.02% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             5049618      4.98%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24337715     24.01%     95.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             5047462      4.98%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              101389067                       # Type of FU issued
-system.cpu.iq.rate                           0.871355                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    20105900                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.198304                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          340264641                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         128359131                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     99626279                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total              101366848                       # Type of FU issued
+system.cpu.iq.rate                           0.870864                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    20101822                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.198308                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          340255638                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128310520                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     99608490                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 460                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                626                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          113                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              121494727                       # Number of integer alu accesses
+system.cpu.iq.fp_inst_queue_writes                624                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          115                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              121468430                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     240                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           289423                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads           288068                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      4336791                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1514                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         1348                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       605232                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4329242                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         1500                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         1342                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       602499                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         7566                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        130606                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         7579                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        130663                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 827318                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 8114310                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                683997                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           109712406                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 825377                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8119454                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                685980                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           109688255                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26812702                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              5350076                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               4360                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 178818                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                342272                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           1348                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         436595                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       412881                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               849476                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             100127969                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23806710                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1261098                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              26805153                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              5347343                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               4395                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 180270                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                342292                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           1342                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         435059                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       412404                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               847463                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             100109842                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23803071                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1257006                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         12669                       # number of nop insts executed
-system.cpu.iew.exec_refs                     28724643                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 20624882                       # Number of branches executed
-system.cpu.iew.exec_stores                    4917933                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.860517                       # Inst execution rate
-system.cpu.iew.wb_sent                       99711034                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      99626392                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  59704097                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95546076                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       0.856206                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.624872                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        17384953                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         12822                       # number of nop insts executed
+system.cpu.iew.exec_refs                     28718921                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 20621209                       # Number of branches executed
+system.cpu.iew.exec_stores                    4915850                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.860065                       # Inst execution rate
+system.cpu.iew.wb_sent                       99693752                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      99608605                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  59691637                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  95527463                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       0.855758                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.624864                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        17362842                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            8218                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            825610                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    113612998                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.801437                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.737923                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            823674                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    113658017                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.801119                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.737711                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     77188479     67.94%     67.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     18612991     16.38%     84.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      7152574      6.30%     90.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      3468909      3.05%     93.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1644585      1.45%     95.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       541952      0.48%     95.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       704226      0.62%     96.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       178939      0.16%     96.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4120343      3.63%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     77235221     67.95%     67.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     18611593     16.38%     84.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      7151823      6.29%     90.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      3469408      3.05%     93.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1644636      1.45%     95.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       541902      0.48%     95.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       703188      0.62%     96.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       178974      0.16%     96.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4121272      3.63%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    113612998                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    113658017                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             90602408                       # Number of instructions committed
 system.cpu.commit.committedOps               91053639                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -672,78 +674,78 @@ system.cpu.commit.op_class_0::MemWrite        4744844      5.21%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91053639                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               4120343                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    217925513                       # The number of ROB reads
-system.cpu.rob.rob_writes                   219569964                       # The number of ROB writes
-system.cpu.timesIdled                             581                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           52792                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               4121272                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    217947492                       # The number of ROB reads
+system.cpu.rob.rob_writes                   219521309                       # The number of ROB writes
+system.cpu.timesIdled                             570                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           52283                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    90589799                       # Number of Instructions Simulated
 system.cpu.committedOps                      91041030                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.284449                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.284449                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.778544                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.778544                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                108112154                       # number of integer regfile reads
-system.cpu.int_regfile_writes                58701199                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        58                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       93                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 369067542                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 58693892                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                28415154                       # number of misc regfile reads
+system.cpu.cpi                               1.284891                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.284891                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.778276                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.778276                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                108097873                       # number of integer regfile reads
+system.cpu.int_regfile_writes                58692304                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        59                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       96                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 369004699                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 58686555                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                28410228                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   7784                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           5470195                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.784912                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            18253010                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           5470707                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs              3.336499                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          35707500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.784912                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999580                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999580                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           5470634                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.784091                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            18249365                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           5471146                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              3.335565                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          35796500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.784091                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999578                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999578                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          355                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          157                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          344                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          168                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          61911209                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         61911209                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     13890997                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13890997                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4353726                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4353726                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses          61906904                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         61906904                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     13887331                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13887331                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4353747                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4353747                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          522                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           522                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         3872                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      18244723                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         18244723                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     18245245                       # number of overall hits
-system.cpu.dcache.overall_hits::total        18245245                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      9585970                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       9585970                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       381255                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       381255                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      18241078                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         18241078                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     18241600                       # number of overall hits
+system.cpu.dcache.overall_hits::total        18241600                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      9587264                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       9587264                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       381234                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       381234                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            7                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            7                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data           15                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total           15                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      9967225                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9967225                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9967232                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9967232                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  88736242500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  88736242500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   4002302858                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   4002302858                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       296500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       296500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  92738545358                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  92738545358                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  92738545358                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  92738545358                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23476967                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23476967                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9968498                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9968498                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9968505                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9968505                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  88773272500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  88773272500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4000795875                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4000795875                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       291000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       291000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  92774068375                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  92774068375                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  92774068375                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  92774068375                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23474595                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23474595                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          529                       # number of SoftPFReq accesses(hits+misses)
@@ -752,309 +754,309 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887
 system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28211948                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28211948                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28212477                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28212477                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408314                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.408314                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080519                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.080519                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     28209576                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28209576                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28210105                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28210105                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.408410                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.408410                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080514                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.080514                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total     0.013233                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.003859                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.003859                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.353298                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.353298                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.353292                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.353292                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9256.887149                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  9256.887149                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10497.705887                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10497.705887                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  9304.349541                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  9304.349541                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  9304.343007                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  9304.343007                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       330007                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       109189                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            121421                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           12842                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717874                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     8.502492                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.353373                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.353373                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.353366                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.353366                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  9259.500156                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  9259.500156                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        19400                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        19400                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  9306.724882                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  9306.724882                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  9306.718347                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  9306.718347                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       329915                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       108865                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            121409                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           12838                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     2.717385                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     8.479903                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      5470195                       # number of writebacks
-system.cpu.dcache.writebacks::total           5470195                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4337753                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      4337753                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158766                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       158766                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      5470634                       # number of writebacks
+system.cpu.dcache.writebacks::total           5470634                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4338603                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      4338603                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       158750                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       158750                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           15                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total           15                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4496519                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4496519                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4496519                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4496519                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248217                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      5248217                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222489                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       222489                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4497353                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4497353                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4497353                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4497353                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5248661                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      5248661                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       222484                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       222484                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            4                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            4                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      5470706                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      5470706                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      5470710                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      5470710                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43257355500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  43257355500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2285854739                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2285854739                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      5471145                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      5471145                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      5471149                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      5471149                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  43288788000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  43288788000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2285573254                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2285573254                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       214500                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       214500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45543210239                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  45543210239                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45543424739                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  45543424739                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223547                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223547                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046988                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046988                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  45574361254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  45574361254                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  45574575754                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  45574575754                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.223589                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.223589                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046987                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.046987                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.007561                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.007561                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193915                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.193915                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193911                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.193911                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8242.295526                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8242.295526                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.012374                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.012374                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.193946                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.193946                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.193943                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.193943                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8247.586956                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  8247.586956                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        53625                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        53625                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8324.923737                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  8324.923737                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8324.956859                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  8324.956859                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8329.949445                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  8329.949445                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8329.982560                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  8329.982560                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               452                       # number of replacements
-system.cpu.icache.tags.tagsinuse           428.759642                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            32301343                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               911                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          35457.017563                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               447                       # number of replacements
+system.cpu.icache.tags.tagsinuse           427.448157                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            32273898                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               904                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          35701.214602                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   428.759642                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.837421                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.837421                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          459                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           52                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           22                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          331                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.896484                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          64605911                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         64605911                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     32301343                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        32301343                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      32301343                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         32301343                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     32301343                       # number of overall hits
-system.cpu.icache.overall_hits::total        32301343                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1157                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1157                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1157                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1157                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1157                       # number of overall misses
-system.cpu.icache.overall_misses::total          1157                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     61697981                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     61697981                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     61697981                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     61697981                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     61697981                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     61697981                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     32302500                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     32302500                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     32302500                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     32302500                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     32302500                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     32302500                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000036                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53325.826275                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53325.826275                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53325.826275                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53325.826275                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53325.826275                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53325.826275                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        18986                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          108                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               225                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst   427.448157                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.834860                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.834860                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          457                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           53                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           51                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           18                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          335                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.892578                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          64550990                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         64550990                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     32273898                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        32273898                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      32273898                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         32273898                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     32273898                       # number of overall hits
+system.cpu.icache.overall_hits::total        32273898                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1145                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1145                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1145                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1145                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1145                       # number of overall misses
+system.cpu.icache.overall_misses::total          1145                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     60302481                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     60302481                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     60302481                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     60302481                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     60302481                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     60302481                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     32275043                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     32275043                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     32275043                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     32275043                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     32275043                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     32275043                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000035                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000035                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000035                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000035                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000035                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000035                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 52665.922271                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 52665.922271                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        18953                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          107                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               219                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    84.382222                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    21.600000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    86.543379                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    21.400000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          452                       # number of writebacks
-system.cpu.icache.writebacks::total               452                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          245                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          245                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          245                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          245                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          245                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          245                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          912                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          912                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          912                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          912                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          912                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          912                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     50324485                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     50324485                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     50324485                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     50324485                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     50324485                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     50324485                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks          447                       # number of writebacks
+system.cpu.icache.writebacks::total               447                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          240                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          240                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          240                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          240                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          240                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          240                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          905                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          905                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          905                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          905                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          905                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          905                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     49734485                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     49734485                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     49734485                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     49734485                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     49734485                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     49734485                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000028                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000028                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000028                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000028                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55180.356360                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55180.356360                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55180.356360                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 55180.356360                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55180.356360                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 55180.356360                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      4981576                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      5296807                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit       274066                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      4981065                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      5296247                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit       274020                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage     14075593                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements              236                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        11228.158132                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            5318864                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            14906                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           356.827050                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage     14074841                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements              248                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        11235.818499                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            5318374                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            14915                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           356.578880                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 11064.722538                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   163.435594                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.675337                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009975                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.685312                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          176                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        14494                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           10                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          160                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          493                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3697                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9309                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          105                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          890                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.010742                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.884644                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        180495153                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       180495153                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      5450602                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      5450602                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        17129                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        17129                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       226024                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       226024                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          209                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total          209                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5243596                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      5243596                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          209                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      5469620                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         5469829                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          209                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      5469620                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        5469829                       # number of overall hits
+system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   174.301588                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.675141                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.010639                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.685780                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          181                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        14486                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          168                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          469                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3489                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         9544                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          100                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          884                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.011047                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.884155                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        180510207                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       180510207                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      5451171                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      5451171                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        17033                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        17033                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       226019                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       226019                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          210                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total          210                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      5243562                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      5243562                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          210                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      5469581                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         5469791                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          210                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      5469581                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        5469791                       # number of overall hits
 system.cpu.l2cache.UpgradeReq_misses::cpu.data            3                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total            3                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          499                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          499                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          703                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          703                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          588                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          588                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          703                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1087                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          1790                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          703                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1087                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         1790                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        60500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total        60500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     41219500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     41219500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     48001500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     48001500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     40148500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     40148500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     48001500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     81368000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    129369500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     48001500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     81368000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    129369500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      5450602                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      5450602                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        17129                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        17129                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data          500                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          500                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          695                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          695                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1065                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total         1065                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          695                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1565                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          2260                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          695                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1565                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         2260                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        59500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total        59500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     41259500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     41259500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     47414000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     47414000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     71274500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     71274500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     47414000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    112534000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    159948000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     47414000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    112534000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    159948000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      5451171                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      5451171                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        17033                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        17033                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::cpu.data            3                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.UpgradeReq_accesses::total            3                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       226523                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       226523                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          912                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          912                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      5244184                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      5244184                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          912                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      5470707                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      5471619                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          912                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      5470707                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      5471619                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       226519                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       226519                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          905                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          905                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      5244627                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      5244627                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          905                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      5471146                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      5472051                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          905                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      5471146                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      5472051                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002203                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.002203                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.770833                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.770833                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000112                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000112                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.770833                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.000199                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.000327                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.770833                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.000199                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.000327                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82604.208417                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82604.208417                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68280.938834                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68280.938834                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68279.761905                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68279.761905                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68280.938834                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74855.565777                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72273.463687                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68280.938834                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74855.565777                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72273.463687                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.002207                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.002207                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.767956                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.767956                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000203                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000203                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.767956                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.000286                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.000413                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.767956                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.000286                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.000413                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        82519                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        82519                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70773.451327                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1063,158 +1065,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          170                       # number of writebacks
-system.cpu.l2cache.writebacks::total              170                       # number of writebacks
+system.cpu.l2cache.unused_prefetches                7                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks          175                       # number of writebacks
+system.cpu.l2cache.writebacks::total              175                       # number of writebacks
 system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          158                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_hits::total          158                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           32                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           32                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           37                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           37                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data          190                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total          191                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          195                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total          196                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data          190                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total          191                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       316176                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       316176                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data          195                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total          196                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       316084                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       316084                       # number of HardPFReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            3                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total            3                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          341                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          341                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          702                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          702                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          556                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          556                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          702                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          897                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         1599                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          702                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          897                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       316176                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       317775                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    851895298                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    851895298                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        42500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        42500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     32684500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     32684500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43736000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43736000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     35150000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     35150000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43736000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     67834500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    111570500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43736000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     67834500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    851895298                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    963465798                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          342                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          342                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          694                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          694                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1028                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1028                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          694                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1370                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         2064                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          694                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1370                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       316084                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       318148                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    852614747                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    852614747                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        41500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        41500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     32745000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     32745000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     43196500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     43196500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63614500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63614500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     43196500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     96359500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    139556000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     43196500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     96359500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    852614747                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    992170747                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001505                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001505                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.769737                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.769737                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000106                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000106                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.769737                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000164                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.000292                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.769737                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000164                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001510                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001510                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.766851                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.766851                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000196                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000196                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.766851                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.000250                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.000377                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.766851                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.000250                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.058077                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2694.370534                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  2694.370534                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95848.973607                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95848.973607                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62301.994302                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62301.994302                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63219.424460                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63219.424460                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62301.994302                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75623.745819                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69775.171982                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62301.994302                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75623.745819                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2694.370534                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total  3031.911881                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.058141                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2697.430895                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  2697.430895                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  2697.430895                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total  3118.582380                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     10942269                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      5470664                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2916                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       303004                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       302696                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops          308                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       5245095                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      5450772                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        20045                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         1323                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       318050                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests     10943135                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      5471097                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         2877                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       303361                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       302576                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops          785                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       5245531                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      5451346                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        19910                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         1794                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       317966                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp            4                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeReq            3                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::UpgradeResp            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       226523                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       226523                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          912                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244184                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2275                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16411619                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          16413894                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        87232                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    700217984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          700305216                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      319547                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      5791165                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.052881                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.224033                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq       226519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       226519                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          905                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      5244627                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2256                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     16412936                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          16415192                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        86464                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    700274176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          700360640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      319939                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      5791989                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.053010                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.224658                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            5485231     94.72%     94.72% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             305626      5.28%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                308      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            5485738     94.71%     94.71% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             305466      5.27%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                785      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        5791165                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    10941781515                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        5791989                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    10942648515                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization         18.8                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy         6019                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1367498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1357497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    8206066491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    8206724991                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization         14.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              15694                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty          170                       # Transaction distribution
-system.membus.trans_dist::CleanEvict               58                       # Transaction distribution
+system.membus.trans_dist::ReadResp              16175                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty          175                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               63                       # Transaction distribution
 system.membus.trans_dist::UpgradeReq                4                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               340                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              340                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         15695                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        32301                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  32301                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1037056                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1037056                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq               341                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              341                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         16176                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        33275                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  33275                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1068224                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1068224                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             16267                       # Request fanout histogram
+system.membus.snoop_fanout::samples             16759                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   16267    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   16759    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               16267                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            26872796                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               16759                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            27529285                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           83907066                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           86434816                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 63290598f..d813cd17b 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,75 +1,75 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.061602                       # Number of seconds simulated
-sim_ticks                                 61602281500                       # Number of ticks simulated
-final_tick                                61602281500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.065987                       # Number of seconds simulated
+sim_ticks                                 65986743500                       # Number of ticks simulated
+final_tick                                65986743500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60207                       # Simulator instruction rate (inst/s)
-host_op_rate                                   106015                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               23475786                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 445092                       # Number of bytes of host memory used
-host_seconds                                  2624.08                       # Real time elapsed on the host
+host_inst_rate                                 126294                       # Simulator instruction rate (inst/s)
+host_op_rate                                   222383                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               52748930                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 414760                       # Number of bytes of host memory used
+host_seconds                                  1250.96                       # Real time elapsed on the host
 sim_insts                                   157988547                       # Number of instructions simulated
 sim_ops                                     278192464                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             63872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1883072                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1946944                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        63872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           63872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        12160                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             12160                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                998                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29423                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30421                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             190                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  190                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1036845                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             30568218                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                31605063                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1036845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1036845                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            197395                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 197395                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            197395                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1036845                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            30568218                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               31802458                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         30421                       # Number of read requests accepted
-system.physmem.writeReqs                          190                       # Number of write requests accepted
-system.physmem.readBursts                       30421                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                        190                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  1941440                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      5504                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                     10240                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   1946944                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                  12160                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                       86                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       1                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst             69440                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1890368                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1959808                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        69440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           69440                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        17920                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             17920                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1085                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29537                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30622                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             280                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  280                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1052333                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             28647693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                29700026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1052333                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1052333                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            271570                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 271570                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            271570                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1052333                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            28647693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               29971596                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         30622                       # Number of read requests accepted
+system.physmem.writeReqs                          280                       # Number of write requests accepted
+system.physmem.readBursts                       30622                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                        280                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  1952768                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      7040                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                     16064                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   1959808                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                  17920                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      110                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1928                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                2059                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                2023                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                1928                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                2025                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                1901                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                1952                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                1864                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                1938                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                1931                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               1804                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1932                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                2084                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                2041                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                1935                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                2086                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                1909                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                1974                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                1865                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                1948                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                1940                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               1806                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               1794                       # Per bank write bursts
 system.physmem.perBankRdBursts::12               1792                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               1800                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               1818                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               1778                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               1799                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               1828                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               1779                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                  10                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                  78                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                   7                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                  28                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                   6                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                   7                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                 107                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                  30                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                  12                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                  60                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                   8                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                  16                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
@@ -82,26 +82,26 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     61602096500                       # Total gap between requests
+system.physmem.totGap                     65986546500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   30421                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   30622                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                    190                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     29853                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       380                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        14                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                    280                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     29999                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       397                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        88                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        22                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         5                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                        9                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                       14                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,322 +193,331 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         2721                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      716.466005                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     515.355667                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     387.992511                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            365     13.41%     13.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          230      8.45%     21.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          123      4.52%     26.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          120      4.41%     30.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           92      3.38%     34.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          132      4.85%     39.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          112      4.12%     43.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           67      2.46%     45.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         1480     54.39%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           2721                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples             9                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean      3363.666667                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev    10055.376646                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023              8     88.89%     88.89% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719            1     11.11%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total               9                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples             9                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.777778                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.765969                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.666667                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16                  1     11.11%     11.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                  8     88.89%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total               9                       # Writes before turning the bus around for reads
-system.physmem.totQLat                      133021500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 701802750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    151675000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        4385.08                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         2831                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      694.731190                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     483.360902                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     396.952113                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            443     15.65%     15.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          258      9.11%     24.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          108      3.81%     28.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          115      4.06%     32.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          113      3.99%     36.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          115      4.06%     40.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          137      4.84%     45.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           80      2.83%     48.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         1462     51.64%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           2831                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples            14                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean      2175.285714                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       28.380874                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     8064.070078                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023             13     92.86%     92.86% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719            1      7.14%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total              14                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples            14                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.928571                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.918266                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.615728                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16                  1      7.14%      7.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                 12     85.71%     92.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  1      7.14%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total              14                       # Writes before turning the bus around for reads
+system.physmem.totQLat                      136557750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 708657750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    152560000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        4475.54                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  23135.08                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          31.52                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           0.17                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       31.61                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        0.20                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  23225.54                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          29.59                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           0.24                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       29.70                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        0.27                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.25                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.25                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.23                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.23                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        15.67                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      27658                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                       106                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   91.18                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  56.08                       # Row buffer hit rate for writes
-system.physmem.avgGap                      2012416.99                       # Average gap between requests
-system.physmem.pageHitRate                      90.96                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   10924200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    5960625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 121984200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                   984960                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4023218160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2835924705                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            34470717000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              41469713850                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              673.239327                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    57330547250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2056860000                       # Time in different power states
+system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        14.53                       # Average write queue length when enqueuing
+system.physmem.readRowHits                      27745                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                       178                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   90.93                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  63.57                       # Row buffer hit rate for writes
+system.physmem.avgGap                      2135348.73                       # Average gap between requests
+system.physmem.pageHitRate                      90.68                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   11551680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    6303000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 123130800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                  1574640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             4309537440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3035388510                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            36925944000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              44413430070                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              673.125124                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    61414409250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2203240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      2211196750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      2364289750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    9608760                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    5242875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 114199800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    9805320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    5350125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 114441600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                    51840                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4023218160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3020047245                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            34309197750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              41481566430                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              673.431898                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    57061053250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2056860000                       # Time in different power states
+system.physmem_1.refreshEnergy             4309537440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3171429270                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            36806601750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              44417217345                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              673.182663                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    61216839000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2203240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      2480893250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      2563655500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                36908905                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          36908905                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            741640                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             21094596                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21013333                       # Number of BTB hits
+system.cpu.branchPred.lookups                40828848                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          40828848                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           1470674                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             26813424                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             99.614769                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 5443330                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               4414                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6079027                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              92484                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        26813424                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           21202389                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses          5611035                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       566146                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        123204564                       # number of cpu cycles simulated
+system.cpu.numCycles                        131973488                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           27815555                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      199030250                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    36908905                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           26456663                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      94541896                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1553195                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  366                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          5275                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           14                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.CacheLines                  27443897                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                182895                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          123139703                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.847279                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.366421                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           30825655                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      222121094                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    40828848                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           27281416                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      99433771                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 3060135                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        329                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 6280                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        112427                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles           56                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          115                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  29997924                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                374431                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       8                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          131908700                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.964131                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.412100                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 62945303     51.12%     51.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3649645      2.96%     54.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3480674      2.83%     56.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5913881      4.80%     61.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  7544216      6.13%     67.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5413971      4.40%     72.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  3251108      2.64%     74.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2020095      1.64%     76.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 28920810     23.49%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 65727022     49.83%     49.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4068693      3.08%     52.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  3626407      2.75%     55.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  6133247      4.65%     60.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  7782444      5.90%     66.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5574161      4.23%     70.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  3387073      2.57%     73.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2926863      2.22%     75.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 32682790     24.78%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            123139703                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.299574                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.615445                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 12941515                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              63708297                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  35887575                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9825719                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 776597                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              331225446                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                 776597                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 18253426                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8529207                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          16791                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  40202725                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              55360957                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              325142954                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1786                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 778303                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               48626694                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4947433                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           327068188                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             863737810                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        532004029                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               425                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            131908700                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.309372                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.683074                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 15512553                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              64273138                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  40712149                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9880793                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1530067                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              365468602                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                1530067                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 21068463                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                11448631                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          17559                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  44736331                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              53107649                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              355543189                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 24245                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 799476                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               46595900                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4792588                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           358065930                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             942303414                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        580264608                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             22491                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             279212747                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 47855441                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                492                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            490                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  66412323                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            105336194                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            36169392                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          49401722                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          8500449                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  322301392                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2340                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 306103027                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             45906                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        44111268                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     63882734                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           1895                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     123139703                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.485819                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.139102                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 78853183                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                501                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            500                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  64461317                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            113156478                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            38725561                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          51813945                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9109294                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  346336448                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                4423                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 319025181                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            175223                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        68148407                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    106206343                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           3978                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     131908700                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.418530                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.165753                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            30259811     24.57%     24.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19566759     15.89%     40.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            16687041     13.55%     54.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17331203     14.07%     68.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            14759381     11.99%     80.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            12567446     10.21%     90.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             6273248      5.09%     95.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3904177      3.17%     98.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1790637      1.45%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            35712645     27.07%     27.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            20185531     15.30%     42.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17171104     13.02%     55.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17670057     13.40%     68.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            15380757     11.66%     80.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            12917935      9.79%     90.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             6743014      5.11%     95.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             4104772      3.11%     98.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             2022885      1.53%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       123139703                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       131908700                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  338800      8.53%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                3433517     86.49%     95.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                197610      4.98%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  364922      8.93%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      8.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                3529438     86.37%     95.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                191983      4.70%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass             33341      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             174121950     56.88%     56.89% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                11182      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                   343      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.90% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             98066351     32.04%     88.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            33869829     11.06%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass             33340      0.01%      0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             182585704     57.23%     57.24% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                11686      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                   478      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 321      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     57.25% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            101596397     31.85%     89.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34797255     10.91%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              306103027                       # Type of FU issued
-system.cpu.iq.rate                           2.484510                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3969927                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012969                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          739361233                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         366454635                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    304282658                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 357                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                618                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          133                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              310039433                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     180                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         58196288                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              319025181                       # Type of FU issued
+system.cpu.iq.rate                           2.417343                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     4086343                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012809                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          774202119                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         414517759                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    314637932                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               18509                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              33754                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses         4413                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              323069884                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    8300                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         57418928                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     14556809                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        63678                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        41328                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      4729640                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     22377093                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        67905                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        65034                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      7285809                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3641                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        141544                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         4034                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        140997                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 776597                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5329160                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               3100599                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           322303732                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             76830                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             105336194                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             36169392                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1101                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   2588                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3102623                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          41328                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         371679                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       414776                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               786455                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             305156727                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              97750586                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            946300                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1530067                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 8343953                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               3020633                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           346340871                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            136261                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             113156478                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             38725561                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1825                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   2944                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               3026950                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          65034                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         548248                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1104057                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1652305                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             316487526                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             100816589                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2537655                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    131430384                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31401849                       # Number of branches executed
-system.cpu.iew.exec_stores                   33679798                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.476830                       # Inst execution rate
-system.cpu.iew.wb_sent                      304565843                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     304282791                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 230213909                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 333860423                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.469736                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.689551                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        44209690                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                    135188403                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 32185799                       # Number of branches executed
+system.cpu.iew.exec_stores                   34371814                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.398114                       # Inst execution rate
+system.cpu.iew.wb_sent                      315304152                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     314642345                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 238446717                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 344411432                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       2.384133                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.692331                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        68273083                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             445                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            742008                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    117118936                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.375299                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.092759                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1477187                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    122118176                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.278059                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.046851                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     52925822     45.19%     45.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     15815600     13.50%     58.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     10978628      9.37%     68.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8749337      7.47%     75.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1860126      1.59%     77.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1720772      1.47%     78.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       865935      0.74%     79.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       690105      0.59%     79.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     23512611     20.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     56957157     46.64%     46.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16546673     13.55%     60.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     11180219      9.16%     69.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      8765216      7.18%     76.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2116572      1.73%     78.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1764817      1.45%     79.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       934979      0.77%     80.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       730886      0.60%     81.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     23121657     18.93%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    117118936                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    122118176                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
 system.cpu.commit.committedOps              278192464                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -554,340 +563,337 @@ system.cpu.commit.op_class_0::MemWrite       31439752     11.30%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         278192464                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              23512611                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    416008479                       # The number of ROB reads
-system.cpu.rob.rob_writes                   650833820                       # The number of ROB writes
-system.cpu.timesIdled                             568                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           64861                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              23121657                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    445462066                       # The number of ROB reads
+system.cpu.rob.rob_writes                   702797421                       # The number of ROB writes
+system.cpu.timesIdled                             887                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           64788                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
 system.cpu.committedOps                     278192464                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.779832                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.779832                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.282327                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.282327                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                491477136                       # number of integer regfile reads
-system.cpu.int_regfile_writes               239432261                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       110                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       84                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 107533030                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 64416979                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               195275946                       # number of misc regfile reads
+system.cpu.cpi                               0.835336                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.835336                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.197123                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.197123                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                504041942                       # number of integer regfile reads
+system.cpu.int_regfile_writes               248656420                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      4180                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      782                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 109261684                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 65602098                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               202573497                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2072312                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4068.008256                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            68071038                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2076408                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             32.783074                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle       19455459500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4068.008256                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993166                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993166                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2073508                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4068.413497                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            71894591                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2077604                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             34.604569                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle       21372047500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4068.413497                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993265                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993265                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          633                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         3336                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          127                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          542                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         3404                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         143788642                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        143788642                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     36725212                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        36725212                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31345825                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31345825                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      68071037                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         68071037                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     68071037                       # number of overall hits
-system.cpu.dcache.overall_hits::total        68071037                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2691153                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2691153                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        93927                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        93927                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2785080                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2785080                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2785080                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2785080                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  32304195500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  32304195500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2956614994                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2956614994                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35260810494                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35260810494                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35260810494                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35260810494                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     39416365                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     39416365                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         151442194                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        151442194                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     40548572                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        40548572                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31346019                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31346019                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      71894591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         71894591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     71894591                       # number of overall hits
+system.cpu.dcache.overall_hits::total        71894591                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2693971                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2693971                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        93733                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        93733                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2787704                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2787704                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2787704                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2787704                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  32332975500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  32332975500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2952822993                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2952822993                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35285798493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35285798493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35285798493                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35285798493                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     43242543                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     43242543                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439752                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439752                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     70856117                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     70856117                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     70856117                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     70856117                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.068275                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.068275                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002988                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.002988                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.039306                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.039306                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039306                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039306                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.849465                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.849465                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.796523                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.796523                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.609567                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12660.609567                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.609567                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12660.609567                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs       221476                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             43220                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.124387                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     74682295                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     74682295                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     74682295                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     74682295                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.062299                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.062299                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002981                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.002981                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037328                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037328                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037328                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037328                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12657.656083                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12657.656083                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs       219202                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets          497                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             43207                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               4                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.073298                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   124.250000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2066601                       # number of writebacks
-system.cpu.dcache.writebacks::total           2066601                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       696788                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       696788                       # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      2066969                       # number of writebacks
+system.cpu.dcache.writebacks::total           2066969                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       698217                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       698217                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data        11883                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total        11883                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       708671                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       708671                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       708671                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       708671                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994365                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994365                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82044                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82044                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076409                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076409                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076409                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076409                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24195923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24195923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2799396995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2799396995                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  26995319995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  26995319995                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  26995319995                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  26995319995                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.050597                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.050597                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002610                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002610                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.029305                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.029305                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.029305                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.029305                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.143815                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.143815                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13000.964644                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13000.964644                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13000.964644                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13000.964644                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data       710100                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       710100                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       710100                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       710100                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1995754                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1995754                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        81850                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        81850                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2077604                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2077604                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2077604                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2077604                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24221413500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24221413500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2795777993                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2795777993                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27017191493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  27017191493                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27017191493                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27017191493                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.046153                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.046153                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002603                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002603                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027819                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.027819                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027819                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.027819                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements                53                       # number of replacements
-system.cpu.icache.tags.tagsinuse           825.039758                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            27442574                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1013                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          27090.398815                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements                93                       # number of replacements
+system.cpu.icache.tags.tagsinuse           870.928206                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            29996478                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1113                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          26951.013477                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   825.039758                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.402851                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.402851                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          960                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   870.928206                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.425258                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.425258                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1020                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          870                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.468750                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          54888808                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         54888808                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     27442574                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27442574                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27442574                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27442574                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27442574                       # number of overall hits
-system.cpu.icache.overall_hits::total        27442574                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1323                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1323                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1323                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1323                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1323                       # number of overall misses
-system.cpu.icache.overall_misses::total          1323                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     97204000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     97204000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     97204000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     97204000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     97204000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     97204000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27443897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27443897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27443897                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27443897                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27443897                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27443897                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           34                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          906                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.498047                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          59996959                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         59996959                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     29996478                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        29996478                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      29996478                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         29996478                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     29996478                       # number of overall hits
+system.cpu.icache.overall_hits::total        29996478                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1445                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1445                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1445                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1445                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1445                       # number of overall misses
+system.cpu.icache.overall_misses::total          1445                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    106088999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    106088999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    106088999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    106088999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    106088999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    106088999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     29997923                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     29997923                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     29997923                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     29997923                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     29997923                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     29997923                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000048                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000048                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000048                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000048                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000048                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000048                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73472.411187                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 73472.411187                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 73472.411187                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 73472.411187                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 73472.411187                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 73472.411187                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73417.992388                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 73417.992388                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 73417.992388                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 73417.992388                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 73417.992388                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          515                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    46.818182                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks           53                       # number of writebacks
-system.cpu.icache.writebacks::total                53                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          309                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          309                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          309                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          309                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          309                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          309                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1014                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1014                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1014                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1014                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1014                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1014                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     77418000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     77418000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     77418000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     77418000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     77418000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     77418000                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks           93                       # number of writebacks
+system.cpu.icache.writebacks::total                93                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          332                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          332                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          332                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          332                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          332                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          332                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1113                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1113                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1113                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1113                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1113                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1113                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     84684499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     84684499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     84684499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     84684499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     84684499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     84684499                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000037                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000037                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000037                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000037                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76349.112426                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76349.112426                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76349.112426                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76349.112426                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76349.112426                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76349.112426                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements              493                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        20711.322176                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            4035102                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs            30410                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           132.689970                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements              650                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        20606.403574                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            4037654                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs            30622                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           131.854680                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 19791.559632                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   674.841856                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   244.920687                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.603990                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.020595                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.007474                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.632059                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29917                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          782                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1386                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27622                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.912994                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         33310456                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        33310456                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2066601                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2066601                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks           53                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total           53                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        53071                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        53071                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           16                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           16                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1993914                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1993914                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           16                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2046985                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2047001                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           16                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2046985                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2047001                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data        28998                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        28998                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          998                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          998                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          425                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          425                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          998                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29423                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30421                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          998                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29423                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30421                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2118138000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   2118138000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     75717000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     75717000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     32635000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     32635000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     75717000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   2150773000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   2226490000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     75717000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   2150773000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   2226490000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2066601                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2066601                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks           53                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total           53                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        82069                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        82069                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1014                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         1014                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1994339                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1994339                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1014                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2076408                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2077422                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1014                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2076408                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2077422                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.353337                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.353337                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.984221                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.984221                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000213                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000213                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.984221                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.014170                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.014644                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.984221                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014170                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014644                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73044.278916                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73044.278916                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75868.737475                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75868.737475                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76788.235294                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76788.235294                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75868.737475                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73098.358427                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 73189.244272                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75868.737475                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73098.358427                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 73189.244272                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   710.830105                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   275.118635                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.598769                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.021693                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.008396                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.628858                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29972                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          833                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1405                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        27613                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.914673                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         33330894                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        33330894                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2066969                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2066969                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks           93                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total           93                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        52906                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        52906                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           28                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           28                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1995161                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1995161                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           28                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2048067                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2048095                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           28                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2048067                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2048095                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data        28982                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        28982                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1085                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         1085                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          555                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          555                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1085                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        29537                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         30622                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1085                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        29537                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        30622                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2117059500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2117059500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     82707500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     82707500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     43407000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     43407000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     82707500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   2160466500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   2243174000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     82707500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   2160466500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   2243174000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2066969                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2066969                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks           93                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total           93                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        81888                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        81888                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1113                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         1113                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1995716                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1995716                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1113                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2077604                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2078717                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1113                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2077604                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2078717                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.353922                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.353922                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.974843                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.974843                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.000278                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.000278                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.974843                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.014217                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.014731                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.974843                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.014217                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.014731                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73047.391484                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73047.391484                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76228.110599                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76228.110599                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78210.810811                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78210.810811                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76228.110599                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73144.412093                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 73253.673829                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76228.110599                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73144.412093                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 73253.673829                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -896,123 +902,121 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          190                       # number of writebacks
-system.cpu.l2cache.writebacks::total              190                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28998                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        28998                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          998                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          998                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          425                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          425                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          998                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29423                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30421                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          998                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29423                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30421                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1828158000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1828158000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     65737000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     65737000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     28385000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     28385000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     65737000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1856543000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   1922280000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     65737000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1856543000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   1922280000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.353337                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.353337                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.984221                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.984221                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000213                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000213                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.984221                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014170                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014644                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.984221                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014170                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.014644                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.278916                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.278916                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65868.737475                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65868.737475                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66788.235294                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66788.235294                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.737475                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63098.358427                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63189.244272                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.737475                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63098.358427                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63189.244272                       # average overall mshr miss latency
+system.cpu.l2cache.writebacks::writebacks          280                       # number of writebacks
+system.cpu.l2cache.writebacks::total              280                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28982                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        28982                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1085                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1085                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          555                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          555                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1085                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        29537                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        30622                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1085                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        29537                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        30622                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1827239500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1827239500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     71857500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     71857500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     37857000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     37857000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     71857500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1865096500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1936954000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     71857500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1865096500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1936954000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.353922                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.353922                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.974843                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.974843                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.000278                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.000278                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.974843                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014217                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014731                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.974843                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014217                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.014731                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4149788                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2072369                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests           42                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops          279                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops          279                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      4152318                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2073604                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests           20                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops          325                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops          325                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       1995353                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2066791                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean           53                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict         6014                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        82069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        82069                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         1014                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1994339                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2081                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6225130                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6227211                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        68288                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265152576                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          265220864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         493                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2077916                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000156                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.012505                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp       1996829                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2067249                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean           93                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict         6909                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        81888                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        81888                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1113                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1995716                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2319                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6228716                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6231035                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        77184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    265252672                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          265329856                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         650                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2079367                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000167                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.012936                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2077591     99.98%     99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                325      0.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2079019     99.98%     99.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                348      0.02%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2077916                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4141548000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          6.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1521000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2079367                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4143221000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          6.3                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       1670997                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3114612500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          5.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               1423                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty          190                       # Transaction distribution
-system.membus.trans_dist::CleanEvict               24                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             28998                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            28998                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          1423                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  61056                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1959104                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1959104                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 1959104                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy    3116406000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          4.7                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp               1640                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty          280                       # Transaction distribution
+system.membus.trans_dist::CleanEvict               45                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             28982                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            28982                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          1640                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        61569                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        61569                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  61569                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      1977728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total      1977728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 1977728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             30635                       # Request fanout histogram
+system.membus.snoop_fanout::samples             30947                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   30635    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   30947    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               30635                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            42769000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               30947                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            43483000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          160316500                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          161384500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
index c6f6cfa54..fcf7ab908 100644
--- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,103 +1,103 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.412076                       # Number of seconds simulated
-sim_ticks                                412076211500                       # Number of ticks simulated
-final_tick                               412076211500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.412080                       # Number of seconds simulated
+sim_ticks                                412079966500                       # Number of ticks simulated
+final_tick                               412079966500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 319842                       # Simulator instruction rate (inst/s)
-host_op_rate                                   319842                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              215393213                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301832                       # Number of bytes of host memory used
-host_seconds                                  1913.13                       # Real time elapsed on the host
+host_inst_rate                                 374495                       # Simulator instruction rate (inst/s)
+host_op_rate                                   374495                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              252200387                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254932                       # Number of bytes of host memory used
+host_seconds                                  1633.94                       # Real time elapsed on the host
 sim_insts                                   611901617                       # Number of instructions simulated
 sim_ops                                     611901617                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            156480                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24143168                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24299648                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       156480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          156480                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18790784                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18790784                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2445                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             377237                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                379682                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293606                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293606                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               379736                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             58589085                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                58968820                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          379736                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             379736                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45600264                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45600264                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45600264                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              379736                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            58589085                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              104569084                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        379682                       # Number of read requests accepted
-system.physmem.writeReqs                       293606                       # Number of write requests accepted
-system.physmem.readBursts                      379682                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293606                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24277120                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     22528                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18788736                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24299648                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18790784                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      352                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            156608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24143296                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24299904                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       156608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          156608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18790848                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18790848                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2447                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             377239                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                379686                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          293607                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               293607                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               380043                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             58588861                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                58968904                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          380043                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             380043                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45600004                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45600004                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45600004                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              380043                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            58588861                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              104568908                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        379686                       # Number of read requests accepted
+system.physmem.writeReqs                       293607                       # Number of write requests accepted
+system.physmem.readBursts                      379686                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     293607                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24278080                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     21824                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18789376                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24299904                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18790848                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      341                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               23686                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               23158                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               23442                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24500                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               25445                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23568                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               23655                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               23906                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23193                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23982                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24711                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               23685                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               23156                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               23444                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24498                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               25450                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23569                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               23652                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               23913                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23182                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23988                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24719                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              22783                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23721                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              24390                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              22740                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23722                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              24391                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              22743                       # Per bank write bursts
 system.physmem.perBankRdBursts::15              22450                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               17782                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               17456                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17944                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               18851                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               19513                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               17945                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18853                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               19514                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               18590                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18777                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               18778                       # Per bank write bursts
 system.physmem.perBankWrBursts::7               18659                       # Per bank write bursts
 system.physmem.perBankWrBursts::8               18440                       # Per bank write bursts
 system.physmem.perBankWrBursts::9               18941                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              19255                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18046                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18263                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18731                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17195                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              19257                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18049                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18261                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18732                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17196                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              17131                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    412076123500                       # Total gap between requests
+system.physmem.totGap                    412079864500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  379682                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  379686                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293606                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    377941                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 293607                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    377956                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                      1374                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        15                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
@@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6897                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7266                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    17028                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17389                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17450                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17490                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17475                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17479                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17478                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17534                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17491                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17549                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17546                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17520                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17637                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17354                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       40                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       21                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       18                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        9                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6977                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7349                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16982                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17402                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17456                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17496                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17482                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17480                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17469                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17515                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17450                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17520                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17545                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17504                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17668                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17405                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17352                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       38                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
@@ -193,56 +193,52 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       142335                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      302.556532                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.740913                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     324.275213                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          50726     35.64%     35.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        38947     27.36%     63.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13162      9.25%     72.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         8307      5.84%     78.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5691      4.00%     82.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3798      2.67%     84.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3047      2.14%     86.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2540      1.78%     88.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16117     11.32%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         142335                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17335                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        21.880819                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      236.752171                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17326     99.95%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       142401                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      302.436977                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     179.883041                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     323.731419                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          50699     35.60%     35.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        38890     27.31%     62.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13190      9.26%     72.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         8518      5.98%     78.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5731      4.02%     82.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3813      2.68%     84.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2946      2.07%     86.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2544      1.79%     88.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16070     11.29%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         142401                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17327                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        21.892595                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      236.629202                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17319     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            4      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::28672-29695            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17335                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17335                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.935333                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.864235                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.642113                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17130     98.82%     98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             152      0.88%     99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              27      0.16%     99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               9      0.05%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               6      0.03%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               1      0.01%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59               1      0.01%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63               2      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               2      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-227             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17335                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4058081750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11170519250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1896650000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10698.02                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17327                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17327                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.943729                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.871773                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        3.342990                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-23           17278     99.72%     99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-31              33      0.19%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-39               6      0.03%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-47               2      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-55               2      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-63               2      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-79               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-103              1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-119             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::392-399             1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17327                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4062204500                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11174923250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1896725000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10708.47                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29448.02                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          58.91                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29458.47                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          58.92                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          45.60                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                       58.97                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                       45.60                       # Average system write bandwidth in MiByte/s
@@ -251,71 +247,75 @@ system.physmem.busUtil                           0.82                       # Da
 system.physmem.busUtilRead                       0.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.82                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     314253                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    216307                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.84                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.67                       # Row buffer hit rate for writes
-system.physmem.avgGap                       612035.45                       # Average gap between requests
+system.physmem.avgWrQLen                        21.44                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     314203                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    216323                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   82.83                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.68                       # Row buffer hit rate for writes
+system.physmem.avgGap                       612036.46                       # Average gap between requests
 system.physmem.pageHitRate                      78.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  548334360                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  299190375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1492491000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                956130480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26914520880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            61976871495                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           192877504500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             285065043090                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              691.784602                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   320322978500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13759980000                       # Time in different power states
+system.physmem_0.actEnergy                  547933680                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  298971750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1492662600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                956298960                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            26915029440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            62025350850                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           192839650500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             285075897780                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              691.797872                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   320257941500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     13760240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     77989027750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     78061587250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  527491440                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  287817750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1465854000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                945995760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26914520880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            59032825200                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           195460001250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             284634506280                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              690.739793                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   324635867250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13759980000                       # Time in different power states
+system.physmem_1.actEnergy                  528617880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  288432375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1466212800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                946125360                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            26915029440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            58968919935                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           195520730250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             284634068040                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              690.725678                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   324739070000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     13760240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     73676135250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     73580458750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               123917200                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          87658954                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6214605                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             71577882                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                67272105                       # Number of BTB hits
+system.cpu.branchPred.lookups               123917421                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          87658943                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6214661                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             71578372                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67267052                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.984487                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15041853                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1126020                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             93.976784                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15041989                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1126026                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups            7056                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits               4451                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             2605                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          734                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    149344669                       # DTB read hits
-system.cpu.dtb.read_misses                     549013                       # DTB read misses
+system.cpu.dtb.read_hits                    149344684                       # DTB read hits
+system.cpu.dtb.read_misses                     549067                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                149893682                       # DTB read accesses
-system.cpu.dtb.write_hits                    57319597                       # DTB write hits
-system.cpu.dtb.write_misses                     63704                       # DTB write misses
+system.cpu.dtb.read_accesses                149893751                       # DTB read accesses
+system.cpu.dtb.write_hits                    57319581                       # DTB write hits
+system.cpu.dtb.write_misses                     63710                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                57383301                       # DTB write accesses
-system.cpu.dtb.data_hits                    206664266                       # DTB hits
-system.cpu.dtb.data_misses                     612717                       # DTB misses
+system.cpu.dtb.write_accesses                57383291                       # DTB write accesses
+system.cpu.dtb.data_hits                    206664265                       # DTB hits
+system.cpu.dtb.data_misses                     612777                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                207276983                       # DTB accesses
-system.cpu.itb.fetch_hits                   226051267                       # ITB hits
+system.cpu.dtb.data_accesses                207277042                       # DTB accesses
+system.cpu.itb.fetch_hits                   226050668                       # ITB hits
 system.cpu.itb.fetch_misses                        48                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               226051315                       # ITB accesses
+system.cpu.itb.fetch_accesses               226050716                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -329,66 +329,101 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  485                       # Number of system calls
-system.cpu.numCycles                        824152423                       # number of cpu cycles simulated
+system.cpu.numCycles                        824159933                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   611901617                       # Number of instructions committed
 system.cpu.committedOps                     611901617                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      12834608                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      12834895                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.346871                       # CPI: cycles per instruction
-system.cpu.ipc                               0.742462                       # IPC: instructions per cycle
-system.cpu.tickCycles                       739334528                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        84817895                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           2535265                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.660624                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           202570425                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2539361                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             79.772205                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1635033500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.660624                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997964                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997964                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.346883                       # CPI: cycles per instruction
+system.cpu.ipc                               0.742455                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass            52179272      8.53%      8.53% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               355264620     58.06%     66.59% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 152833      0.02%     66.61% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     66.61% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                144588      0.02%     66.64% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     3      0.00%     66.64% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                369991      0.06%     66.70% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    2      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                  3790      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     66.70% # Class of committed instruction
+system.cpu.op_class_0::MemRead              146565535     23.95%     90.65% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              57220983      9.35%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                611901617                       # Class of committed instruction
+system.cpu.tickCycles                       739333991                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        84825942                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           2535268                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.644038                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           202570428                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2539364                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             79.772111                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1636792500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.644038                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997960                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997960                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           73                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          829                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3         3145                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         414584975                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        414584975                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    146904268                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       146904268                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     55666157                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       55666157                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     202570425                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        202570425                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    202570425                       # number of overall hits
-system.cpu.dcache.overall_hits::total       202570425                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1908505                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1908505                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1543877                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1543877                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3452382                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3452382                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3452382                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3452382                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  37724666000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  37724666000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  47726490500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  47726490500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  85451156500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  85451156500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  85451156500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  85451156500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    148812773                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    148812773                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         414584966                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        414584966                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    146904269                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146904269                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     55666159                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       55666159                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     202570428                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        202570428                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    202570428                       # number of overall hits
+system.cpu.dcache.overall_hits::total       202570428                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1908498                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1908498                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1543875                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1543875                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3452373                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3452373                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3452373                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3452373                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  37718879500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  37718879500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  47736374000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  47736374000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  85455253500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  85455253500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  85455253500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  85455253500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    148812767                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    148812767                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     57210034                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     57210034                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    206022807                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    206022807                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    206022807                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    206022807                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    206022801                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    206022801                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    206022801                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    206022801                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012825                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.012825                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.026986                       # miss rate for WriteReq accesses
@@ -397,14 +432,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.016757
 system.cpu.dcache.demand_miss_rate::total     0.016757                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.016757                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.016757                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19766.605799                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19766.605799                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30913.402104                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30913.402104                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24751.361958                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24751.361958                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24751.361958                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24751.361958                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19763.646333                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19763.646333                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30919.843899                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30919.843899                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24752.613203                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24752.613203                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24752.613203                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24752.613203                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -413,32 +448,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2339407                       # number of writebacks
-system.cpu.dcache.writebacks::total           2339407                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143967                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       143967                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769054                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       769054                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       913021                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       913021                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       913021                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       913021                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764538                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1764538                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      2339413                       # number of writebacks
+system.cpu.dcache.writebacks::total           2339413                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       143957                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       143957                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       769052                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       769052                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       913009                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       913009                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       913009                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       913009                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1764541                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1764541                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data       774823                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       774823                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2539361                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2539361                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2539361                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2539361                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33207035500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33207035500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23344377500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  23344377500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56551413000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  56551413000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56551413000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  56551413000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      2539364                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2539364                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2539364                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2539364                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33202779000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33202779000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23350926000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  23350926000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  56553705000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  56553705000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  56553705000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  56553705000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.011857                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.011857                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.013543                       # mshr miss rate for WriteReq accesses
@@ -447,69 +482,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012326
 system.cpu.dcache.demand_mshr_miss_rate::total     0.012326                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012326                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.012326                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18819.110441                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18819.110441                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.658416                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.658416                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22269.938382                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22269.938382                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22269.938382                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22269.938382                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18816.666204                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18816.666204                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30137.110024                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30137.110024                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22270.814661                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22270.814661                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22270.814661                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22270.814661                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              3156                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1116.812774                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           226046283                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4984                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          45354.390650                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              3158                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1117.678366                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           226045682                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4986                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          45336.077417                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1116.812774                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.545319                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.545319                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1117.678366                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.545741                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.545741                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1828                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           77                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           80                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           17                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3           75                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1590                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.892578                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         452107518                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        452107518                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    226046283                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       226046283                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     226046283                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        226046283                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    226046283                       # number of overall hits
-system.cpu.icache.overall_hits::total       226046283                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4984                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4984                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4984                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4984                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4984                       # number of overall misses
-system.cpu.icache.overall_misses::total          4984                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    231170500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    231170500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    231170500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    231170500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    231170500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    231170500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    226051267                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    226051267                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    226051267                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    226051267                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    226051267                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    226051267                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         452106322                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        452106322                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    226045682                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       226045682                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     226045682                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        226045682                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    226045682                       # number of overall hits
+system.cpu.icache.overall_hits::total       226045682                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4986                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4986                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4986                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4986                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4986                       # number of overall misses
+system.cpu.icache.overall_misses::total          4986                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    233628500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    233628500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    233628500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    233628500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    233628500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    233628500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    226050668                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    226050668                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    226050668                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    226050668                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    226050668                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    226050668                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000022                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46382.524077                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 46382.524077                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 46382.524077                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 46382.524077                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 46382.524077                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 46382.524077                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46856.899318                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 46856.899318                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 46856.899318                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 46856.899318                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 46856.899318                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 46856.899318                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -518,135 +553,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         3156                       # number of writebacks
-system.cpu.icache.writebacks::total              3156                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4984                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4984                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4984                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4984                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4984                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    226186500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    226186500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    226186500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    226186500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    226186500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    226186500                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks         3158                       # number of writebacks
+system.cpu.icache.writebacks::total              3158                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4986                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4986                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4986                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4986                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4986                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4986                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    228642500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    228642500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    228642500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    228642500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    228642500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    228642500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000022                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000022                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45382.524077                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45382.524077                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45382.524077                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 45382.524077                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45382.524077                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 45382.524077                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45856.899318                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45856.899318                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45856.899318                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 45856.899318                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45856.899318                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 45856.899318                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           347699                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29505.280941                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3908745                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           380129                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.282680                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     189125528500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21321.882455                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.938322                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8022.460164                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.650692                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.replacements           347705                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29504.977164                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3908748                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           380135                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.282526                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     189119343500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21322.016390                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   160.931124                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8022.029650                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.650696                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.004911                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.244826                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.900430                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.244813                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.900420                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32430                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          163                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          116                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          122                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          223                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13172                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18756                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.989685                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         41820417                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        41820417                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2339407                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2339407                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         3156                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         3156                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       571850                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       571850                       # number of ReadExReq hits
+system.cpu.l2cache.tags.tag_accesses         41820503                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41820503                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2339413                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2339413                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         3158                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         3158                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       571852                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       571852                       # number of ReadExReq hits
 system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2539                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadCleanReq_hits::total         2539                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590274                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1590274                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1590273                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1590273                       # number of ReadSharedReq hits
 system.cpu.l2cache.demand_hits::cpu.inst         2539                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2162124                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2164663                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2162125                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2164664                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst         2539                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2162124                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2164663                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206310                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206310                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2445                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2445                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       170927                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       170927                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2445                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       377237                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        379682                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2445                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       377237                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       379682                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16220356500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16220356500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    192028500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    192028500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  13781881500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  13781881500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    192028500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  30002238000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  30194266500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    192028500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  30002238000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  30194266500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2339407                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2339407                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         3156                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         3156                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.overall_hits::cpu.data      2162125                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2164664                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206308                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206308                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2447                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2447                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       170931                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       170931                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2447                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       377239                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        379686                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2447                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       377239                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       379686                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16226611500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16226611500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    194481500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    194481500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  13777909500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  13777909500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    194481500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30004521000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30199002500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    194481500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30004521000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30199002500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2339413                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2339413                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         3158                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         3158                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data       778160                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total       778160                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4984                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         4984                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1761201                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1761201                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4984                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2539361                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2544345                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4984                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2539361                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2544345                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.265125                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.265125                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.490570                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.490570                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.097051                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.097051                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.490570                       # miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4986                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4986                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1761204                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1761204                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4986                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2539364                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2544350                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4986                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2539364                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2544350                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.265123                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.265123                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.490774                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.490774                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.097053                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.097053                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.490774                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.148556                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.149226                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.490570                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.149227                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.490774                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.148556                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.149226                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78621.281082                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78621.281082                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78539.263804                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78539.263804                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80630.219333                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80630.219333                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78539.263804                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.535878                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79525.146043                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78539.263804                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.535878                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79525.146043                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.149227                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78652.362002                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78652.362002                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79477.523498                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79477.523498                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80605.095038                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80605.095038                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79477.523498                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79537.166094                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79536.781709                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79477.523498                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79537.166094                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79536.781709                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -655,123 +690,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       293606                       # number of writebacks
-system.cpu.l2cache.writebacks::total           293606                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            4                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            4                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206310                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206310                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2445                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2445                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       170927                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       170927                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2445                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       377237                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       379682                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2445                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       377237                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       379682                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14157256500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14157256500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    167578500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    167578500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12072611500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12072611500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    167578500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26229868000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  26397446500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    167578500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26229868000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26397446500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks       293607                       # number of writebacks
+system.cpu.l2cache.writebacks::total           293607                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            5                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            5                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206308                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206308                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2447                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2447                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       170931                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       170931                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2447                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       377239                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       379686                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2447                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       377239                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       379686                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14163531500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14163531500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    170011500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    170011500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12068599500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12068599500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    170011500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26232131000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  26402142500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    170011500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26232131000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  26402142500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.265125                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265125                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.490570                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.490570                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.097051                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.097051                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.490570                       # mshr miss rate for demand accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.265123                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.265123                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.490774                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.490774                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.097053                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.097053                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.490774                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.148556                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.149226                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.490570                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.149227                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.490774                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.148556                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.149226                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68621.281082                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68621.281082                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68539.263804                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68539.263804                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70630.219333                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70630.219333                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68539.263804                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.535878                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69525.146043                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68539.263804                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.535878                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69525.146043                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.149227                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68652.362002                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68652.362002                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69477.523498                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69477.523498                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70605.095038                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70605.095038                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69477.523498                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69537.166094                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69536.781709                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69477.523498                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69537.166094                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69536.781709                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5082766                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538421                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      5082776                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2538426                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2391                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2391                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2394                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2394                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       1766185                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2633013                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         3156                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       249951                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       1766190                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2633020                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         3158                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       249953                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq       778160                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp       778160                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4984                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761201                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13124                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7613987                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           7627111                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       520960                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312241152                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312762112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      347699                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2892044                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000827                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.028741                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4986                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1761204                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13130                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7613996                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7627126                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       521216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312241728                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          312762944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      347705                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2892055                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000828                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.028759                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2889653     99.92%     99.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2391      0.08%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2889661     99.92%     99.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2394      0.08%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2892044                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4883946000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        2892055                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4883959000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7476000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7479000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3809041500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    3809046000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             173372                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       293606                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            51706                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206310                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206310                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        173372                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1104676                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1104676                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43090432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43090432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             173378                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       293607                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            51709                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206308                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206308                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        173378                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1104688                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1104688                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43090752                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43090752                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            724994                       # Request fanout histogram
+system.membus.snoop_fanout::samples            725002                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  724994    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  725002    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              724994                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2020992000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              725002                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2021006000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2009252250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2009290500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
index 415eb183d..6a1fec128 100644
--- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
@@ -1,103 +1,103 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.363609                       # Number of seconds simulated
-sim_ticks                                363608804500                       # Number of ticks simulated
-final_tick                               363608804500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.362632                       # Number of seconds simulated
+sim_ticks                                362631828500                       # Number of ticks simulated
+final_tick                               362631828500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 100066                       # Simulator instruction rate (inst/s)
-host_op_rate                                   108385                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               71824585                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304984                       # Number of bytes of host memory used
-host_seconds                                  5062.46                       # Real time elapsed on the host
+host_inst_rate                                 285981                       # Simulator instruction rate (inst/s)
+host_op_rate                                   309756                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              204718125                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275016                       # Number of bytes of host memory used
+host_seconds                                  1771.37                       # Real time elapsed on the host
 sim_insts                                   506579366                       # Number of instructions simulated
 sim_ops                                     548692589                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            179584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9028480                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9208064                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       179584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          179584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6218624                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6218624                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2806                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141070                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                143876                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97166                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97166                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               493893                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             24830202                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                25324095                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          493893                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             493893                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          17102512                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               17102512                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          17102512                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              493893                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            24830202                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42426607                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        143876                       # Number of read requests accepted
-system.physmem.writeReqs                        97166                       # Number of write requests accepted
-system.physmem.readBursts                      143876                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97166                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9201472                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      6592                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6217344                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9208064                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6218624                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      103                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            179456                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9032064                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9211520                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       179456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          179456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6221440                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6221440                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2804                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             141126                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                143930                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97210                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97210                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               494871                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             24906981                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                25401852                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          494871                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             494871                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          17156354                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               17156354                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          17156354                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              494871                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            24906981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               42558206                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        143930                       # Number of read requests accepted
+system.physmem.writeReqs                        97210                       # Number of write requests accepted
+system.physmem.readBursts                      143930                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97210                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9204736                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      6784                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6219456                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9211520                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6221440                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      106                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9345                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8917                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                8955                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8654                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                9386                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                9354                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                8955                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8104                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                8603                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                8629                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               8742                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9406                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8921                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                8949                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8657                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                9384                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                9355                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                8962                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8101                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                8596                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                8628                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               8740                       # Per bank write bursts
 system.physmem.perBankRdBursts::11               9454                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               9335                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               9509                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8712                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9119                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                6212                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6095                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6031                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               9340                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               9510                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               8709                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9112                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                6249                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6105                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6032                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                5882                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6240                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6242                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6046                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5509                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5790                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5862                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               5980                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6237                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6240                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6051                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5508                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5781                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5861                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               5978                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               6494                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6352                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6321                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               5998                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6092                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6355                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6320                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6000                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               6086                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    363608778500                       # Total gap between requests
+system.physmem.totGap                    362631802500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  143876                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  143930                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97166                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    143433                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97210                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    143484                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::1                       320                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        20                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
@@ -144,34 +144,34 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     2923                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     3110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     5563                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5694                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5686                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5706                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5721                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5699                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5724                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     2964                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     3137                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     5566                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5692                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5699                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5703                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5710                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     5731                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5734                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5738                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5678                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5681                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5643                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5621                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       11                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5739                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5733                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5740                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5717                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5686                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5636                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5622                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
@@ -193,109 +193,112 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        65427                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      235.654638                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     156.256012                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     241.782834                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          24843     37.97%     37.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        18425     28.16%     66.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         6952     10.63%     76.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7899     12.07%     88.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2020      3.09%     91.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1104      1.69%     93.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          778      1.19%     94.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          662      1.01%     95.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         2744      4.19%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          65427                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5612                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.618496                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      380.574654                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5610     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        65461                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      235.617299                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     156.242018                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     241.589954                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          24858     37.97%     37.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        18413     28.13%     66.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         6961     10.63%     76.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7914     12.09%     88.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2009      3.07%     91.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1136      1.74%     93.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          792      1.21%     94.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          657      1.00%     95.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         2721      4.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          65461                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5611                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        25.630191                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      380.618779                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5609     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5612                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5612                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.310406                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.214262                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.369355                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17            2682     47.79%     47.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19            2777     49.48%     97.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21              56      1.00%     98.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23              33      0.59%     98.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25              17      0.30%     99.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27              10      0.18%     99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29               7      0.12%     99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31               5      0.09%     99.55% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33               7      0.12%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35               4      0.07%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37               3      0.05%     99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-41               2      0.04%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43               4      0.07%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-49               1      0.02%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50-51               1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-53               1      0.02%     99.96% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total            5611                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5611                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.319373                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.223479                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.351913                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-17            2643     47.10%     47.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18-19            2820     50.26%     97.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-21              52      0.93%     98.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22-23              28      0.50%     98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-25              21      0.37%     99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26-27               8      0.14%     99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-29               6      0.11%     99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30-31               9      0.16%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-33               4      0.07%     99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34-35               6      0.11%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-37               5      0.09%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-41               1      0.02%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42-43               3      0.05%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-45               2      0.04%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::70-71               1      0.02%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::72-73               1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::98-99               1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5612                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1539890250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4235634000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    718865000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10710.57                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::90-91               1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5611                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1538291500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4234991500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    719120000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10695.65                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29460.57                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          25.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          17.10                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       25.32                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       17.10                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29445.65                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          25.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          17.15                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       25.40                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       17.16                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.20                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.13                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        19.45                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     110770                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     64716                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   77.05                       # Row buffer hit rate for reads
+system.physmem.avgWrQLen                        19.56                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     110801                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     64737                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   77.04                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  66.60                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1508487.23                       # Average gap between requests
+system.physmem.avgGap                      1503822.69                       # Average gap between requests
 system.physmem.pageHitRate                      72.83                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  249041520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  135885750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 558807600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                312407280                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            23748734880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            47272879035                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           176694091500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             248971847565                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              684.736255                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   293641319750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     12141480000                       # Time in different power states
+system.physmem_0.actEnergy                  249185160                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  135964125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 559455000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                312906240                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            23685164880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            47417547600                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           175983265500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             248343488505                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              684.841129                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   292457177000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     12108980000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     57820495250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     58063198250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  245269080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  133827375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 562192800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                  245586600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  134000625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 562138200                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                316684080                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            23748734880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            46853247600                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           177062189250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             248922145065                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              684.599560                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   294255473500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     12141480000                       # Time in different power states
+system.physmem_1.refreshEnergy            23685164880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            46768401675                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           176552684250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             248264660310                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              684.623774                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   293406599500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     12108980000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     57206580500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     57113763250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               131890227                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          98029520                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6134595                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             68518889                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                64416393                       # Number of BTB hits
+system.cpu.branchPred.lookups               131880511                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          98032974                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5909980                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             68420287                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                60518878                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.012606                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9980436                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              18277                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             88.451658                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 9982385                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              18500                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         3889648                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            3881527                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             8121                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        53795                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -414,98 +417,133 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        727217609                       # number of cpu cycles simulated
+system.cpu.numCycles                        725263657                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   506579366                       # Number of instructions committed
 system.cpu.committedOps                     548692589                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      13188504                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      12911806                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.435545                       # CPI: cycles per instruction
-system.cpu.ipc                               0.696599                       # IPC: instructions per cycle
-system.cpu.tickCycles                       690736700                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        36480909                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           1141376                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.790078                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           171162589                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1145472                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            149.425380                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.431688                       # CPI: cycles per instruction
+system.cpu.ipc                               0.698476                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               375609862     68.46%     68.46% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 339219      0.06%     68.52% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                3      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     68.52% # Class of committed instruction
+system.cpu.op_class_0::MemRead              115883283     21.12%     89.64% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              56860222     10.36%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                548692589                       # Class of committed instruction
+system.cpu.tickCycles                       688919604                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        36344053                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           1141477                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.722142                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           170992714                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1145573                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            149.263918                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        4896334500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.790078                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993845                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993845                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.722142                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993829                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993829                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          551                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3500                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          553                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3497                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         346584178                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        346584178                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114644865                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114644865                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     53537898                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       53537898                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2744                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2744                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         346245015                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        346245015                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114475063                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114475063                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     53537828                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53537828                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2741                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2741                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168182763                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168182763                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168185507                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168185507                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       855598                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        855598                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       701151                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       701151                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data           15                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total           15                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      1556749                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1556749                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1556764                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1556764                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14056066500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14056066500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21917357000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21917357000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35973423500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35973423500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35973423500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35973423500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    115500463                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    115500463                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     168012891                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168012891                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168015632                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168015632                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       855770                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        855770                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       701221                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       701221                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data           16                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total           16                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data      1556991                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1556991                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1557007                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1557007                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14058873500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14058873500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21921294000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21921294000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35980167500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35980167500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35980167500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35980167500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    115330833                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    115330833                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2759                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2759                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2757                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2757                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    169739512                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    169739512                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    169742271                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    169742271                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007408                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.007408                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012927                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.012927                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005437                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.005437                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009171                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009171                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009171                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009171                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.353619                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.353619                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31259.111090                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31259.111090                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.043429                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23108.043429                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23107.820774                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23107.820774                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    169569882                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    169569882                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    169572639                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    169572639                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007420                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.007420                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.012928                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.012928                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.005803                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.005803                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009182                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009182                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009182                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009182                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23108.783224                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23108.545755                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -514,111 +552,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1069283                       # number of writebacks
-system.cpu.dcache.writebacks::total           1069283                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66543                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        66543                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344746                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       344746                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       411289                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       411289                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       411289                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       411289                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       789055                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       789055                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356405                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       356405                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           12                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total           12                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1145460                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1145460                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1145472                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1145472                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12372636000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12372636000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11132196500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  11132196500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       944000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       944000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23504832500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  23504832500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23505776500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  23505776500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006832                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006832                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006571                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006571                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004349                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004349                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006748                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006748                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006748                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006748                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15680.321397                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15680.321397                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31234.681051                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31234.681051                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78666.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78666.666667                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20519.994151                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20519.994151                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20520.603297                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20520.603297                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1069336                       # number of writebacks
+system.cpu.dcache.writebacks::total           1069336                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        66650                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        66650                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       344781                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       344781                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       411431                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       411431                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       411431                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       411431                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       789120                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       789120                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356440                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       356440                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           13                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total           13                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1145560                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1145560                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1145573                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1145573                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12372328000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12372328000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11135047500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  11135047500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1042000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1042000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  23507375500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  23507375500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  23508417500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  23508417500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006842                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006842                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006572                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006572                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.004715                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.004715                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006756                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006756                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006756                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006756                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             17687                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1188.299437                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           199347924                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             19559                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          10192.132727                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             18130                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1186.413401                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           198770599                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             20001                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           9938.033048                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1188.299437                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.580224                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.580224                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1872                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1186.413401                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.579303                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.579303                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1871                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           59                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          305                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1404                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.914062                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         398754525                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        398754525                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    199347924                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       199347924                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     199347924                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        199347924                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    199347924                       # number of overall hits
-system.cpu.icache.overall_hits::total       199347924                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        19559                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         19559                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        19559                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          19559                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        19559                       # number of overall misses
-system.cpu.icache.overall_misses::total         19559                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    449446000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    449446000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    449446000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    449446000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    449446000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    449446000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    199367483                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    199367483                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    199367483                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    199367483                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    199367483                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    199367483                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000098                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000098                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000098                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000098                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000098                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000098                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22978.986656                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22978.986656                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22978.986656                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22978.986656                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22978.986656                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22978.986656                       # average overall miss latency
+system.cpu.icache.tags.age_task_id_blocks_1024::2           58                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          312                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1397                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.913574                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         397601201                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        397601201                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    198770599                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       198770599                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     198770599                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        198770599                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    198770599                       # number of overall hits
+system.cpu.icache.overall_hits::total       198770599                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        20001                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         20001                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        20001                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          20001                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        20001                       # number of overall misses
+system.cpu.icache.overall_misses::total         20001                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    455038500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    455038500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    455038500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    455038500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    455038500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    455038500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    198790600                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    198790600                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    198790600                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    198790600                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    198790600                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    198790600                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000101                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000101                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000101                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000101                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000101                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000101                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 22750.787461                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 22750.787461                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -627,134 +665,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        17687                       # number of writebacks
-system.cpu.icache.writebacks::total             17687                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19559                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        19559                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        19559                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        19559                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        19559                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        19559                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    429887000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    429887000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    429887000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    429887000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    429887000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    429887000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000098                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000098                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000098                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21978.986656                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21978.986656                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21978.986656                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21978.986656                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21978.986656                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21978.986656                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        18130                       # number of writebacks
+system.cpu.icache.writebacks::total             18130                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        20001                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        20001                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        20001                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        20001                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        20001                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        20001                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    435037500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    435037500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    435037500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    435037500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    435037500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    435037500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000101                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000101                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000101                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000101                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           112304                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        27637.803257                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1771245                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           143514                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            12.341967                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     163256914000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 23514.215736                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   307.353699                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  3816.233823                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.717597                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009380                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.116462                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.843439                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31210                       # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements           112376                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        27628.930561                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1772118                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           143588                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            12.341686                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     163251686000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   308.787313                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  3819.558908                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.717181                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.009423                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.116564                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.843168                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31212                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          321                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4944                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25846                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.952454                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         19053033                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        19053033                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      1069283                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      1069283                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        17449                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        17449                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       255738                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       255738                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        16752                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        16752                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       748650                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       748650                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        16752                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1004388                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         1021140                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        16752                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1004388                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        1021140                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       100917                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       100917                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2807                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2807                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        40167                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        40167                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2807                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       141084                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        143891                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2807                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       141084                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       143891                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7914773500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7914773500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    223970500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    223970500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3305851000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   3305851000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    223970500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  11220624500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  11444595000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    223970500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  11220624500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  11444595000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      1069283                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      1069283                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        17449                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        17449                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       356655                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       356655                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        19559                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        19559                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       788817                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       788817                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        19559                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1145472                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      1165031                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        19559                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1145472                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      1165031                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.282954                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.282954                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.143514                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.143514                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050921                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050921                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.143514                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.123167                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.123508                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.143514                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.123167                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.123508                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78428.545240                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78428.545240                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79789.989312                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79789.989312                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82302.661389                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82302.661389                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79789.989312                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79531.516685                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79536.558923                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79789.989312                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79531.516685                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79536.558923                       # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          324                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         4939                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        25849                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.952515                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         19061751                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        19061751                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      1069336                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      1069336                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        17893                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        17893                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       255742                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       255742                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        17196                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        17196                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       748691                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       748691                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        17196                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1004433                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1021629                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        17196                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1004433                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1021629                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       100949                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       100949                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2805                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2805                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        40191                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        40191                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2805                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       141140                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        143945                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2805                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       141140                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       143945                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7917540500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7917540500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    223778500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    223778500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3305085000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3305085000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    223778500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11222625500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  11446404000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    223778500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11222625500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  11446404000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      1069336                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      1069336                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        17893                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        17893                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       356691                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       356691                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        20001                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        20001                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       788882                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       788882                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        20001                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1145573                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1165574                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        20001                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1145573                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1165574                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.283015                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.283015                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.140243                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.140243                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.050947                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.050947                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.140243                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.123205                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.123497                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.140243                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.123205                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.123497                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78431.093919                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79514.138444                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79519.288617                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -763,8 +802,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97166                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97166                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        97210                       # number of writebacks
+system.cpu.l2cache.writebacks::total            97210                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           14                       # number of ReadSharedReq MSHR hits
@@ -775,117 +814,117 @@ system.cpu.l2cache.demand_mshr_hits::total           15                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100917                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       100917                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2806                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2806                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        40153                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        40153                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2806                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       141070                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       143876                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2806                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       141070                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       143876                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6905603500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6905603500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       100949                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       100949                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2804                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2804                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        40177                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        40177                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2804                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       141126                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       143930                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2804                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       141126                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       143930                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6908050500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6908050500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    195670500                       # number of ReadCleanReq MSHR miss cycles
 system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    195670500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2903188500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2903188500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2902356000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2902356000                       # number of ReadSharedReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    195670500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9808792000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  10004462500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9810406500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  10006077000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    195670500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9808792000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  10004462500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.282954                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.282954                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.143463                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.143463                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050903                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050903                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.143463                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123154                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.123495                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.143463                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123154                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.123495                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68428.545240                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68428.545240                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69732.893799                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69732.893799                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.152940                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.152940                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69732.893799                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69531.381584                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69535.311657                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69732.893799                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69531.381584                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69535.311657                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9810406500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  10006077000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.283015                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.283015                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.140193                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.140193                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.050929                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.050929                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.140193                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.123192                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.123484                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.140193                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.123192                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.123484                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      2324094                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159133                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4986                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2609                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2606                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      2325181                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      1159677                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         4997                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2608                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2605                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        808376                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      1166449                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        17687                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        87231                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       356655                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       356655                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        19559                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       788817                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        56805                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3432320                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           3489125                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2383744                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141744320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          144128064                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      112304                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1277335                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.006003                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.077277                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        808883                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      1166546                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        18130                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        87307                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       356691                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       356691                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        20001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       788882                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        58132                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      3432623                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           3490755                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2440384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    141754176                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          144194560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      112376                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1277950                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.006008                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.077309                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1269670     99.40%     99.40% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               7662      0.60%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1270275     99.40%     99.40% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               7672      0.60%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  3      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1277335                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     2249017000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1277950                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     2250056500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      29357961                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      30027947                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1718215984                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1718367983                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              42959                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        97166                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            12529                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            100917                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           100917                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         42959                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397447                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 397447                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15426688                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15426688                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              42981                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        97210                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            12558                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            100949                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           100949                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         42981                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       397628                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 397628                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15432960                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                15432960                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            253571                       # Request fanout histogram
+system.membus.snoop_fanout::samples            253698                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  253571    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  253698    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              253571                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           685058500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              253698                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           685564500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          763682500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          763995250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index d56531c9c..1b2646d9c 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,121 +1,121 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.234067                       # Number of seconds simulated
-sim_ticks                                234067145000                       # Number of ticks simulated
-final_tick                               234067145000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.232865                       # Number of seconds simulated
+sim_ticks                                232864525000                       # Number of ticks simulated
+final_tick                               232864525000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  77703                       # Simulator instruction rate (inst/s)
-host_op_rate                                    84180                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               35998538                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 329176                       # Number of bytes of host memory used
-host_seconds                                  6502.13                       # Real time elapsed on the host
+host_inst_rate                                 164421                       # Simulator instruction rate (inst/s)
+host_op_rate                                   178126                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75782118                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 300244                       # Number of bytes of host memory used
+host_seconds                                  3072.82                       # Real time elapsed on the host
 sim_insts                                   505234934                       # Number of instructions simulated
 sim_ops                                     547348155                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            528384                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10113344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     16488320                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             27130048                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       528384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          528384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18753344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18753344                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               8256                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158021                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       257630                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                423907                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          293021                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               293021                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2257404                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             43207021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     70442693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               115907117                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2257404                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2257404                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          80119506                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               80119506                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          80119506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2257404                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            43207021                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     70442693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              196026623                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        423907                       # Number of read requests accepted
-system.physmem.writeReqs                       293021                       # Number of write requests accepted
-system.physmem.readBursts                      423907                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     293021                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 26979584                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    150464                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18751744                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  27130048                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18753344                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     2351                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                       6                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst            523840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10146304                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     16460800                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             27130944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       523840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          523840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18710656                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18710656                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               8185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158536                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       257200                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                423921                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          292354                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               292354                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2249548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             43571703                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     70688311                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               116509563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2249548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2249548                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          80349963                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               80349963                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          80349963                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2249548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            43571703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     70688311                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              196859526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        423921                       # Number of read requests accepted
+system.physmem.writeReqs                       292354                       # Number of write requests accepted
+system.physmem.readBursts                      423921                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     292354                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 26979136                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    151808                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18708352                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  27130944                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18710656                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     2372                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                       5                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               26590                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               25594                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               25276                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               32211                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               27176                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               28517                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               25342                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24044                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               25598                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               25550                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              25481                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              26074                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              27377                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              26182                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              25062                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              25482                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18771                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               18326                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               17966                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               17954                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18603                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18522                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               18156                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               17645                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18039                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17820                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18389                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              18735                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              18802                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              18436                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              18499                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              18333                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               26585                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               25966                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               25309                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               32108                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               27451                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               28247                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               25115                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24228                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               25496                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               25694                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              25307                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              26044                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              27396                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              26024                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              24983                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              25596                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18605                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               18353                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               18036                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               17927                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18566                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18339                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               17904                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               17705                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               17878                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17947                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18182                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              18731                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              18803                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              18363                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              18474                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              18505                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    234067092500                       # Total gap between requests
+system.physmem.totGap                    232864472500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  423907                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  423921                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 293021                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    324297                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     49438                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     12772                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      8887                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      7182                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      6051                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      5178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4282                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3308                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        79                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       41                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                       22                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                       12                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 292354                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    324214                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     49387                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     12801                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      8884                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      7277                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      6144                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      5194                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4262                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3284                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        56                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       20                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                       12                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        8                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
@@ -148,37 +148,37 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     7217                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     7709                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    12444                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    14936                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    16344                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    16981                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17377                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17664                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17969                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    18131                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    18327                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    18655                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    18757                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    18967                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    19091                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17673                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17198                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      142                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       36                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       12                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     7265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7749                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    12414                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    15014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    16308                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    16940                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    18097                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    18294                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    18577                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    18700                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    18855                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    19016                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17254                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17136                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      128                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       57                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       27                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       14                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
@@ -197,111 +197,115 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       323145                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      141.515567                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      99.534760                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     179.780407                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127         203801     63.07%     63.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        79524     24.61%     87.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        15124      4.68%     92.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7403      2.29%     94.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         4958      1.53%     96.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2458      0.76%     96.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1821      0.56%     97.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1542      0.48%     97.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6514      2.02%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         323145                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17117                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.623824                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      142.773249                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17115     99.99%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       322606                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      141.616907                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      99.575706                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     179.865264                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127         203481     63.07%     63.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        79249     24.57%     87.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        15283      4.74%     92.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7278      2.26%     94.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         4895      1.52%     96.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2519      0.78%     96.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1928      0.60%     97.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1485      0.46%     97.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6488      2.01%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         322606                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17068                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.693051                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      142.945620                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17066     99.99%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::18432-19455            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17117                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17117                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.117252                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.059352                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.476775                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               9319     54.44%     54.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                336      1.96%     56.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18               5339     31.19%     87.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               1368      7.99%     95.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                375      2.19%     97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                151      0.88%     98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 90      0.53%     99.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 54      0.32%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 43      0.25%     99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 14      0.08%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 11      0.06%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  3      0.02%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  5      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  2      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  1      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::35                  1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36                  1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::37                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::38                  2      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17117                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     8655442270                       # Total ticks spent queuing
-system.physmem.totMemAccLat               16559617270                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   2107780000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20532.13                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total           17068                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17068                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.126670                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.068877                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.479655                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               9203     53.92%     53.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                342      2.00%     55.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18               5412     31.71%     87.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               1340      7.85%     95.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                381      2.23%     97.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                185      1.08%     98.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 84      0.49%     99.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 48      0.28%     99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 28      0.16%     99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 13      0.08%     99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  9      0.05%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  6      0.04%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  6      0.04%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  3      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  3      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::33                  1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::34                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::35                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::51                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           17068                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     8669198966                       # Total ticks spent queuing
+system.physmem.totMemAccLat               16573242716                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   2107745000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20565.10                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39282.13                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         115.26                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          80.11                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      115.91                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       80.12                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39315.10                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         115.86                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          80.34                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      116.51                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       80.35                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           1.53                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.90                       # Data bus utilization in percentage for reads
+system.physmem.busUtilRead                       0.91                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.63                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.12                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.74                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     306165                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     85234                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   72.63                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  29.09                       # Row buffer hit rate for writes
-system.physmem.avgGap                       326486.19                       # Average gap between requests
-system.physmem.pageHitRate                      54.77                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1230881400                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  671611875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1674738000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                945710640                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            15287822160                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            82093251645                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            68426008500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             170330024220                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              727.711031                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   113299566780                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7815860000                       # Time in different power states
+system.physmem.avgWrQLen                        21.66                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     306141                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     85116                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   72.62                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  29.11                       # Row buffer hit rate for writes
+system.physmem.avgGap                       325104.84                       # Average gap between requests
+system.physmem.pageHitRate                      54.81                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 1231478640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  671937750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1677023400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                942418800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            15209503920                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            82038252060                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            67754804250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             169525418820                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              728.002962                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   112181922825                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7775820000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    112947723720                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    112906030175                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 1211996520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  661307625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1612860600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                952903440                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            15287822160                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            79567358490                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            70641696000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             169935944835                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              726.027425                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   117000888833                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7815860000                       # Time in different power states
+system.physmem_1.actEnergy                 1207422720                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  658812000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1610934000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                951801840                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            15209503920                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            78953270130                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            70460943000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             169052687610                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              725.972811                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   116702858630                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7775820000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    109246895167                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    108384997620                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               175180766                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         131398582                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           7457767                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90448674                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83962981                       # Number of BTB hits
+system.cpu.branchPred.lookups               174583649                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         131051926                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           7234327                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             90400017                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                79003628                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.829422                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                12120591                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             103810                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             87.393377                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                12104831                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104507                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         4687804                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            4673781                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            14023                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        53864                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -420,232 +424,232 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  548                       # Number of system calls
-system.cpu.numCycles                        468134291                       # number of cpu cycles simulated
+system.cpu.numCycles                        465729051                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            7820267                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      732116673                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   175180766                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           96083572                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     452171073                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                14968467                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 4602                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            73                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        11985                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 236801931                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 34000                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          467492233                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.696108                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.181518                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            7627967                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      727492581                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   174583649                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           95782240                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     450186491                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14522705                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 4278                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           141                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        13015                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 235271545                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 36405                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          465093244                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.693494                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.182412                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 95390302     20.40%     20.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                132755119     28.40%     48.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 57878050     12.38%     61.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                181468762     38.82%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 95400849     20.51%     20.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                132044062     28.39%     48.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 57356261     12.33%     61.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                180292072     38.76%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            467492233                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.374210                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.563903                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32386715                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             118994468                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 287021244                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              22094342                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                6995464                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             24069927                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                496423                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              716090334                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              30070891                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                6995464                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 63523233                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                55798726                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       40379426                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 276600311                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              24195073                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              686795271                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13387267                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               9456751                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2380300                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1659301                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1902126                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           831315383                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            3020004146                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        724106734                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               424                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            465093244                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.374861                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.562051                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32522816                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             120066297                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 282921194                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              22809829                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                6773108                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             23856996                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                495879                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              710982293                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              29095211                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                6773108                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 63338503                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                55962062                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       40377047                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 273519607                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              25122917                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              682713266                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              12851705                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               9930975                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2510705                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1794472                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                1920747                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           827509638                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            3000483863                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        718633951                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups                88                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             654095674                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                177219709                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1544715                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        1534907                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  42449008                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            143548530                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            67987102                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12901487                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11312004                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  668319179                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2978345                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 610345579                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5883396                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       123949369                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    319552681                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            713                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     467492233                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.305574                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.102144                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                173413964                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1545834                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        1536299                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  43818789                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            142365669                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            67523427                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          12892964                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         11349045                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  664768510                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2979350                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 608926727                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5749477                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       120399705                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    306541360                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1718                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     465093244                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.309257                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.101839                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           150289114     32.15%     32.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           101200175     21.65%     53.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           145769872     31.18%     84.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            63327215     13.55%     98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             6905270      1.48%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 587      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           148683316     31.97%     31.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           100887288     21.69%     53.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           145497620     31.28%     84.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            63056493     13.56%     98.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             6967915      1.50%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 612      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       467492233                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       465093244                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                71934630     52.97%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     30      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     52.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               44579938     32.83%     85.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              19275701     14.20%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                71909518     53.13%     53.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     30      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     53.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               44304480     32.74%     85.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              19119642     14.13%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             413246027     67.71%     67.71% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               352054      0.06%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            134225887     21.99%     89.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            62521608     10.24%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             412592470     67.76%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               352106      0.06%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              3      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            133579374     21.94%     89.75% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            62402774     10.25%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              610345579                       # Type of FU issued
-system.cpu.iq.rate                           1.303783                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   135790299                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.222481                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         1829856789                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         795275233                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    595043365                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 297                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                322                       # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total              608926727                       # Type of FU issued
+system.cpu.iq.rate                           1.307470                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   135333670                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.222250                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1824029756                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         788176792                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    594203276                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                  89                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                 70                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           16                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              746135699                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     179                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          7278929                       # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses              744260342                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      55                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          7285470                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     27665247                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        25667                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        29087                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     11126882                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     26482386                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        24610                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        29757                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     10663207                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       224857                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         22662                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       225824                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         22615                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                6995464                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                22964751                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                919913                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           672785382                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                6773108                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                22711376                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                916891                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           669240779                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             143548530                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             67987102                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1489803                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 257985                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                525401                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          29087                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3817186                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3742282                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              7559468                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             599464871                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             129581939                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          10880708                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             142365669                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             67523427                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1490808                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 256518                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                523375                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          29757                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3591194                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3743418                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              7334612                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             598426944                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             129087025                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          10499783                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       1487858                       # number of nop insts executed
-system.cpu.iew.exec_refs                    190527023                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                131393815                       # Number of branches executed
-system.cpu.iew.exec_stores                   60945084                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.280540                       # Inst execution rate
-system.cpu.iew.wb_sent                      596341042                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     595043381                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 349946127                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 570674546                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.271095                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.613215                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       110160125                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                       1492919                       # number of nop insts executed
+system.cpu.iew.exec_refs                    190006687                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                131263664                       # Number of branches executed
+system.cpu.iew.exec_stores                   60919662                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.284925                       # Inst execution rate
+system.cpu.iew.wb_sent                      595449226                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     594203292                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 349565798                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 571378084                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.275856                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.611794                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       107129246                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2977632                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           6968998                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    450355888                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.218352                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.886219                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6746083                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    448430808                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.223582                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.891618                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    221337598     49.15%     49.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    116324478     25.83%     74.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     43749692      9.71%     84.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     23265748      5.17%     89.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     11567595      2.57%     92.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      7783316      1.73%     94.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      8242109      1.83%     95.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      4251497      0.94%     96.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     13833855      3.07%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    219662042     48.98%     48.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    116371870     25.95%     74.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43476650      9.70%     84.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     23164070      5.17%     89.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     11528126      2.57%     92.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7755918      1.73%     94.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      8275201      1.85%     95.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      4244089      0.95%     96.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     13952842      3.11%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    450355888                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    448430808                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            506578818                       # Number of instructions committed
 system.cpu.commit.committedOps              548692039                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -691,389 +695,392 @@ system.cpu.commit.op_class_0::MemWrite       56860220     10.36%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         548692039                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              13833855                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1095367059                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1334871218                       # The number of ROB writes
-system.cpu.timesIdled                           12751                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          642058                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              13952842                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1090292113                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1328334369                       # The number of ROB writes
+system.cpu.timesIdled                           12786                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          635807                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   505234934                       # Number of Instructions Simulated
 system.cpu.committedOps                     547348155                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.926568                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.926568                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.079252                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.079252                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                611137722                       # number of integer regfile reads
-system.cpu.int_regfile_writes               328167949                       # number of integer regfile writes
+system.cpu.cpi                               0.921807                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.921807                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.084826                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.084826                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                610135542                       # number of integer regfile reads
+system.cpu.int_regfile_writes               327337405                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
-system.cpu.cc_regfile_reads                2170388141                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                376631000                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               217967292                       # number of misc regfile reads
+system.cpu.cc_regfile_reads                2166261838                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                376539611                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               217603213                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2977084                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2817526                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.629948                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           169361200                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2818038                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             60.098977                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           2817145                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.627957                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168870791                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2817657                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             59.933055                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         500883000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.629948                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999277                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999277                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.627957                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999273                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999273                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          174                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          276                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           67                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         356245262                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        356245262                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    114657971                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       114657971                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     51723280                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       51723280                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         2781                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          2781                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488558                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total      1488558                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         355267161                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        355267161                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    114168570                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114168570                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     51722271                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       51722271                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         2788                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          2788                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488560                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488560                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     166381251                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        166381251                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    166384032                       # number of overall hits
-system.cpu.dcache.overall_hits::total       166384032                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      4836633                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       4836633                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2515769                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2515769                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     165890841                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        165890841                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    165893629                       # number of overall hits
+system.cpu.dcache.overall_hits::total       165893629                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      4837166                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       4837166                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2516778                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2516778                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           12                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           12                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data           67                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total           67                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      7352402                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        7352402                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      7352414                       # number of overall misses
-system.cpu.dcache.overall_misses::total       7352414                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  57448748500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  57448748500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18924298425                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18924298425                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       887000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       887000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  76373046925                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  76373046925                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  76373046925                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  76373046925                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    119494604                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    119494604                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           66                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           66                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      7353944                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        7353944                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      7353956                       # number of overall misses
+system.cpu.dcache.overall_misses::total       7353956                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57478265500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  57478265500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18947607428                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18947607428                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1052500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      1052500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  76425872928                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  76425872928                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  76425872928                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  76425872928                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    119005736                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    119005736                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     54239049                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     54239049                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         2793                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         2793                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488625                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total      1488625                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         2800                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         2800                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488626                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488626                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    173733653                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    173733653                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    173736446                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    173736446                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040476                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.040476                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046383                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.046383                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004296                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.004296                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000045                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.042320                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.042320                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.042319                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.042319                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11877.839088                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11877.839088                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7522.271888                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  7522.271888                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13238.805970                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13238.805970                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10387.496076                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10387.496076                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10387.479123                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10387.479123                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           15                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       910856                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          221280                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs           15                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     4.116305                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    173244785                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    173244785                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    173247585                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    173247585                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040646                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.040646                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.046402                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.046402                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.004286                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.004286                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000044                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000044                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.042448                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.042448                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.042448                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.042448                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11882.632413                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11882.632413                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  7528.517584                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  7528.517584                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15946.969697                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15946.969697                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10392.501347                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10392.501347                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10392.484389                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10392.484389                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           36                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       916660                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          221191                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     7.200000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     4.144201                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2817526                       # number of writebacks
-system.cpu.dcache.writebacks::total           2817526                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2538406                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      2538406                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1995936                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1995936                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           67                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total           67                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4534342                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4534342                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4534342                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4534342                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2298227                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2298227                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519833                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       519833                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      2817145                       # number of writebacks
+system.cpu.dcache.writebacks::total           2817145                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2539309                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      2539309                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1996958                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1996958                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           66                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           66                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      4536267                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4536267                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4536267                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4536267                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2297857                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2297857                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       519820                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       519820                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           10                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           10                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2818060                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2818060                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2818070                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2818070                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29530364500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  29530364500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4603208492                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4603208492                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       671000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       671000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  34133572992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  34133572992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  34134243992                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  34134243992                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019233                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019233                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2817677                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2817677                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2817687                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2817687                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  29541351500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  29541351500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4603156994                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4603156994                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       669500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       669500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  34144508494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  34144508494                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  34145177994                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  34145177994                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019309                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019309                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009584                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009584                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003580                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003580                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016221                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.016221                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016220                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.016220                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12849.193966                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12849.193966                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8855.167894                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8855.167894                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        67100                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        67100                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.436567                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.436567                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.631692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.631692                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.003571                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.003571                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016264                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.016264                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016264                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.016264                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12856.044349                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12856.044349                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8855.290281                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8855.290281                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        66950                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        66950                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12117.964016                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12117.964016                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12118.158615                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12118.158615                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             73421                       # number of replacements
-system.cpu.icache.tags.tagsinuse           466.150305                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           236720018                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             73932                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3201.861413                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      115595672500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   466.150305                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.910450                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.910450                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           99                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          258                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          120                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           17                       # Occupied blocks per task id
+system.cpu.icache.tags.replacements             76528                       # number of replacements
+system.cpu.icache.tags.tagsinuse           466.435319                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           235186472                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             77040                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           3052.783904                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle      115558244500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   466.435319                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.911006                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.911006                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           98                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          262                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          119                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           16                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           17                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         473677631                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        473677631                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    236720018                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       236720018                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     236720018                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        236720018                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    236720018                       # number of overall hits
-system.cpu.icache.overall_hits::total       236720018                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        81816                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         81816                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        81816                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          81816                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        81816                       # number of overall misses
-system.cpu.icache.overall_misses::total         81816                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1337252702                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1337252702                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1337252702                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1337252702                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1337252702                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1337252702                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    236801834                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    236801834                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    236801834                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    236801834                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    236801834                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    236801834                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000346                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000346                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000346                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000346                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000346                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000346                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16344.635548                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16344.635548                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16344.635548                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16344.635548                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16344.635548                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16344.635548                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       158150                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          252                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              6634                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    23.839313                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    50.400000                       # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         470619957                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        470619957                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    235186472                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       235186472                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     235186472                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        235186472                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    235186472                       # number of overall hits
+system.cpu.icache.overall_hits::total       235186472                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        84972                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         84972                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        84972                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          84972                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        84972                       # number of overall misses
+system.cpu.icache.overall_misses::total         84972                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1359599197                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1359599197                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1359599197                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1359599197                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1359599197                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1359599197                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    235271444                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    235271444                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    235271444                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    235271444                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    235271444                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    235271444                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000361                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000361                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000361                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000361                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000361                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000361                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16000.555442                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16000.555442                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16000.555442                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16000.555442                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16000.555442                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16000.555442                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       161540                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          362                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              6762                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               6                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    23.889382                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    60.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        73421                       # number of writebacks
-system.cpu.icache.writebacks::total             73421                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7851                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         7851                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         7851                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         7851                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         7851                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         7851                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        73965                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        73965                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        73965                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        73965                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        73965                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        73965                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1106045298                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1106045298                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1106045298                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1106045298                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1106045298                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1106045298                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000312                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000312                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000312                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000312                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000312                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000312                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14953.630744                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14953.630744                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14953.630744                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14953.630744                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14953.630744                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14953.630744                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        76528                       # number of writebacks
+system.cpu.icache.writebacks::total             76528                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         7901                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         7901                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         7901                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         7901                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         7901                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         7901                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        77071                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        77071                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        77071                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        77071                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        77071                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        77071                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1127867788                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1127867788                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1127867788                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1127867788                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1127867788                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1127867788                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000328                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000328                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000328                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000328                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14634.139793                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14634.139793                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14634.139793                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14634.139793                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14634.139793                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14634.139793                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      8512826                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      8514409                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit          561                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      8513492                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      8514887                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          402                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage       743711                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           395988                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15132.629454                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3179530                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           411918                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.718842                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     170668253000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 13783.431676                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1349.197778                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.841274                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.082348                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.923622                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022         1007                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        14923                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           36                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          235                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          736                       # Occupied blocks per task id
+system.cpu.l2cache.prefetcher.pfSpanPage       743841                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           395630                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15127.357564                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3184940                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           411561                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.738683                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     169696310500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 13778.300526                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data     0.000101                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  1349.056936                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.840961                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000000                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.082340                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.923301                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022         1053                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        14878                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           34                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3          239                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          778                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          154                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          207                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4874                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6268                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3420                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.061462                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.910828                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         94799517                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        94799517                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2352015                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2352015                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       515062                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       515062                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       517153                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       517153                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        65667                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        65667                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2137304                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      2137304                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        65667                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2654457                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2720124                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        65667                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2654457                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2720124                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           32                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           32                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         5060                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         5060                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         8262                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         8262                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       158521                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       158521                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         8262                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       163581                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        171843                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         8262                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       163581                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       171843                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       104000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       104000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    481607500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    481607500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    598906500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    598906500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  12080001500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  12080001500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    598906500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  12561609000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13160515500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    598906500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  12561609000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13160515500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2352015                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2352015                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       515062                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       515062                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           32                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           32                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       522213                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       522213                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        73929                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        73929                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2295825                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      2295825                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        73929                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2818038                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2891967                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        73929                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2818038                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2891967                       # number of overall (read+write) accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4895                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6342                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         3283                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.064270                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908081                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         94885258                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        94885258                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2350571                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2350571                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       519224                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       519224                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       516915                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       516915                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        68843                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        68843                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      2136682                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      2136682                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        68843                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2653597                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2722440                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        68843                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2653597                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2722440                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           30                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           30                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         5096                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         5096                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         8194                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         8194                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       158964                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       158964                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         8194                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       164060                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        172254                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         8194                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       164060                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       172254                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        40500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total        40500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    484398500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    484398500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    596844000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    596844000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  12095410500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  12095410500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    596844000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  12579809000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  13176653000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    596844000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  12579809000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  13176653000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2350571                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2350571                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       519224                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       519224                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           30                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           30                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       522011                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       522011                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        77037                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        77037                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2295646                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      2295646                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        77037                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2817657                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2894694                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        77037                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2817657                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2894694                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009690                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.009690                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.111756                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.111756                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.069048                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.069048                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111756                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.058048                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.059421                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111756                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.058048                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.059421                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         3250                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total         3250                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95179.347826                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95179.347826                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72489.288308                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72489.288308                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76204.424020                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76204.424020                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72489.288308                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76791.369413                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76584.530647                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72489.288308                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76791.369413                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76584.530647                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.009762                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.009762                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.106364                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.106364                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.069246                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.069246                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.106364                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.058226                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.059507                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.106364                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.058226                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.059507                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         1350                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total         1350                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95054.650706                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95054.650706                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72839.150598                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72839.150598                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76088.991847                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76088.991847                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72839.150598                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76678.099476                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76495.483414                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72839.150598                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76678.099476                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76495.483414                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1082,158 +1089,159 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       293021                       # number of writebacks
-system.cpu.l2cache.writebacks::total           293021                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1390                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1390                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4166                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4166                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         5556                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         5561                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         5556                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         5561                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       350786                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       350786                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           32                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           32                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3670                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3670                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         8257                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         8257                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       154355                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       154355                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         8257                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158025                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       166282                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         8257                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158025                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       350786                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       517068                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18631455358                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18631455358                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       467000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       467000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    333539000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    333539000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    549061000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    549061000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  10851655500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  10851655500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    549061000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11185194500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11734255500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    549061000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11185194500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18631455358                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  30365710858                       # number of overall MSHR miss cycles
+system.cpu.l2cache.unused_prefetches             1977                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks       292354                       # number of writebacks
+system.cpu.l2cache.writebacks::total           292354                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1396                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         1396                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            9                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total            9                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data         4126                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total         4126                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         5522                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         5531                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            9                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         5522                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         5531                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       350840                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       350840                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           30                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           30                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3700                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3700                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         8185                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         8185                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       154838                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       154838                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         8185                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158538                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       166723                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         8185                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158538                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       350840                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       517563                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  18642506693                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  18642506693                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       439500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       439500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    332568000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    332568000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    547176500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    547176500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  10861820000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  10861820000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    547176500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11194388000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11741564500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    547176500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11194388000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  18642506693                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  30384071193                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007028                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007028                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.111688                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.111688                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.067233                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.067233                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.111688                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056076                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.057498                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.111688                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056076                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.007088                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.007088                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.106248                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.106248                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.067449                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.067449                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.106248                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056266                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.057596                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.106248                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056266                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.178795                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53113.451956                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14593.750000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14593.750000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90882.561308                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90882.561308                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66496.427274                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66496.427274                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70303.232807                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70303.232807                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66496.427274                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70781.170701                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70568.404878                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66496.427274                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70781.170701                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58726.726191                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.178797                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53136.776573                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14650                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14650                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89883.243243                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89883.243243                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66851.130116                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66851.130116                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70149.575686                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70149.575686                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66851.130116                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70610.125017                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70425.583153                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66851.130116                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70610.125017                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53136.776573                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58706.034228                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5782982                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2890992                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23909                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       260193                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       244256                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        15937                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       2369788                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2645036                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       538932                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       265577                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       391986                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests      5788431                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2893715                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        23913                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       261080                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       244791                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        16289                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       2372715                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2642925                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       543102                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       266298                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       392168                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           32                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           32                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       522213                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       522213                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        73965                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2295825                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       221313                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8453667                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8674980                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9430272                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    360676160                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          370106432                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      950621                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3842619                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.078093                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.283354                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq           30                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           30                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       522011                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       522011                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        77071                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2295646                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       230634                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8452520                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           8683154                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      9828032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    360627392                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          370455424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      950855                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      3845578                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.078356                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.284056                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            3558474     92.61%     92.61% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             268208      6.98%     99.59% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              15937      0.41%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            3560544     92.59%     92.59% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             268745      6.99%     99.58% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              16289      0.42%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3842619                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5782438005                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        3845578                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     5787888505                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
 system.cpu.toL2Bus.snoopLayer0.occupancy         1506                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     111022344                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     115689827                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4227098948                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    4226522955                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.8                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             420240                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       293021                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            98541                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               36                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3666                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3666                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        420241                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1239411                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1239411                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45883328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                45883328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             420223                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       292354                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            98859                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               33                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3697                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3697                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        420224                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1239087                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1239087                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     45841536                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                45841536                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            815505                       # Request fanout histogram
+system.membus.snoop_fanout::samples            815167                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  815505    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  815167    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              815505                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2215026289                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              815167                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          2211611288                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.9                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2242814920                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         2242842427                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 080fc4b8f..139608a38 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,108 +1,108 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.404912                       # Number of seconds simulated
-sim_ticks                                404911731500                       # Number of ticks simulated
-final_tick                               404911731500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.481958                       # Number of seconds simulated
+sim_ticks                                481957625500                       # Number of ticks simulated
+final_tick                               481957625500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59948                       # Simulator instruction rate (inst/s)
-host_op_rate                                   110933                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               29356650                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 419644                       # Number of bytes of host memory used
-host_seconds                                 13792.85                       # Real time elapsed on the host
+host_inst_rate                                 104668                       # Simulator instruction rate (inst/s)
+host_op_rate                                   193689                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               61009723                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 318640                       # Number of bytes of host memory used
+host_seconds                                  7899.69                       # Real time elapsed on the host
 sim_insts                                   826847303                       # Number of instructions simulated
 sim_ops                                    1530082520                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            162176                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24538048                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             24700224                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       162176                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          162176                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     18887104                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          18887104                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2534                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             383407                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                385941                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          295111                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               295111                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               400522                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             60600981                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                61001502                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          400522                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             400522                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          46644991                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               46644991                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          46644991                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              400522                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            60600981                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              107646493                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        385941                       # Number of read requests accepted
-system.physmem.writeReqs                       295111                       # Number of write requests accepted
-system.physmem.readBursts                      385941                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     295111                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 24680320                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     19904                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  18885056                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  24700224                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               18887104                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      311                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            154624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24604096                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             24758720                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       154624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          154624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     18874880                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          18874880                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2416                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             384439                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                386855                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          294920                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               294920                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               320825                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             51050330                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51371155                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          320825                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             320825                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          39162945                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               39162945                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          39162945                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              320825                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            51050330                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               90534100                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        386855                       # Number of read requests accepted
+system.physmem.writeReqs                       294920                       # Number of write requests accepted
+system.physmem.readBursts                      386855                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     294920                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 24737792                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20928                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  18873280                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  24758720                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               18874880                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      327                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               24031                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               26423                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               24936                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               24514                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               23470                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               23659                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               24566                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               24334                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               23673                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               23472                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              24737                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              23939                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              23178                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              22917                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              23861                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              23920                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               18617                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               19947                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               19213                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               19024                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               18187                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               18473                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               19133                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               19079                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               18679                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               17947                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              18901                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              17752                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              17391                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              17019                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              17841                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              17876                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               24516                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               26460                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               24685                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               24442                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               23203                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               23588                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               24636                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               24397                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               23786                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               23509                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              24817                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              23975                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              23290                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              22963                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              23965                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              24296                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               18881                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               19925                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               19022                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               18969                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               18086                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               18421                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               19142                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               19085                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               18675                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               17903                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              18899                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              17761                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              17398                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              16983                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              17797                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              17948                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    404911622500                       # Total gap between requests
+system.physmem.totGap                    481957508500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  385941                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  386855                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 295111                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    380814                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      4468                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       307                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         9                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 294920                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    381052                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      5169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       278                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,44 +144,44 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     6167                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     6528                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    16966                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    17552                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    17613                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    17658                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    17689                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    17680                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    17711                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    17661                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    17715                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    17693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    17766                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    17756                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    17771                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    17868                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    17615                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    17553                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     6623                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     7003                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    16980                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    17478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    17588                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    17593                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    17583                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    17584                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    17617                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    17604                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    17655                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    17615                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    17685                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    17703                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    17675                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    17789                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    17559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    17489                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                       33                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       20                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                        5                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       16                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
@@ -193,344 +193,343 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       147028                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      296.294039                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     174.908610                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     323.351914                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          54375     36.98%     36.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        40100     27.27%     64.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        13677      9.30%     73.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         7439      5.06%     78.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         5510      3.75%     82.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         3768      2.56%     84.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         3010      2.05%     86.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         2924      1.99%     88.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16225     11.04%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         147028                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         17521                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        22.008789                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      217.166856                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          17511     99.94%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071            1      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       150272                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      290.205707                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     171.657717                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     319.431199                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          56562     37.64%     37.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        41303     27.49%     65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        13716      9.13%     74.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         7600      5.06%     79.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         5568      3.71%     83.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         3790      2.52%     85.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2987      1.99%     87.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         2640      1.76%     89.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16106     10.72%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         150272                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         17470                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        22.124900                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      243.906372                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          17461     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            5      0.03%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            2      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::7168-8191            1      0.01%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::26624-27647            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           17521                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         17521                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.841447                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.770042                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        2.569197                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19           17331     98.92%     98.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23             134      0.76%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27              31      0.18%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31               4      0.02%     99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35               3      0.02%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39               3      0.02%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43               1      0.01%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47               1      0.01%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51               4      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55               2      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91               1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111             1      0.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119             1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127             1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::8192-9215            1      0.01%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::29696-30719            1      0.01%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           17470                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         17470                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.880080                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.823698                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        2.084974                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19           17271     98.86%     98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23             152      0.87%     99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27              24      0.14%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31               6      0.03%     99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35               3      0.02%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39               4      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43               4      0.02%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47               1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59               1      0.01%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63               1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91               1      0.01%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::208-211             1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           17521                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     4288044250                       # Total ticks spent queuing
-system.physmem.totMemAccLat               11518606750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1928150000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11119.58                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           17470                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     4249579000                       # Total ticks spent queuing
+system.physmem.totMemAccLat               11496979000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1932640000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       10994.23                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  29869.58                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          60.95                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          46.64                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       61.00                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       46.64                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  29744.23                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          51.33                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          39.16                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       51.37                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       39.16                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.84                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.48                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.36                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.71                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.40                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.31                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        21.53                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     317942                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    215725                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.45                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.10                       # Row buffer hit rate for writes
-system.physmem.avgGap                       594538.48                       # Average gap between requests
-system.physmem.pageHitRate                      78.40                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  570719520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  311404500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1528168200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                982685520                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            26446645680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            62100381375                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           188471152500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             280411157295                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.529485                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   312985847250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     13520780000                       # Time in different power states
+system.physmem.avgWrQLen                        20.94                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     315674                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    215465                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   81.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                       706915.78                       # Average gap between requests
+system.physmem.pageHitRate                      77.94                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  581999040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  317559000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1528152600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                981784800                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            31478846880                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            70268579415                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           227533024500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             332689946235                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              690.294629                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   377929772750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     16093480000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     78402005250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     87930818250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  540562680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  294949875                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1479324600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                929082960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            26446645680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            59763827970                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           190520760750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             279975154515                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              691.452692                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   316410940750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     13520780000                       # Time in different power states
+system.physmem_1.actEnergy                  553777560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  302160375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1486375800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                928823760                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            31478846880                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            68021430795                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           229504207500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             332275622670                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              689.434954                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   381228600750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     16093480000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     74976935500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     84631916750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               219859048                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         219859048                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           8758546                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            124148256                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               121897688                       # Number of BTB hits
+system.cpu.branchPred.lookups               297786504                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         297786504                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          23596621                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            229702188                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.187193                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                27156156                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1403906                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                40293529                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            4405587                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups       229702188                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits          119907455                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses        109794733                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted     11576014                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        809823464                       # number of cpu cycles simulated
+system.cpu.numCycles                        963915252                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          176591288                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1214997993                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   219859048                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          149053844                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     622702021                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                18219345                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        230                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                91157                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        715943                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       449274                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           28                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 171574494                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               2309765                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          809659613                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.796039                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.371227                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          229572933                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1587362959                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   297786504                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          160200984                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     709710694                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                48100941                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                       1387                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                31814                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        398605                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles         6640                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles           18                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 216353847                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               6306355                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       6                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          963772561                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.083618                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.495232                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                417404830     51.55%     51.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 32671589      4.04%     55.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 32039233      3.96%     59.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 32726753      4.04%     63.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 26705475      3.30%     66.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 26911183      3.32%     70.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 35262840      4.36%     74.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 31547344      3.90%     78.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                174390366     21.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                472321182     49.01%     49.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 36440853      3.78%     52.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 36199829      3.76%     56.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 33073350      3.43%     59.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 28557183      2.96%     62.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 29987754      3.11%     66.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 40189317      4.17%     70.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 37482048      3.89%     74.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                249521045     25.89%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            809659613                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.271490                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.500325                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                121391489                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             370091708                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 226645475                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              82421269                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                9109672                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2145160206                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                9109672                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                153539670                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               151301355                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          41989                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 272974154                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             222692773                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2099917751                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                135565                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              138360760                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               24932221                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               49265464                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2208208417                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5316744595                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       3383996279                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             60226                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            963772561                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.308934                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.646787                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                165558629                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             380809572                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 312283336                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              81070554                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               24050470                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2743818074                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               24050470                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                201592178                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               193949048                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          12373                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 351358358                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             192810134                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2626442761                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                758361                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              120779385                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               21914925                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               41340162                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2707324732                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            6591643908                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4206582921                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           2532048                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1616961572                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                591246845                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               3675                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           3497                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 423124310                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            508481889                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           201115971                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         229749012                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         68249944                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2031398692                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               54143                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1792547451                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            420919                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       501370315                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    849083500                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          53591                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     809659613                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.213952                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.069729                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps               1090363160                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                921                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            827                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 369363812                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            608309859                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           244105032                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         253215291                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         76456984                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2419527437                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded              123521                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1999245990                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           3630215                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       889568438                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1509945066                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         122969                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     963772561                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.074396                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.106547                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           239429764     29.57%     29.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           124356019     15.36%     44.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           119082530     14.71%     59.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           108043901     13.34%     72.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            89929088     11.11%     84.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            60282735      7.45%     91.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            42261465      5.22%     96.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            18997036      2.35%     99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             7277075      0.90%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           335335755     34.79%     34.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           135420425     14.05%     48.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           129949182     13.48%     62.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           118520110     12.30%     74.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            97996233     10.17%     84.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            67311922      6.98%     91.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            45709014      4.74%     96.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            22671115      2.35%     98.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            10858805      1.13%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       809659613                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       963772561                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                11520020     42.79%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     42.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               12317290     45.76%     88.55% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3082634     11.45%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                11256438     43.50%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     43.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11830784     45.72%     89.22% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               2789302     10.78%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2934339      0.16%      0.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1185141409     66.11%     66.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               369471      0.02%     66.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               4797462      0.27%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 190      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                  20      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 21      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                 479      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            428879813     23.93%     90.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           170424247      9.51%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2910372      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1333563815     66.70%     66.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               358658      0.02%     66.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               4798558      0.24%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  10      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            471264290     23.57%     90.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186350287      9.32%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1792547451                       # Type of FU issued
-system.cpu.iq.rate                           2.213504                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    26919944                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.015018                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4422066274                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2533070112                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1765468749                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               29104                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              69216                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses         5504                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1816520301                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12755                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        185916260                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1999245990                       # Type of FU issued
+system.cpu.iq.rate                           2.074089                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    25876524                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.012943                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4990508159                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        3305732748                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1923901013                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1263121                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            4059650                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       238029                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2021668252                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  543890                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        179792885                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    124400743                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       210576                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       369684                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     51957776                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    224226629                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       339387                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       641597                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     94946837                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        22915                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1100                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        32049                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           734                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                9109672                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                98354510                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               6118608                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2031452835                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            404669                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             508484056                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            201115971                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              41229                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                1818362                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               3401419                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         369684                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        4846207                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      4373880                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              9220087                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1773318465                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             423351838                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          19228986                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               24050470                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               144665099                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               6487735                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2419650958                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1303031                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             608309942                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            244105032                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              42573                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                1493780                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               4140484                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         641597                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        8724662                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     20631512                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             29356174                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1945805936                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             456837338                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          53440054                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    590572450                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                169222012                       # Number of branches executed
-system.cpu.iew.exec_stores                  167220612                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.189759                       # Inst execution rate
-system.cpu.iew.wb_sent                     1769957940                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1765474253                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1342270213                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2056372436                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.180073                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.652737                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       501430525                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                    635668777                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                185171662                       # Number of branches executed
+system.cpu.iew.exec_stores                  178831439                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.018648                       # Inst execution rate
+system.cpu.iew.wb_sent                     1934669445                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1924139042                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1457092334                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2203939353                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.996170                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.661131                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       889643735                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             552                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           8839580                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    741419902                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.063719                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.574359                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          23627115                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    831081217                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.841075                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.465971                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    276552385     37.30%     37.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    172772725     23.30%     60.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     55960386      7.55%     68.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     86390933     11.65%     79.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     25906280      3.49%     83.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     26508569      3.58%     86.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      9812132      1.32%     88.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8956469      1.21%     89.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     78560023     10.60%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    351390819     42.28%     42.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    184611364     22.21%     64.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     57978208      6.98%     71.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     87188862     10.49%     81.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     30418140      3.66%     85.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     26591078      3.20%     88.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     10434720      1.26%     90.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      9032324      1.09%     91.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     73435702      8.84%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    741419902                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    831081217                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            826847303                       # Number of instructions committed
 system.cpu.commit.committedOps             1530082520                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -576,350 +575,350 @@ system.cpu.commit.op_class_0::MemWrite      149158195      9.75%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1530082520                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              78560023                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   2694372924                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4131439321                       # The number of ROB writes
-system.cpu.timesIdled                            2207                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          163851                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              73435702                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3177371770                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4973814894                       # The number of ROB writes
+system.cpu.timesIdled                            2014                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          142691                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   826847303                       # Number of Instructions Simulated
 system.cpu.committedOps                    1530082520                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.979411                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.979411                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.021022                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.021022                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2730823256                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1440512155                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      5926                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      463                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 599968810                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                405913106                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               971975039                       # number of misc regfile reads
+system.cpu.cpi                               1.165772                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.165772                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.857801                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.857801                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2928585667                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1576867903                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    239177                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        8                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 617820038                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                419954937                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1064369445                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2532888                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.837732                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           382237058                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2536984                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            150.665932                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle        1673396500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.837732                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998007                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998007                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2545945                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4088.303608                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           421067815                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2550041                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.121978                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle        1812560500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4088.303608                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998121                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998121                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           24                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          870                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         3173                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           20                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          634                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         3418                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         773578930                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        773578930                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    233596304                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       233596304                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148199808                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148199808                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     381796112                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        381796112                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    381796112                       # number of overall hits
-system.cpu.dcache.overall_hits::total       381796112                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2766458                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2766458                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       958403                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       958403                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3724861                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3724861                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3724861                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3724861                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  58572979000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  58572979000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  29883028996                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  29883028996                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  88456007996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  88456007996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  88456007996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  88456007996                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    236362762                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    236362762                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         851394195                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        851394195                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    272697526                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       272697526                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148366944                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148366944                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     421064470                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        421064470                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    421064470                       # number of overall hits
+system.cpu.dcache.overall_hits::total       421064470                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2566340                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2566340                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       791267                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       791267                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3357607                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3357607                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3357607                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3357607                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  57037182000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  57037182000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  24501570500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  24501570500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  81538752500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  81538752500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  81538752500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  81538752500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    275263866                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    275263866                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149158211                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149158211                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    385520973                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    385520973                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    385520973                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    385520973                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.011704                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.011704                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006425                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006425                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009662                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009662                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009662                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009662                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21172.553135                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21172.553135                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31180.024474                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31180.024474                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23747.465475                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23747.465475                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23747.465475                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23747.465475                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs         9959                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets            9                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              1047                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.511939                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets            9                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data    424422077                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    424422077                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    424422077                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    424422077                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009323                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.009323                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005305                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.005305                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.007911                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.007911                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007911                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007911                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.107351                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.107351                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30964.984639                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30964.984639                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24284.781542                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24284.781542                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24284.781542                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24284.781542                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs         8528                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets         1295                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               875                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets              14                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs     9.746286                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    92.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2332013                       # number of writebacks
-system.cpu.dcache.writebacks::total           2332013                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       999668                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       999668                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        19404                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        19404                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1019072                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1019072                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1019072                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1019072                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1766790                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1766790                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       938999                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       938999                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2705789                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2705789                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2705789                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2705789                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33605058000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  33605058000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  28689647497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  28689647497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  62294705497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  62294705497                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  62294705497                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  62294705497                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007475                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007475                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006295                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006295                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007019                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.007019                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007019                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.007019                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19020.403104                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19020.403104                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30553.437753                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30553.437753                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23022.750664                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23022.750664                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23022.750664                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23022.750664                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2337968                       # number of writebacks
+system.cpu.dcache.writebacks::total           2337968                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       800154                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       800154                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         5753                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         5753                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       805907                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       805907                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       805907                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       805907                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1766186                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1766186                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       785514                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       785514                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2551700                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2551700                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2551700                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2551700                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  33673145000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  33673145000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  23618473500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  23618473500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  57291618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  57291618500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  57291618500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  57291618500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006416                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006416                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006012                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006012                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006012                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006012                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19065.457998                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19065.457998                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30067.539853                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30067.539853                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22452.333150                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22452.333150                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22452.333150                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22452.333150                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              6016                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1043.380208                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           171393952                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              7637                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          22442.575881                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4014                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1083.903563                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           216343916                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5738                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          37703.714883                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1043.380208                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.509463                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.509463                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1621                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           16                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           41                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          275                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1224                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.791504                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         343325473                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        343325473                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    171395976                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       171395976                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     171395976                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        171395976                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    171395976                       # number of overall hits
-system.cpu.icache.overall_hits::total       171395976                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       178518                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        178518                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       178518                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         178518                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       178518                       # number of overall misses
-system.cpu.icache.overall_misses::total        178518                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1062576000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1062576000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1062576000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1062576000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1062576000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1062576000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    171574494                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    171574494                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    171574494                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    171574494                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    171574494                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    171574494                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001040                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001040                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001040                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001040                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001040                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001040                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  5952.206500                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  5952.206500                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  5952.206500                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  5952.206500                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  5952.206500                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  5952.206500                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          613                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1083.903563                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.529250                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.529250                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1724                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           39                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           78                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1566                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.841797                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         432715084                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        432715084                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    216344175                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       216344175                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     216344175                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        216344175                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    216344175                       # number of overall hits
+system.cpu.icache.overall_hits::total       216344175                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         9672                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          9672                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         9672                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           9672                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         9672                       # number of overall misses
+system.cpu.icache.overall_misses::total          9672                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    343660500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    343660500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    343660500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    343660500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    343660500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    343660500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    216353847                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    216353847                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    216353847                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    216353847                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    216353847                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    216353847                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000045                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000045                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000045                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35531.482630                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35531.482630                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35531.482630                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35531.482630                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35531.482630                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35531.482630                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          348                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 9                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    68.111111                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    43.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         6016                       # number of writebacks
-system.cpu.icache.writebacks::total              6016                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2032                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2032                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2032                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2032                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2032                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2032                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       176486                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       176486                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       176486                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       176486                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       176486                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       176486                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    805089500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    805089500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    805089500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    805089500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    805089500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    805089500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001029                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001029                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001029                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001029                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001029                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001029                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4561.775438                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  4561.775438                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4561.775438                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  4561.775438                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4561.775438                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  4561.775438                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         4014                       # number of writebacks
+system.cpu.icache.writebacks::total              4014                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2282                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2282                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2282                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2282                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2282                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2282                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7390                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         7390                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         7390                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         7390                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         7390                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         7390                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    243725000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    243725000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    243725000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    243725000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    243725000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    243725000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000034                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000034                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000034                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000034                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32980.378890                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32980.378890                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32980.378890                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 32980.378890                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32980.378890                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 32980.378890                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           355100                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29624.391257                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3897105                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           387449                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.058369                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle     189360575500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21018.110892                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   185.534699                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  8420.745667                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.641422                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005662                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.256981                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.904065                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32349                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          228                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        13364                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        18670                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987213                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         43097417                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        43097417                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      2332013                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      2332013                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         5708                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         5708                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1488                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1488                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       563712                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       563712                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         5057                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         5057                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1589822                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1589822                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         5057                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2153534                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2158591                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         5057                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2153534                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2158591                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       167317                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       167317                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       206886                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       206886                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2535                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2535                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       176564                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       176564                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2535                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       383450                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        385985                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2535                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       383450                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       385985                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      8361500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total      8361500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16391900500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  16391900500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    208226000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    208226000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14213856500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  14213856500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    208226000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  30605757000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  30813983000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    208226000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  30605757000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  30813983000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      2332013                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      2332013                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         5708                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         5708                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       168805                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       168805                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       770598                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       770598                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         7592                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         7592                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1766386                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1766386                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         7592                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2536984                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2544576                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         7592                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2536984                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2544576                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.991185                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.991185                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.268475                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.268475                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.333904                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.333904                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.099958                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.099958                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.333904                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.151144                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.151689                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.333904                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.151144                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.151689                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    49.974001                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    49.974001                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79231.559893                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79231.559893                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82140.433925                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82140.433925                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80502.574137                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80502.574137                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82140.433925                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79816.813144                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79832.073785                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82140.433925                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79816.813144                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79832.073785                       # average overall miss latency
+system.cpu.l2cache.tags.replacements           355161                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29604.694298                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3909300                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           387527                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.087813                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     233930910500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 20962.660906                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst   196.060575                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  8445.972818                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.639730                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.005983                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.257751                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.903464                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32366                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          235                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        11314                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        20752                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.987732                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         41979246                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        41979246                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      2337968                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      2337968                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         3923                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         3923                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data          317                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total          317                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       577397                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       577397                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3252                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         3252                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1588195                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1588195                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3252                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2165592                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2168844                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3252                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2165592                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2168844                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         1342                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         1342                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       206686                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       206686                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2416                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2416                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       177763                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       177763                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2416                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       384449                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        386865                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2416                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       384449                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       386865                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      2044500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total      2044500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  16338042000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  16338042000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    195535500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    195535500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  14302139500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  14302139500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    195535500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30640181500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30835717000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    195535500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30640181500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30835717000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      2337968                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      2337968                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         3923                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         3923                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1659                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         1659                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       784083                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       784083                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5668                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         5668                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1765958                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1765958                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         5668                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2550041                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2555709                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         5668                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2550041                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2555709                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.808921                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.808921                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.263602                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.263602                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.426253                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.426253                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.100661                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.100661                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.426253                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.150762                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.151373                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.426253                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.150762                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.151373                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  1523.472429                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  1523.472429                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79047.647156                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79047.647156                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80933.567881                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80933.567881                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80456.222611                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80456.222611                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80933.567881                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79698.949666                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79706.659946                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80933.567881                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79698.949666                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79706.659946                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -928,136 +927,136 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       295111                       # number of writebacks
-system.cpu.l2cache.writebacks::total           295111                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            7                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            7                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       167317                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       167317                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206886                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       206886                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2535                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2535                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       176564                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       176564                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2535                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       383450                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       385985                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2535                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       383450                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       385985                       # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   3236471489                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   3236471489                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14323040500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14323040500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    182885002                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    182885002                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12448203030                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12448203030                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    182885002                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26771243530                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  26954128532                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    182885002                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26771243530                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  26954128532                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks       294920                       # number of writebacks
+system.cpu.l2cache.writebacks::total           294920                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            9                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            9                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         1342                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         1342                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       206686                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       206686                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2416                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2416                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       177763                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       177763                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2416                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       384449                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       386865                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2416                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       384449                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       386865                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     25553999                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     25553999                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  14271182000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  14271182000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    171375500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    171375500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  12524509500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  12524509500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    171375500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  26795691500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  26967067000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    171375500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  26795691500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  26967067000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.991185                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.991185                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.268475                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.268475                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.333904                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.333904                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.099958                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.099958                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.333904                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.151144                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.151689                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.333904                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.151144                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.151689                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19343.351178                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19343.351178                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69231.559893                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69231.559893                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72143.985010                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72143.985010                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70502.497848                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70502.497848                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72143.985010                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69816.778015                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.062210                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72143.985010                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69816.778015                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.062210                       # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.808921                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.808921                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.263602                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.263602                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.426253                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.426253                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.100661                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.100661                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.426253                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.150762                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.151373                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.426253                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.150762                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.151373                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19041.728018                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19041.728018                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69047.647156                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69047.647156                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70933.567881                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70933.567881                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70456.222611                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70456.222611                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70933.567881                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69698.949666                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69706.659946                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70933.567881                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69698.949666                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69706.659946                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      5421179                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2705952                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       181282                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         3493                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3493                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       1942871                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      2627124                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         6016                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       260864                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq       168805                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp       168805                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       770598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       770598                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       176486                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1766386                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       190093                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7944466                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           8134559                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       870848                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    311615808                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          312486656                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      523994                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      3237375                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.108652                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.311202                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests      5109049                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2551690                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         8246                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2834                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2829                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            5                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       1773348                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      2632888                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         4014                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       268218                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq         1659                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp         1659                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       784083                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       784083                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         7390                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1765958                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17072                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      7649345                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           7666417                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       619648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    312832576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          313452224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      356883                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2914251                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.004390                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.066139                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2885627     89.13%     89.13% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             351748     10.87%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2901462     99.56%     99.56% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              12784      0.44%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  5      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        3237375                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     5077578963                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          1.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     264736482                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    3889880082                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             179098                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       295111                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            56587                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq           167360                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            206843                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           206843                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        179098                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1290940                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1290940                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                1290940                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43587328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43587328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                43587328                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total        2914251                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4896549913                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          1.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy      11087994                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    3825891006                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.8                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp             180179                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       294920                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            57436                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq             1352                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            206676                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           206676                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        180179                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      1127418                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total      1127418                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                1127418                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     43633600                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43633600                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                43633600                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            904999                       # Request fanout histogram
+system.membus.snoop_fanout::samples            740563                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  904999    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  740563    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              904999                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          2207449441                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         2041679000                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.5                       # Layer utilization (%)
+system.membus.snoop_fanout::total              740563                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1999132580                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         2047220500                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
index 55abb5639..19e47bc98 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.225711                       # Number of seconds simulated
-sim_ticks                                225710988500                       # Number of ticks simulated
-final_tick                               225710988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.223533                       # Number of seconds simulated
+sim_ticks                                223532962500                       # Number of ticks simulated
+final_tick                               223532962500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 329346                       # Simulator instruction rate (inst/s)
-host_op_rate                                   329346                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              186465123                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304340                       # Number of bytes of host memory used
-host_seconds                                  1210.47                       # Real time elapsed on the host
+host_inst_rate                                 354404                       # Simulator instruction rate (inst/s)
+host_op_rate                                   354404                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              198715635                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258580                       # Number of bytes of host memory used
+host_seconds                                  1124.89                       # Real time elapsed on the host
 sim_insts                                   398664665                       # Number of instructions simulated
 sim_ops                                     398664665                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          249088                       # Nu
 system.physmem.num_reads::cpu.inst               3892                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               3978                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  7870                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1103571                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1127956                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2231526                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1103571                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1103571                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1103571                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1127956                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2231526                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1114323                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1138946                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2253269                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1114323                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1114323                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1114323                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1138946                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2253269                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          7870                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        7870                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -41,15 +41,15 @@ system.physmem.bytesWrittenSys                      0                       # To
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 549                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 676                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 471                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 548                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 675                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 473                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 633                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 474                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 477                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 563                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 562                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 560                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 470                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 471                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 437                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                354                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                323                       # Per bank write bursts
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    225710901000                       # Total gap between requests
+system.physmem.totGap                    223532875000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::4                      0                       # Wr
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
 system.physmem.rdQLenPdf::0                      6816                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       969                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       971                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        83                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1545                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      324.680906                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     194.047178                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     332.516800                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            535     34.63%     34.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          349     22.59%     57.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          192     12.43%     69.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          105      6.80%     76.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           65      4.21%     80.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           39      2.52%     83.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           33      2.14%     85.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           33      2.14%     87.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          194     12.56%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1545                       # Bytes accessed per row activation
-system.physmem.totQLat                       52849750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 200412250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples         1541                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      325.149903                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.496255                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.966466                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            538     34.91%     34.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          340     22.06%     56.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          192     12.46%     69.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          106      6.88%     76.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           56      3.63%     79.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           49      3.18%     83.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           40      2.60%     85.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           36      2.34%     88.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          184     11.94%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1541                       # Bytes accessed per row activation
+system.physmem.totQLat                       51693000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 199255500                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     39350000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6715.34                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        6568.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25465.34                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.23                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25318.36                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.25                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.23                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.25                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
@@ -216,70 +216,74 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6317                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6320                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   80.27                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   80.30                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28679911.18                       # Average gap between requests
-system.physmem.pageHitRate                      80.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    6743520                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3679500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  34132800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     28403160.74                       # Average gap between requests
+system.physmem.pageHitRate                      80.30                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    6751080                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3683625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  34125000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14742137280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5830950375                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           130309976250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             150927619725                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.685069                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   216780859000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7536880000                       # Time in different power states
+system.physmem_0.refreshEnergy            14599740480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5792542920                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           129035577000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             149472420105                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.696853                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   214662823500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7464080000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1390733500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1403552000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4936680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2693625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  27003600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    4891320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2668875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  26933400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14742137280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5568136200                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           130540515000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             150885422385                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.498114                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   217165940000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7536880000                       # Time in different power states
+system.physmem_1.refreshEnergy            14599740480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5529545775                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           129266276250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             149430056100                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.507329                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   215046035000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7464080000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1005282000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1017823750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                46155674                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          26673496                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            964868                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             25433927                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                21299796                       # Number of BTB hits
+system.cpu.branchPred.lookups                45898041                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          26691639                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            566044                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             25194489                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                18810772                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             83.745605                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 8306241                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             74.662249                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8282157                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                322                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         2248490                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2235007                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            13483                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       111495                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     95501420                       # DTB read hits
-system.cpu.dtb.read_misses                        115                       # DTB read misses
+system.cpu.dtb.read_hits                     95357145                       # DTB read hits
+system.cpu.dtb.read_misses                        114                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 95501535                       # DTB read accesses
-system.cpu.dtb.write_hits                    73594615                       # DTB write hits
+system.cpu.dtb.read_accesses                 95357259                       # DTB read accesses
+system.cpu.dtb.write_hits                    73594596                       # DTB write hits
 system.cpu.dtb.write_misses                       852                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                73595467                       # DTB write accesses
-system.cpu.dtb.data_hits                    169096035                       # DTB hits
-system.cpu.dtb.data_misses                        967                       # DTB misses
+system.cpu.dtb.write_accesses                73595448                       # DTB write accesses
+system.cpu.dtb.data_hits                    168951741                       # DTB hits
+system.cpu.dtb.data_misses                        966                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                169097002                       # DTB accesses
-system.cpu.itb.fetch_hits                    98403660                       # ITB hits
-system.cpu.itb.fetch_misses                      1242                       # ITB misses
+system.cpu.dtb.data_accesses                168952707                       # DTB accesses
+system.cpu.itb.fetch_hits                    96790867                       # ITB hits
+system.cpu.itb.fetch_misses                      1237                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                98404902                       # ITB accesses
+system.cpu.itb.fetch_accesses                96792104                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,26 +297,61 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        451421977                       # number of cpu cycles simulated
+system.cpu.numCycles                        447065925                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   398664665                       # Number of instructions committed
 system.cpu.committedOps                     398664665                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       4268732                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2363843                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.132335                       # CPI: cycles per instruction
-system.cpu.ipc                               0.883131                       # IPC: instructions per cycle
-system.cpu.tickCycles                       447606238                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3815739                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.121408                       # CPI: cycles per instruction
+system.cpu.ipc                               0.891736                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass            23123356      5.80%      5.80% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               141652567     35.53%     41.33% # Class of committed instruction
+system.cpu.op_class_0::IntMult                2124322      0.53%     41.86% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     41.86% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd              35620060      8.93%     50.80% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp               7072549      1.77%     52.57% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt               2735231      0.69%     53.26% # Class of committed instruction
+system.cpu.op_class_0::FloatMult             16498021      4.14%     57.40% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv               1563283      0.39%     57.79% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     57.79% # Class of committed instruction
+system.cpu.op_class_0::MemRead               94754511     23.77%     81.56% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              73520765     18.44%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                398664665                       # Class of committed instruction
+system.cpu.tickCycles                       443407678                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3658247                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               771                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3291.720604                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           167948311                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          3291.617120                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           167826980                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              4165                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          40323.724130                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          40294.593037                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3291.720604                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.803643                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803643                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3291.617120                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803617                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803617                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3394                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           25                       # Occupied blocks per task id
@@ -320,40 +359,40 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          216
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         3113                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.828613                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         335915017                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        335915017                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     94433513                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        94433513                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73514798                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73514798                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     167948311                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        167948311                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    167948311                       # number of overall hits
-system.cpu.dcache.overall_hits::total       167948311                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         335672353                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        335672353                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     94312181                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94312181                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73514799                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73514799                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     167826980                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        167826980                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    167826980                       # number of overall hits
+system.cpu.dcache.overall_hits::total       167826980                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data         1183                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total          1183                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         5932                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         5932                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         7115                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7115                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         7115                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7115                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     87406500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     87406500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    430164000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    430164000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    517570500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    517570500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    517570500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    517570500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     94434696                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     94434696                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data         5931                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5931                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         7114                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7114                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         7114                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7114                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     88520000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     88520000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    429316500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    429316500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    517836500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    517836500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    517836500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    517836500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     94313364                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94313364                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     73520730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    167955426                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167955426                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    167955426                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167955426                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    167834094                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    167834094                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    167834094                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    167834094                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000013                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000013                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000081                       # miss rate for WriteReq accesses
@@ -362,14 +401,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000042
 system.cpu.dcache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000042                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73885.460693                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73885.460693                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72515.846258                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72515.846258                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 72743.569923                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72743.569923                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 72743.569923                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72743.569923                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74826.711750                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 74826.711750                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72385.179565                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 72385.179565                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72791.186393                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72791.186393                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72791.186393                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72791.186393                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -382,12 +421,12 @@ system.cpu.dcache.writebacks::writebacks          654                       # nu
 system.cpu.dcache.writebacks::total               654                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          214                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          214                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2736                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         2736                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         2950                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         2950                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         2950                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         2950                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         2735                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         2735                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         2949                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         2949                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         2949                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         2949                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          969                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          969                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3196                       # number of WriteReq MSHR misses
@@ -396,14 +435,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         4165
 system.cpu.dcache.demand_mshr_misses::total         4165                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         4165                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         4165                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     70744000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     70744000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    240380000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    240380000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    311124000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    311124000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    311124000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    311124000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     71272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     71272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    239421000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    239421000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    310693000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    310693000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    310693000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    310693000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -412,68 +451,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000025                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73007.223942                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73007.223942                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75212.765957                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75212.765957                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74699.639856                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 74699.639856                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74699.639856                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 74699.639856                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73552.115583                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73552.115583                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74912.703379                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74912.703379                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74596.158463                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 74596.158463                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74596.158463                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 74596.158463                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              3187                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1919.659270                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            98398495                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              5165                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          19051.015489                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              3190                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1919.630000                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            96785699                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              5168                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          18727.882933                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1919.659270                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.937334                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.937334                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1919.630000                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.937319                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.937319                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1978                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           96                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          203                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          397                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1282                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          396                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1287                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.965820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         196812485                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        196812485                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     98398495                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        98398495                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      98398495                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         98398495                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     98398495                       # number of overall hits
-system.cpu.icache.overall_hits::total        98398495                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5165                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5165                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5165                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5165                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5165                       # number of overall misses
-system.cpu.icache.overall_misses::total          5165                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    317382500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    317382500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    317382500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    317382500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    317382500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    317382500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     98403660                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     98403660                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     98403660                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     98403660                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     98403660                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     98403660                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000052                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.693127                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61448.693127                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.693127                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61448.693127                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.693127                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61448.693127                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         193586902                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        193586902                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     96785699                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        96785699                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      96785699                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         96785699                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     96785699                       # number of overall hits
+system.cpu.icache.overall_hits::total        96785699                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5168                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5168                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5168                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5168                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5168                       # number of overall misses
+system.cpu.icache.overall_misses::total          5168                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    316704500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    316704500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    316704500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    316704500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    316704500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    316704500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     96790867                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     96790867                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     96790867                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     96790867                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     96790867                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     96790867                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000053                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000053                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000053                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000053                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000053                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000053                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61281.830495                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61281.830495                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61281.830495                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61281.830495                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61281.830495                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61281.830495                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -482,70 +521,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         3187                       # number of writebacks
-system.cpu.icache.writebacks::total              3187                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5165                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         5165                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         5165                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         5165                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         5165                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         5165                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312217500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    312217500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312217500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    312217500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312217500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    312217500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000052                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000052                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000052                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000052                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60448.693127                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60448.693127                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60448.693127                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 60448.693127                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60448.693127                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 60448.693127                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         3190                       # number of writebacks
+system.cpu.icache.writebacks::total              3190                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         5168                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         5168                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         5168                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         5168                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         5168                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         5168                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    311536500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    311536500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    311536500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    311536500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    311536500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    311536500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000053                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000053                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000053                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000053                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60281.830495                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60281.830495                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60281.830495                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 60281.830495                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60281.830495                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 60281.830495                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4422.016724                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               4792                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4421.902302                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               4798                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs             5270                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.909298                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.910436                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   372.106243                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3407.923384                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   641.987096                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011356                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.104002                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.019592                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.134949                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   372.081904                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3407.854115                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   641.966284                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011355                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.103999                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.019591                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.134946                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024         5270                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          126                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          612                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          613                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4439                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.160828                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           114772                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          114772                       # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses           114820                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          114820                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks          654                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          654                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         3187                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         3187                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         3190                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         3190                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           61                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           61                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1273                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         1273                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         1276                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         1276                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data          126                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total          126                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         1273                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         1276                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          187                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            1460                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         1273                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            1463                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1276                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          187                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           1460                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1463                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         3137                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         3137                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3892                       # number of ReadCleanReq misses
@@ -558,58 +597,58 @@ system.cpu.l2cache.demand_misses::total          7870                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         3892                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         3978                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         7870                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    235063000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    235063000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    291102500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    291102500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     67816500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     67816500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    291102500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    302879500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    593982000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    291102500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    302879500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    593982000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    234104000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    234104000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    290385500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    290385500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     68345000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     68345000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    290385500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    302449000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    592834500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    290385500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    302449000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    592834500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks          654                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total          654                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         3187                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         3187                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         3190                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         3190                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         3198                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         3198                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5165                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         5165                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         5168                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         5168                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          967                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          967                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         5165                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst         5168                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         4165                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         9330                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         5165                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9333                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         5168                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         4165                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         9330                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9333                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.980926                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.980926                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.753533                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.753533                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.753096                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.753096                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.869700                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.869700                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.753533                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.753096                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.955102                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.843516                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.753533                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.843244                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.753096                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.955102                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.843516                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74932.419509                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74932.419509                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74795.092497                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74795.092497                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80637.931034                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80637.931034                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74795.092497                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76138.637506                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75474.205845                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74795.092497                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76138.637506                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75474.205845                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.843244                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.713420                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.713420                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74610.868448                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74610.868448                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81266.349584                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81266.349584                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74610.868448                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76030.417295                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75328.398983                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74610.868448                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76030.417295                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75328.398983                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -630,78 +669,78 @@ system.cpu.l2cache.demand_mshr_misses::total         7870
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         3892                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         3978                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         7870                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    203693000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    203693000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    252182500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    252182500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     59406500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     59406500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    252182500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    263099500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    515282000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    252182500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    263099500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    515282000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    202734000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    202734000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    251465500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    251465500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     59935000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     59935000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    251465500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    262669000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    514134500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    251465500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    262669000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    514134500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.980926                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.980926                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.753533                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.753533                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.753096                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.753096                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.869700                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.869700                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.753533                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.753096                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.843516                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.753533                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.843244                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.753096                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955102                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.843516                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64932.419509                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64932.419509                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64795.092497                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64795.092497                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.931034                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.931034                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64795.092497                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66138.637506                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65474.205845                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.843244                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.713420                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.713420                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64610.868448                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64610.868448                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71266.349584                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71266.349584                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64610.868448                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66030.417295                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.398983                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64610.868448                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66030.417295                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.398983                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        13288                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         3958                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        13294                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         3961                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          6132                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          6135                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          654                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         3187                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         3190                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict          117                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         3198                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         3198                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         5165                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         5168                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          967                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13517                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        13526                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9101                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             22618                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       534528                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             22627                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       534912                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       308416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             842944                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             843328                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         9330                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         9333                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               9330    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               9333    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           9330                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       10485000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           9333                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       10491000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7747500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7752000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       6247999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
@@ -724,9 +763,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                7870                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9171000                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             9176500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           41782250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           41781750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
index 29dd14148..f3497559e 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.067897                       # Number of seconds simulated
-sim_ticks                                 67896839000                       # Number of ticks simulated
-final_tick                                67896839000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.064189                       # Number of seconds simulated
+sim_ticks                                 64188759000                       # Number of ticks simulated
+final_tick                                64188759000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 250075                       # Simulator instruction rate (inst/s)
-host_op_rate                                   250075                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               45208847                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305364                       # Number of bytes of host memory used
-host_seconds                                  1501.85                       # Real time elapsed on the host
-sim_insts                                   375574808                       # Number of instructions simulated
-sim_ops                                     375574808                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 286389                       # Simulator instruction rate (inst/s)
+host_op_rate                                   286389                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               48946118                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260628                       # Number of bytes of host memory used
+host_seconds                                  1311.42                       # Real time elapsed on the host
+sim_insts                                   375574794                       # Number of instructions simulated
+sim_ops                                     375574794                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            220544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            255296                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               475840                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       220544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          220544                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3446                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               3989                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7435                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3248222                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3760057                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 7008279                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3248222                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3248222                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3248222                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             3760057                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                7008279                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7435                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            220800                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            255360                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               476160                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       220800                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          220800                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3450                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               3990                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7440                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3439855                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3978267                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 7418121                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3439855                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3439855                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3439855                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3978267                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                7418121                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7440                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7435                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7440                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   475840                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   476160                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    475840                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    476160                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 524                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 653                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 449                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 652                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 450                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 600                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 446                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 454                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 513                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 523                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 435                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 407                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                338                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 438                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 408                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                339                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                305                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                414                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                542                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                453                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                379                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                540                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                454                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                380                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     67896729500                       # Total gap between requests
+system.physmem.totGap                     64188663500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7435                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7440                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4260                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1857                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       925                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        62                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4257                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1868                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       921                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       333                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        59                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,100 +186,104 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1351                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      351.928942                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     210.322228                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     345.388131                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            435     32.20%     32.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          296     21.91%     54.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          157     11.62%     65.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           94      6.96%     72.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           63      4.66%     77.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           44      3.26%     80.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           40      2.96%     83.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           30      2.22%     85.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          192     14.21%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1351                       # Bytes accessed per row activation
-system.physmem.totQLat                       64430000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 203836250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37175000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8665.77                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1358                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      347.287187                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     206.380841                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     346.777138                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            443     32.62%     32.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          304     22.39%     55.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          160     11.78%     66.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           96      7.07%     73.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           54      3.98%     77.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           38      2.80%     80.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           38      2.80%     83.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           25      1.84%     85.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          200     14.73%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1358                       # Bytes accessed per row activation
+system.physmem.totQLat                       65294500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 204794500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37200000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8776.14                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27415.77                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           7.01                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  27526.14                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           7.42                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        7.01                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        7.42                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.05                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.05                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.06                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.06                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6082                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6069                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.80                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.57                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9132041.63                       # Average gap between requests
-system.physmem.pageHitRate                      81.80                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5851440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    3192750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  32416800                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      8627508.53                       # Average gap between requests
+system.physmem.pageHitRate                      81.57                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5843880                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3188625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  32221800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             4434643200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2090127870                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            38904370500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              45470602560                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.706043                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    64718030250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2267200000                       # Time in different power states
+system.physmem_0.refreshEnergy             4192060080                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             1996054785                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            36758466000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              42987835170                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.776911                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    61149211250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2143180000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       911143500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       890802750                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    4362120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2380125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  25529400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    4399920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2400750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  25217400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             4434643200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1924310025                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            39049824750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              45441049620                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.270777                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    64961032000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2267200000                       # Time in different power states
+system.physmem_1.refreshEnergy             4192060080                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             1854861795                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            36882319500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              42961259445                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.362844                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    61355238000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2143180000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       668141750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       684265000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                50014651                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          28998018                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            978942                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24722016                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                22941909                       # Number of BTB hits
+system.cpu.branchPred.lookups                47858697                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          27887013                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            573168                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             23334340                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                19575055                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.799507                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 9101024                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                303                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             83.889474                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 8688210                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1446                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         2339152                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2308305                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            30847                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       111425                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    102396635                       # DTB read hits
-system.cpu.dtb.read_misses                      63118                       # DTB read misses
-system.cpu.dtb.read_acv                         49453                       # DTB read access violations
-system.cpu.dtb.read_accesses                102459753                       # DTB read accesses
-system.cpu.dtb.write_hits                    78818401                       # DTB write hits
-system.cpu.dtb.write_misses                      1456                       # DTB write misses
-system.cpu.dtb.write_acv                            2                       # DTB write access violations
-system.cpu.dtb.write_accesses                78819857                       # DTB write accesses
-system.cpu.dtb.data_hits                    181215036                       # DTB hits
-system.cpu.dtb.data_misses                      64574                       # DTB misses
-system.cpu.dtb.data_acv                         49455                       # DTB access violations
-system.cpu.dtb.data_accesses                181279610                       # DTB accesses
-system.cpu.itb.fetch_hits                    49842949                       # ITB hits
-system.cpu.itb.fetch_misses                       342                       # ITB misses
-system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                49843291                       # ITB accesses
+system.cpu.dtb.read_hits                     98833092                       # DTB read hits
+system.cpu.dtb.read_misses                      28443                       # DTB read misses
+system.cpu.dtb.read_acv                           867                       # DTB read access violations
+system.cpu.dtb.read_accesses                 98861535                       # DTB read accesses
+system.cpu.dtb.write_hits                    75500788                       # DTB write hits
+system.cpu.dtb.write_misses                      1454                       # DTB write misses
+system.cpu.dtb.write_acv                            3                       # DTB write access violations
+system.cpu.dtb.write_accesses                75502242                       # DTB write accesses
+system.cpu.dtb.data_hits                    174333880                       # DTB hits
+system.cpu.dtb.data_misses                      29897                       # DTB misses
+system.cpu.dtb.data_acv                           870                       # DTB access violations
+system.cpu.dtb.data_accesses                174363777                       # DTB accesses
+system.cpu.itb.fetch_hits                    46960311                       # ITB hits
+system.cpu.itb.fetch_misses                       430                       # ITB misses
+system.cpu.itb.fetch_acv                            5                       # ITB acv
+system.cpu.itb.fetch_accesses                46960741                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,249 +297,249 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  215                       # Number of system calls
-system.cpu.numCycles                        135793681                       # number of cpu cycles simulated
+system.cpu.numCycles                        128377521                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           50500103                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      448292718                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    50014651                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           32042933                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      83951008                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2060866                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                          4                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                  172                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         13448                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           46                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  49842949                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                438776                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          135495214                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.308550                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.352263                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           47431154                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      424848239                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    47858697                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           30571570                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      80009353                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1247564                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                         13                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                  284                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         13513                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           60                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  46960311                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                225671                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          128078159                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.317101                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.349648                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 56579471     41.76%     41.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4403688      3.25%     45.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  7055956      5.21%     50.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  5366912      3.96%     54.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 11526073      8.51%     62.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  7794072      5.75%     68.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  5845240      4.31%     72.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1860126      1.37%     74.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 35063676     25.88%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 53091522     41.45%     41.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  4331488      3.38%     44.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  6713646      5.24%     50.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5106781      3.99%     54.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 10967794      8.56%     62.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  7526071      5.88%     68.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5305239      4.14%     72.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1848793      1.44%     74.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 33186825     25.91%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            135495214                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.368314                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.301278                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 43850651                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              15792236                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  70529676                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4296377                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1026274                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              9420515                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  4199                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              443538757                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 13825                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1026274                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45639997                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5068254                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         519346                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  72928908                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              10312435                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              440551913                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                438641                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2536044                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2850928                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                3712864                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           287405500                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             580024697                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        412290195                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         167734501                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             259532329                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 27873171                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              37458                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            301                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  16037778                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            104660927                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            80646144                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          12483488                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          9717177                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  409234709                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 295                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 402404750                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            453779                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        33660195                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     16045960                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             80                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     135495214                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.969882                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.211663                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            128078159                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.372797                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.309366                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 42083889                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              13603478                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  67893810                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3877357                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 619625                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              8883159                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  4198                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              421926458                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 13804                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 619625                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 43653235                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 3048927                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         516546                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  70101215                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              10138611                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              419911173                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                439346                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2543427                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2848893                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                3543199                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           273983157                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             552185759                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        393726185                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         158459573                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             259532319                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 14450838                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              37562                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            298                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  15867681                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             99739292                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            76524203                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          11895065                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          9302116                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  392194254                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 290                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 389210938                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            196221                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        16619749                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      7681566                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             75                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     128078159                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         3.038855                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.181056                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            21727779     16.04%     16.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            19323046     14.26%     30.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            22437590     16.56%     46.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18638995     13.76%     60.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            19382000     14.30%     74.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            13933331     10.28%     85.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9554257      7.05%     92.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             6216386      4.59%     96.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4281830      3.16%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17247166     13.47%     13.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            19402738     15.15%     28.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            22008781     17.18%     45.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            17964276     14.03%     59.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            19060613     14.88%     74.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            13269746     10.36%     85.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             8793023      6.87%     91.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             6106038      4.77%     96.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             4225778      3.30%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       135495214                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       128078159                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  249431      1.25%      1.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      1.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.25% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                142108      0.71%      1.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                 93369      0.47%      2.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                  4363      0.02%      2.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult              3491173     17.54%     19.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1672209      8.40%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     28.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                9312767     46.78%     75.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4941825     24.82%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  255592      1.41%      1.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      1.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                138975      0.77%      2.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                 79489      0.44%      2.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                  3727      0.02%      2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult              3445589     19.00%     21.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1648341      9.09%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     30.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8051616     44.40%     75.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4508979     24.87%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             33581      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             151497707     37.65%     37.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2128305      0.53%     38.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     38.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            37050665      9.21%     47.39% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             7361267      1.83%     49.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2793686      0.69%     49.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult           16753119      4.16%     54.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv             1596202      0.40%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            103852879     25.81%     80.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            79337339     19.72%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             146987981     37.77%     37.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2128295      0.55%     38.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     38.32% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            36418632      9.36%     47.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             7354909      1.89%     49.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2800462      0.72%     50.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult           16556521      4.25%     54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv             1584140      0.41%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     54.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             99505104     25.57%     80.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            75841313     19.49%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              402404750                       # Type of FU issued
-system.cpu.iq.rate                           2.963354                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    19907245                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.049471                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          615781749                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         258431172                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    234656399                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           344883989                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          184537520                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    162320770                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              242844978                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               179433436                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         19957407                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              389210938                       # Type of FU issued
+system.cpu.iq.rate                           3.031769                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    18132308                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.046587                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          592570653                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         242193331                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    227932630                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           332257911                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          166691582                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    158290719                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              234731368                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               172578297                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         19373689                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      9906440                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       125316                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        73841                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      7125415                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4984806                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        93159                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        70985                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      3003475                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       383693                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          3808                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       382536                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          3859                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1026274                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3908203                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                111577                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           434157595                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             99580                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             104660927                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             80646144                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                295                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   8166                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                103056                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          73841                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         825839                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       307783                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1133622                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             399257785                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             102509229                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3146965                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 619625                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1856570                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                132026                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           415917767                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            108843                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              99739292                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             76524203                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                290                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   8227                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                123512                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          70985                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         411741                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       230567                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               642308                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             387626106                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              98862428                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1584832                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      24922591                       # number of nop insts executed
-system.cpu.iew.exec_refs                    181329115                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 46548281                       # Number of branches executed
-system.cpu.iew.exec_stores                   78819886                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.940179                       # Inst execution rate
-system.cpu.iew.wb_sent                      397733168                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     396977169                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 196565794                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 281908418                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.923385                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.697268                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        35494113                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                      23723223                       # number of nop insts executed
+system.cpu.iew.exec_refs                    174364706                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 45864043                       # Number of branches executed
+system.cpu.iew.exec_stores                   75502278                       # Number of stores executed
+system.cpu.iew.exec_rate                     3.019424                       # Inst execution rate
+system.cpu.iew.wb_sent                      386487511                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     386223349                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 192322376                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 273878502                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       3.008497                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.702218                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        17254297                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            974783                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    130571429                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     3.053230                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     3.231493                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            569011                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    125612042                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     3.173777                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.248518                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     46510589     35.62%     35.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     17663753     13.53%     49.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      9427402      7.22%     56.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      8631802      6.61%     62.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      6252911      4.79%     67.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4309640      3.30%     71.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      4961322      3.80%     74.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2589236      1.98%     76.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     30224774     23.15%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     42074654     33.50%     33.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     17552788     13.97%     47.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      8725383      6.95%     54.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9055727      7.21%     61.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      6223211      4.95%     66.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4119483      3.28%     69.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      4738198      3.77%     73.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2406397      1.92%     75.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     30716201     24.45%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    130571429                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            398664583                       # Number of instructions committed
-system.cpu.commit.committedOps              398664583                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    125612042                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            398664569                       # Number of instructions committed
+system.cpu.commit.committedOps              398664569                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      168275216                       # Number of memory references committed
-system.cpu.commit.loads                      94754487                       # Number of loads committed
+system.cpu.commit.refs                      168275214                       # Number of memory references committed
+system.cpu.commit.loads                      94754486                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                   44587533                       # Number of branches committed
+system.cpu.commit.branches                   44587530                       # Number of branches committed
 system.cpu.commit.fp_insts                  155295106                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 316365839                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 316365825                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              8007752                       # Number of function calls committed.
 system.cpu.commit.op_class_0::No_OpClass     23123356      5.80%      5.80% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu        141652545     35.53%     41.33% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu        141652533     35.53%     41.33% # Class of committed instruction
 system.cpu.commit.op_class_0::IntMult         2124322      0.53%     41.86% # Class of committed instruction
 system.cpu.commit.op_class_0::IntDiv                0      0.00%     41.86% # Class of committed instruction
 system.cpu.commit.op_class_0::FloatAdd       35620060      8.93%     50.80% # Class of committed instruction
@@ -564,132 +568,132 @@ system.cpu.commit.op_class_0::SimdFloatMisc            0      0.00%     57.79% #
 system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     57.79% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     57.79% # Class of committed instruction
 system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     57.79% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead        94754487     23.77%     81.56% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite       73520729     18.44%    100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead        94754486     23.77%     81.56% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite       73520728     18.44%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total         398664583                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              30224774                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    534502374                       # The number of ROB reads
-system.cpu.rob.rob_writes                   873254462                       # The number of ROB writes
-system.cpu.timesIdled                            3162                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          298467                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   375574808                       # Number of Instructions Simulated
-system.cpu.committedOps                     375574808                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.361562                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.361562                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               2.765775                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         2.765775                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                399095542                       # number of integer regfile reads
-system.cpu.int_regfile_writes               169885767                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 156866113                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                104908933                       # number of floating regfile writes
+system.cpu.commit.op_class_0::total         398664569                       # Class of committed instruction
+system.cpu.commit.bw_lim_events              30716201                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    510811730                       # The number of ROB reads
+system.cpu.rob.rob_writes                   834310252                       # The number of ROB writes
+system.cpu.timesIdled                            3164                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          299362                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   375574794                       # Number of Instructions Simulated
+system.cpu.committedOps                     375574794                       # Number of Ops (including micro ops) Simulated
+system.cpu.cpi                               0.341816                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.341816                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.925550                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.925550                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                385452871                       # number of integer regfile reads
+system.cpu.int_regfile_writes               165252221                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 154536644                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                102074619                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                  350572                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements               777                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3293.060025                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           155551655                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4177                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37240.041896                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements               776                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3292.009184                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           152572889                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4176                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          36535.653496                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3293.060025                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.803970                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.803970                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3292.009184                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.803713                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.803713                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3400                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           45                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           22                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          212                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          211                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            7                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         3114                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         3116                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.830078                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         311150441                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        311150441                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     82050592                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        82050592                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     73501057                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       73501057                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         305192990                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        305192990                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     79071847                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        79071847                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73501036                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73501036                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data            6                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total            6                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     155551649                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        155551649                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    155551649                       # number of overall hits
-system.cpu.dcache.overall_hits::total       155551649                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1805                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1805                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        19672                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        19672                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data        21477                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total          21477                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data        21477                       # number of overall misses
-system.cpu.dcache.overall_misses::total         21477                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    128536500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    128536500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1197114453                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1197114453                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1325650953                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1325650953                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1325650953                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1325650953                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     82052397                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     82052397                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data     152572883                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        152572883                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    152572883                       # number of overall hits
+system.cpu.dcache.overall_hits::total       152572883                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1826                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1826                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19692                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19692                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21518                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21518                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21518                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21518                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    128481000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    128481000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1201737956                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1201737956                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1330218956                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1330218956                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1330218956                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1330218956                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     79073673                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     79073673                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     73520728                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     73520728                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data            6                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total            6                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    155573126                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    155573126                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    155573126                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    155573126                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    152594401                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    152594401                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    152594401                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    152594401                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000023                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000023                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000268                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.000268                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000138                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000138                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000138                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000138                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71211.357341                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71211.357341                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60853.723719                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60853.723719                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61724.214415                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61724.214415                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61724.214415                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61724.214415                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        49394                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           86                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               748                       # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000141                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000141                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000141                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000141                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70361.993428                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70361.993428                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61026.709120                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61026.709120                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61818.893763                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61818.893763                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61818.893763                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61818.893763                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        50592                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           80                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               740                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    66.034759                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           86                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    68.367568                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets           80                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks          656                       # number of writebacks
-system.cpu.dcache.writebacks::total               656                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          817                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          817                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16483                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        16483                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        17300                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        17300                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        17300                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        17300                       # number of overall MSHR hits
+system.cpu.dcache.writebacks::writebacks          655                       # number of writebacks
+system.cpu.dcache.writebacks::total               655                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          838                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          838                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16504                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16504                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        17342                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        17342                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        17342                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        17342                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          988                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          988                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3189                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         3189                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4177                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4177                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4177                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4177                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     74845500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     74845500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    249448500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    249448500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    324294000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    324294000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    324294000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    324294000                       # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3188                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3188                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4176                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4176                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4176                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4176                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     74762500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     74762500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    249321500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    249321500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    324084000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    324084000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    324084000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    324084000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000012                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
@@ -698,210 +702,210 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75754.554656                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75754.554656                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78221.542803                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78221.542803                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77638.017716                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77638.017716                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77638.017716                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77638.017716                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75670.546559                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75670.546559                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78206.242158                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78206.242158                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77606.321839                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77606.321839                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77606.321839                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77606.321839                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              2126                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1833.091155                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            49837345                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4054                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          12293.375678                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2132                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1831.246133                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            46954666                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4060                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          11565.188670                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1833.091155                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.895064                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.895064                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1831.246133                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.894163                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.894163                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1928                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0          121                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          167                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          287                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1353                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          166                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          295                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1346                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.941406                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          99689952                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         99689952                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     49837345                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        49837345                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      49837345                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         49837345                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     49837345                       # number of overall hits
-system.cpu.icache.overall_hits::total        49837345                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         5604                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          5604                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         5604                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           5604                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         5604                       # number of overall misses
-system.cpu.icache.overall_misses::total          5604                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    365347499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    365347499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    365347499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    365347499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    365347499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    365347499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     49842949                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     49842949                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     49842949                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     49842949                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     49842949                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     49842949                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000112                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000112                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000112                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000112                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000112                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000112                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65194.057637                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 65194.057637                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 65194.057637                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 65194.057637                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 65194.057637                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 65194.057637                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          644                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          93924682                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         93924682                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     46954666                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        46954666                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      46954666                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         46954666                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     46954666                       # number of overall hits
+system.cpu.icache.overall_hits::total        46954666                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5645                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5645                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5645                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5645                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5645                       # number of overall misses
+system.cpu.icache.overall_misses::total          5645                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    370489499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    370489499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    370489499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    370489499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    370489499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    370489499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     46960311                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     46960311                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     46960311                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     46960311                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     46960311                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     46960311                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000120                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000120                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000120                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000120                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000120                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000120                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65631.443578                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 65631.443578                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 65631.443578                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 65631.443578                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 65631.443578                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 65631.443578                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          496                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 7                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 8                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           92                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs           62                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         2126                       # number of writebacks
-system.cpu.icache.writebacks::total              2126                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1550                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1550                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1550                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1550                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1550                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1550                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4054                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4054                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4054                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4054                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4054                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4054                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    273942500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    273942500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    273942500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    273942500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    273942500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    273942500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000081                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000081                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000081                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000081                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67573.384312                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67573.384312                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67573.384312                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67573.384312                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67573.384312                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67573.384312                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         2132                       # number of writebacks
+system.cpu.icache.writebacks::total              2132                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1585                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1585                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1585                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1585                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1585                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1585                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4060                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4060                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4060                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4060                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4060                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4060                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    275403500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    275403500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    275403500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    275403500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    275403500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    275403500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000086                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000086                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000086                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000086                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67833.374384                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67833.374384                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67833.374384                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67833.374384                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67833.374384                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67833.374384                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4002.038570                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               3073                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             4841                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             0.634786                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4001.708243                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               3078                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             4847                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.635032                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   371.011804                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2970.742908                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   660.283858                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.011322                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090660                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.020150                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.122133                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         4841                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          147                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          136                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          528                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4030                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.147736                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            97102                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           97102                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks          656                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total          656                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         2126                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         2126                       # number of WritebackClean hits
+system.cpu.l2cache.tags.occ_blocks::writebacks   370.790492                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2968.908882                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   662.008869                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.011316                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.090604                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.020203                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.122122                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4847                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          145                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          533                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4032                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.147919                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            97187                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           97187                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks          655                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total          655                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         2132                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         2132                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          608                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total          608                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data          128                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total          128                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          608                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data          188                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst          610                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total          610                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data          126                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total          126                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          610                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          186                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total             796                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          608                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data          188                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst          610                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          186                       # number of overall hits
 system.cpu.l2cache.overall_hits::total            796                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         3129                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         3129                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3446                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3446                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          860                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          860                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3446                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         3989                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7435                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3446                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         3989                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7435                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    243935500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    243935500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    261376000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    261376000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     71927500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     71927500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    261376000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    315863000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    577239000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    261376000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    315863000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    577239000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks          656                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total          656                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         2126                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         2126                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         3189                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         3189                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4054                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         4054                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data         3128                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         3128                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3450                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3450                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          862                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          862                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3450                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3990                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7440                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3450                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3990                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7440                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    243810500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    243810500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    262807000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    262807000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     71863500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     71863500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    262807000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    315674000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    578481000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    262807000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    315674000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    578481000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks          655                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total          655                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         2132                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         2132                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3188                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3188                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4060                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4060                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          988                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          988                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4054                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4177                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8231                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4054                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4177                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8231                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981185                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.981185                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.850025                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.850025                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.870445                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.870445                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.850025                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.954992                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.903292                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.850025                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.954992                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.903292                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77959.571748                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77959.571748                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75849.100406                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75849.100406                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83636.627907                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83636.627907                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75849.100406                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79183.504638                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77638.063215                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75849.100406                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79183.504638                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77638.063215                       # average overall miss latency
+system.cpu.l2cache.demand_accesses::cpu.inst         4060                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4176                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8236                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4060                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4176                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8236                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981179                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.981179                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.849754                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.849754                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.872470                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.872470                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.849754                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.955460                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.903351                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.849754                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.955460                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.903351                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77944.533248                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77944.533248                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76175.942029                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76175.942029                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83368.329466                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83368.329466                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76175.942029                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79116.290727                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77752.822581                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76175.942029                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79116.290727                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77752.822581                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -910,115 +914,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3129                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         3129                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3446                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3446                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          860                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          860                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3446                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         3989                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7435                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3446                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         3989                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7435                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    212645500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    212645500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    226916000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    226916000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63327500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63327500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    226916000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    275973000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    502889000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    226916000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    275973000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    502889000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981185                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981185                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.850025                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.870445                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.870445                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.954992                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.903292                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.850025                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.954992                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.903292                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67959.571748                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67959.571748                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65849.100406                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65849.100406                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73636.627907                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73636.627907                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65849.100406                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69183.504638                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67638.063215                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65849.100406                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69183.504638                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67638.063215                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3128                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3128                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3450                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3450                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          862                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          862                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3450                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3990                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7440                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3450                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3990                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7440                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    212530500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    212530500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    228307000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    228307000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     63243500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     63243500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    228307000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    275774000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    504081000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    228307000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    275774000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    504081000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981179                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.981179                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.849754                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.849754                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.872470                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.872470                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.849754                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.955460                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.903351                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.849754                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.955460                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.903351                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67944.533248                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67944.533248                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66175.942029                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66175.942029                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73368.329466                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73368.329466                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66175.942029                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69116.290727                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67752.822581                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66175.942029                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69116.290727                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67752.822581                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        11134                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         2903                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        11144                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         2908                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          5042                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty          656                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         2126                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5048                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty          655                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         2132                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict          121                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         3189                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         3189                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4054                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         3188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         3188                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4060                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          988                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10234                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9131                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             19365                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       395520                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309312                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             704832                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        10252                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         9128                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             19380                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       396288                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       309184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             705472                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         8231                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         8236                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               8231    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               8236    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           8231                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        8349000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           8236                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        8359000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       6081000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       6090499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6265500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6264000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               4306                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              3129                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             3129                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4306                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14870                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  14870                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       475840                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  475840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               4312                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              3128                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             3128                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4312                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        14880                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  14880                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       476160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  476160                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7435                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7440                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7435    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7440    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7435                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             9238500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7440                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             9246500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           39203500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           39238750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
index 84e6b72bf..078507389 100644
--- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.215512                       # Number of seconds simulated
-sim_ticks                                215512229500                       # Number of ticks simulated
-final_tick                               215512229500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.211715                       # Number of seconds simulated
+sim_ticks                                211714953000                       # Number of ticks simulated
+final_tick                               211714953000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 167901                       # Simulator instruction rate (inst/s)
-host_op_rate                                   201584                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              132526721                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 327404                       # Number of bytes of host memory used
-host_seconds                                  1626.18                       # Real time elapsed on the host
+host_inst_rate                                 192926                       # Simulator instruction rate (inst/s)
+host_op_rate                                   231629                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              149595583                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280180                       # Number of bytes of host memory used
+host_seconds                                  1415.25                       # Real time elapsed on the host
 sim_insts                                   273037857                       # Number of instructions simulated
 sim_ops                                     327812214                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            218880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            266368                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               485248                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       218880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          218880                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3420                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               4162                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7582                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1015627                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1235976                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2251603                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1015627                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1015627                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1015627                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1235976                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                2251603                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          7582                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            219072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            266432                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               485504                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       219072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          219072                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3423                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               4163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7586                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              1034750                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1258447                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2293197                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1034750                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1034750                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1034750                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1258447                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                2293197                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          7586                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        7582                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        7586                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   485248                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   485504                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    485248                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    485504                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 630                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 844                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 846                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 628                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 541                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 466                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                 349                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 171                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 228                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 209                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 208                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 310                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                342                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                343                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                428                       # Per bank write bursts
 system.physmem.perBankRdBursts::12                553                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                705                       # Per bank write bursts
 system.physmem.perBankRdBursts::14                638                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                540                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                542                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    215511990500                       # Total gap between requests
+system.physmem.totGap                    211714708500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    7582                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    7586                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,9 +90,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      6627                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       894                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        61                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      6629                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       897                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        60                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1510                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      320.169536                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     189.396997                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     331.756940                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            550     36.42%     36.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          336     22.25%     58.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          179     11.85%     70.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           73      4.83%     75.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           74      4.90%     80.26% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           52      3.44%     83.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           33      2.19%     85.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           29      1.92%     87.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          184     12.19%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1510                       # Bytes accessed per row activation
-system.physmem.totQLat                       54741000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 196903500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     37910000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7219.86                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1530                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      316.067974                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     186.296863                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.878934                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            560     36.60%     36.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          363     23.73%     60.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          160     10.46%     70.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           74      4.84%     75.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           70      4.58%     80.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           59      3.86%     84.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           34      2.22%     86.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           28      1.83%     88.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          182     11.90%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1530                       # Bytes accessed per row activation
+system.physmem.totQLat                       52630500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 194868000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     37930000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6937.85                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25969.86                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           2.25                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25687.85                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           2.29                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        2.25                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        2.29                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
@@ -216,49 +216,53 @@ system.physmem.busUtilRead                       0.02                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       6065                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       6048                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.99                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   79.73                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     28424161.24                       # Average gap between requests
-system.physmem.pageHitRate                      79.99                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    5019840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2739000                       # Energy for precharge commands per rank (pJ)
+system.physmem.avgGap                     27908609.08                       # Average gap between requests
+system.physmem.pageHitRate                      79.73                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5080320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    2772000                       # Energy for precharge commands per rank (pJ)
 system.physmem_0.readEnergy                  29905200                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            14075923680                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             5641560180                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           124356115500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             144111263400                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.704665                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   206876360250                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      7196280000                       # Time in different power states
+system.physmem_0.refreshEnergy            13827746400                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             5529396150                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           122174691000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             141569591070                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.700877                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   203247000500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      7069400000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1436474750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1392729000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6373080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3477375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  28977000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    6463800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3526875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  28992600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            14075923680                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             5809762620                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           124208569500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             144133083255                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.805913                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   206629350750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      7196280000                       # Time in different power states
+system.physmem_1.refreshEnergy            13827746400                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             5726317185                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           122001953250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             141595000110                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.820896                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   202960400000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      7069400000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1684213750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1682763000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                32816919                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          16892731                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1463888                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             17497038                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                15468343                       # Number of BTB hits
+system.cpu.branchPred.lookups                32413931                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          16919661                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            738142                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             17496692                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                12856502                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             88.405495                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 6575577                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             73.479615                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6512761                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         2303892                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2264485                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            39407                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       128263                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -377,81 +381,116 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        431024459                       # number of cpu cycles simulated
+system.cpu.numCycles                        423429906                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   273037857                       # Number of instructions committed
 system.cpu.committedOps                     327812214                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       3889164                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2127081                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.578625                       # CPI: cycles per instruction
-system.cpu.ipc                               0.633463                       # IPC: instructions per cycle
-system.cpu.tickCycles                       427416966                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         3607493                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements              1354                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          3085.807941                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           168714884                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              4511                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          37400.772334                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.550810                       # CPI: cycles per instruction
+system.cpu.ipc                               0.644824                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               104312544     31.82%     31.82% # Class of committed instruction
+system.cpu.op_class_0::IntMult                2145905      0.65%     32.48% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     32.48% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd           6594343      2.01%     34.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     34.49% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp           7943502      2.42%     36.91% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt           3118180      0.95%     37.86% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv           1563217      0.48%     38.34% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc         19652356      6.00%     44.33% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult          7136937      2.18%     46.51% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc       7062098      2.15%     48.66% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt           175285      0.05%     48.72% # Class of committed instruction
+system.cpu.op_class_0::MemRead               85732248     26.15%     74.87% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              82375599     25.13%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                327812214                       # Class of committed instruction
+system.cpu.tickCycles                       420106568                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         3323338                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements              1355                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          3085.570959                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           168654881                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              4512                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          37379.184619                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  3085.807941                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.753371                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.753371                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  3085.570959                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.753313                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.753313                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         3157                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           23                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           21                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           12                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          672                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         2432                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         2431                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.770752                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         337448859                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        337448859                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     86582109                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        86582109                       # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses         337328856                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        337328856                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     86522107                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        86522107                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     82047451                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       82047451                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        63534                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         63534                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        63533                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         63533                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     168629560                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        168629560                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    168693094                       # number of overall hits
-system.cpu.dcache.overall_hits::total       168693094                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         2059                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          2059                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data     168569558                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168569558                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168633091                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168633091                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         2060                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          2060                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data         5226                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total         5226                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            5                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            5                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         7285                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           7285                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         7290                       # number of overall misses
-system.cpu.dcache.overall_misses::total          7290                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data    138607500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total    138607500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    393622500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    393622500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    532230000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    532230000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    532230000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    532230000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     86584168                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     86584168                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         7286                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           7286                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         7291                       # number of overall misses
+system.cpu.dcache.overall_misses::total          7291                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    136635000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    136635000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    394688000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    394688000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    531323000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    531323000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    531323000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    531323000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     86524167                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     86524167                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        63539                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        63539                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        63538                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        63538                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    168636845                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    168636845                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    168700384                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    168700384                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    168576844                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168576844                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168640382                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168640382                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000024                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000064                       # miss rate for WriteReq accesses
@@ -462,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000043
 system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67317.872754                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 67317.872754                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75320.034443                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75320.034443                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73058.339053                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73058.339053                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73008.230453                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73008.230453                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66327.669903                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66327.669903                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75523.918867                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75523.918867                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72923.826517                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72923.826517                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72873.817035                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72873.817035                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -488,26 +527,26 @@ system.cpu.dcache.demand_mshr_hits::cpu.data         2777
 system.cpu.dcache.demand_mshr_hits::total         2777                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.overall_mshr_hits::cpu.data         2777                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total         2777                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1638                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total         1638                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1639                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1639                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2870                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total         2870                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            3                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            3                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         4508                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         4508                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         4511                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         4511                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    111882000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    111882000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    219521500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    219521500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       238000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       238000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    331403500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    331403500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    331641500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    331641500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         4509                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4509                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4512                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4512                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    109916500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    109916500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    219842000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    219842000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       481000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       481000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    329758500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    329758500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    330239500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    330239500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000019                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
@@ -518,71 +557,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000027
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000027                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000027                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000027                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68304.029304                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68304.029304                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76488.327526                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76488.327526                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73514.529725                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 73514.529725                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73518.399468                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 73518.399468                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67063.148261                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67063.148261                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        76600                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        76600                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 160333.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 160333.333333                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73133.399867                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73133.399867                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73191.378546                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73191.378546                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             36871                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1923.837997                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            72548794                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             38807                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1869.477002                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             38168                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1923.744161                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            69641436                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             40104                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1736.520946                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1923.837997                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.939374                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.939374                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1923.744161                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.939328                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.939328                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1936                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           86                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           84                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           33                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3          276                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1485                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1483                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.945312                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         145214011                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        145214011                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     72548794                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        72548794                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      72548794                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         72548794                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     72548794                       # number of overall hits
-system.cpu.icache.overall_hits::total        72548794                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        38808                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         38808                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        38808                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          38808                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        38808                       # number of overall misses
-system.cpu.icache.overall_misses::total         38808                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    741346000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    741346000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    741346000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    741346000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    741346000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    741346000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     72587602                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     72587602                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     72587602                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     72587602                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     72587602                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     72587602                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000535                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000535                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000535                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000535                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000535                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000535                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19102.916924                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19102.916924                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19102.916924                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19102.916924                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19102.916924                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19102.916924                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses         139403186                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        139403186                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     69641436                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        69641436                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      69641436                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         69641436                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     69641436                       # number of overall hits
+system.cpu.icache.overall_hits::total        69641436                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        40105                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         40105                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        40105                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          40105                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        40105                       # number of overall misses
+system.cpu.icache.overall_misses::total         40105                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    757528000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    757528000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    757528000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    757528000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    757528000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    757528000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     69681541                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     69681541                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     69681541                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     69681541                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     69681541                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     69681541                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000576                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000576                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000576                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000576                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000576                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000576                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18888.617379                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18888.617379                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18888.617379                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18888.617379                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18888.617379                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18888.617379                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,135 +630,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        36871                       # number of writebacks
-system.cpu.icache.writebacks::total             36871                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        38808                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        38808                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        38808                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        38808                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        38808                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        38808                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    702539000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    702539000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    702539000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    702539000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    702539000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    702539000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000535                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000535                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000535                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000535                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18102.942692                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18102.942692                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18102.942692                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18102.942692                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18102.942692                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18102.942692                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        38168                       # number of writebacks
+system.cpu.icache.writebacks::total             38168                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        40105                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        40105                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        40105                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        40105                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        40105                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        40105                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    717424000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    717424000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    717424000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    717424000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    717424000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    717424000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000576                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000576                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000576                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000576                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000576                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000576                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17888.642314                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17888.642314                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17888.642314                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17888.642314                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17888.642314                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17888.642314                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         4197.336283                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              57954                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             5644                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            10.268249                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         4199.701287                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              60529                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             5648                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            10.716891                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks   353.814210                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3165.192128                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   678.329945                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.010798                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096594                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks   353.800339                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3167.579629                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   678.321319                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.010797                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.096667                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.020701                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.128093                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         5644                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           50                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           42                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2           43                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1250                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4259                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172241                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           540730                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          540730                       # Number of data accesses
+system.cpu.l2cache.tags.occ_percent::total     0.128165                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         5648                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           37                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2           42                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1251                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         4262                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.172363                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           561366                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          561366                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks         1010                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total         1010                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        21970                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        21970                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        23251                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        23251                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        35386                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        35386                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        36680                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        36680                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data          291                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total          291                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        35386                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst        36680                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data          307                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           35693                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        35386                       # number of overall hits
+system.cpu.l2cache.demand_hits::total           36987                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        36680                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data          307                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          35693                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          36987                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         2854                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         2854                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3422                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3422                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1350                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total         1350                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3422                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         4204                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          7626                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3422                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         4204                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         7626                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    215012500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    215012500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    257866500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    257866500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    106408000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total    106408000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    257866500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    321420500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    579287000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    257866500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    321420500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    579287000                       # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3425                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3425                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1351                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total         1351                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3425                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         4205                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7630                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3425                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         4205                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7630                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    215334500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    215334500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    257203500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    257203500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    104684500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total    104684500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    257203500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    320019000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    577222500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    257203500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    320019000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    577222500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks         1010                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total         1010                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        21970                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        21970                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        23251                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        23251                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         2870                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         2870                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        38808                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        38808                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data         1641                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total         1641                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        38808                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         4511                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        43319                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        38808                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         4511                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        43319                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        40105                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        40105                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data         1642                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total         1642                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        40105                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4512                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        44617                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        40105                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4512                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        44617                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994425                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.994425                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.088178                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.088178                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.822669                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.822669                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.088178                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.931944                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.176043                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.088178                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.931944                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.176043                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75337.245971                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75337.245971                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75355.493863                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75355.493863                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78820.740741                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78820.740741                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75355.493863                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76455.875357                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75962.103331                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75355.493863                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76455.875357                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75962.103331                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.085401                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.085401                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.822777                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.822777                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.085401                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.931959                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.171011                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.085401                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.931959                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.171011                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75450.070077                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75450.070077                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75095.912409                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75095.912409                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77486.676536                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77486.676536                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75095.912409                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76104.399524                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75651.703801                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75095.912409                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76104.399524                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75651.703801                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -740,113 +779,113 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data           42
 system.cpu.l2cache.overall_mshr_hits::total           44                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2854                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         2854                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3420                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3420                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1308                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1308                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3420                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         4162                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         7582                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3420                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         4162                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         7582                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    186472500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    186472500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    223532000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    223532000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     90324000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     90324000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    223532000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    276796500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    500328500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    223532000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    276796500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    500328500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3423                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3423                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1309                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1309                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3423                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         4163                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7586                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3423                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         4163                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7586                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    186794500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    186794500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    222839000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    222839000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     88850500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     88850500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    222839000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    275645000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    498484000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    222839000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    275645000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    498484000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994425                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994425                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.088126                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.088126                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.797075                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.797075                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.088126                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.175027                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.088126                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922634                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.175027                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65337.245971                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65337.245971                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65360.233918                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65360.233918                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69055.045872                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69055.045872                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65360.233918                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66505.646324                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65988.987075                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65360.233918                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66505.646324                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65988.987075                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.085351                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.085351                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.797199                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.797199                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.085351                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.922651                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.170025                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.085351                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.922651                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.170025                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65450.070077                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65450.070077                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65100.496640                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65100.496640                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67876.623377                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67876.623377                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65100.496640                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66213.067499                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65711.046665                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65100.496640                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66213.067499                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65711.046665                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        81544                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests        38329                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        15017                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        84140                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests        39625                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        15034                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         40448                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         41746                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty         1010                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        36871                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict          344                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        38168                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict          345                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         2870                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         2870                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        38808                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq         1641                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       114486                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10376                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            124862                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      4843392                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353344                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            5196736                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        40105                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq         1642                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       118377                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side        10379                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            128756                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5009408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       353408                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            5362816                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        43319                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.349062                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.476679                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        44617                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.339243                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.473458                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              28198     65.09%     65.09% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              15121     34.91%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              29481     66.08%     66.08% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              15136     33.92%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          43319                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       78653000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          44617                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       81248000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      58211498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      60156998                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       6787957                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       6789457                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               4728                       # Transaction distribution
+system.membus.trans_dist::ReadResp               4732                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              2854                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             2854                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          4728                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15164                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  15164                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485248                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  485248                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          4732                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        15172                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  15172                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       485504                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  485504                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              7582                       # Request fanout histogram
+system.membus.snoop_fanout::samples              7586                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    7582    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    7586    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                7582                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             8861000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                7586                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             8883500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           40239750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           40266000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index 95007fcba..297ece098 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,66 +1,66 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.116576                       # Number of seconds simulated
-sim_ticks                                116576497500                       # Number of ticks simulated
-final_tick                               116576497500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.111754                       # Number of seconds simulated
+sim_ticks                                111753553500                       # Number of ticks simulated
+final_tick                               111753553500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  72932                       # Simulator instruction rate (inst/s)
-host_op_rate                                    87563                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               31139070                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 321028                       # Number of bytes of host memory used
-host_seconds                                  3743.74                       # Real time elapsed on the host
+host_inst_rate                                 152363                       # Simulator instruction rate (inst/s)
+host_op_rate                                   182928                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               62361670                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292096                       # Number of bytes of host memory used
+host_seconds                                  1792.02                       # Real time elapsed on the host
 sim_insts                                   273037220                       # Number of instructions simulated
 sim_ops                                     327811602                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            620608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           4625216                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher       169088                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              5414912                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       620608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          620608                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               9697                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              72269                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         2642                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 84608                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              5323612                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39675373                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher      1450447                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                46449431                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5323612                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5323612                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5323612                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            39675373                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher      1450447                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               46449431                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         84608                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            620544                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           4626112                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher       168832                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              5415488                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       620544                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          620544                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               9696                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              72283                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         2638                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 84617                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              5552790                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             41395659                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher      1510753                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                48459202                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5552790                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5552790                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5552790                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            41395659                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher      1510753                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               48459202                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         84617                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       84608                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       84617                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  5414912                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                  5415488                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   5414912                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                   5415488                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 955                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 956                       # Per bank write bursts
 system.physmem.perBankRdBursts::1                 811                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 833                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                2939                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10638                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               59815                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 159                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 253                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 227                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 304                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               3835                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 834                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                2907                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10637                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               59817                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 152                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 259                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 225                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 303                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               3870                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                811                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               1140                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               1141                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                693                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                643                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                552                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                638                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                563                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    116576339000                       # Total gap between requests
+system.physmem.totGap                    111753395000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   84608                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   84617                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,17 +94,17 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     64943                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     17781                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       471                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       311                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                       234                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                       214                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                       178                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                       159                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                       176                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     64967                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     17796                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       465                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       298                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                       226                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                       208                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                       173                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                       172                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                       172                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                        53                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                       27                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                       21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::12                       22                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                       18                       # What read queue length does an incoming req see
@@ -190,79 +190,83 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        22133                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      244.635973                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     206.851890                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     150.002141                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           2617     11.82%     11.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8410     38.00%     49.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         7826     35.36%     85.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1287      5.81%     91.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1278      5.77%     96.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          443      2.00%     98.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           32      0.14%     98.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           31      0.14%     99.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          209      0.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          22133                       # Bytes accessed per row activation
-system.physmem.totQLat                      841969540                       # Total ticks spent queuing
-system.physmem.totMemAccLat                2428369540                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    423040000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9951.42                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples        21291                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      254.217463                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     213.921670                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     155.515771                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           2572     12.08%     12.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         7102     33.36%     45.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         8141     38.24%     83.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1445      6.79%     90.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1060      4.98%     95.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          699      3.28%     98.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           33      0.15%     98.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           27      0.13%     99.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          212      1.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          21291                       # Bytes accessed per row activation
+system.physmem.totQLat                      818886094                       # Total ticks spent queuing
+system.physmem.totMemAccLat                2405454844                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    423085000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        9677.56                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28701.42                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          46.45                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  28427.56                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          48.46                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       46.45                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       48.46                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.36                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.36                       # Data bus utilization in percentage for reads
+system.physmem.busUtil                           0.38                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.38                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.36                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                      62473                       # Number of row buffer hits during reads
+system.physmem.readRowHits                      63316                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   73.84                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   74.83                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1377840.62                       # Average gap between requests
-system.physmem.pageHitRate                      73.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  142967160                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   78007875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 595896600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      1320696.73                       # Average gap between requests
+system.physmem.pageHitRate                      74.83                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  137093040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   74802750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 595467600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             7614160320                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            63983019555                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            13820141250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              86234192760                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              739.725127                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    22625688019                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      3892720000                       # Time in different power states
+system.physmem_0.refreshEnergy             7298853120                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            61580578995                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            13031079750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              82717875255                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              740.214288                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    21327892271                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      3731520000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     90057600731                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     86689152979                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                   24358320                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   13290750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  63999000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                   23821560                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   12997875                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  64092600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             7614160320                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            11183518845                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            60135492750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              79034819985                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              677.968221                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    99984324847                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      3892720000                       # Time in different power states
+system.physmem_1.refreshEnergy             7298853120                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            10878672015                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            57506417250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              75784854420                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              678.173227                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    95612479879                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      3731520000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     12698963903                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     12405217621                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                37744347                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          20165678                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1746151                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             18664383                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                17300356                       # Number of BTB hits
+system.cpu.branchPred.lookups                35971731                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          19265386                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            984189                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             17894968                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                13923402                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             92.691818                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 7223561                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               3816                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             77.806241                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 6951964                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               4431                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups         2517343                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            2473442                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            43901                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted       128855                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,233 +385,233 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  191                       # Number of system calls
-system.cpu.numCycles                        233152996                       # number of cpu cycles simulated
+system.cpu.numCycles                        223507108                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           12613908                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      334078036                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    37744347                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           24523917                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     217730977                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3511013                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1155                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles             1                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         2593                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  89097958                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 22048                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          232104140                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.745924                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.249191                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           12083599                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      309381854                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    35971731                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           23348808                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     209499863                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1989645                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 1258                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            93                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles         2666                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  82203342                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 33398                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          222582301                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.671920                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.267628                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 58364721     25.15%     25.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 42980177     18.52%     43.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 30021674     12.93%     56.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                100737568     43.40%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 62373241     28.02%     28.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 40203334     18.06%     46.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 28080746     12.62%     58.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 91924980     41.30%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            232104140                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.161887                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.432870                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 28023980                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              70770832                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 108573375                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              23115192                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1620761                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              6880073                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                135178                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              363549116                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               6170266                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1620761                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 45363672                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                24814789                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         341984                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 113350212                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              46612722                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              355770088                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts               2890615                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               6644499                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 177384                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7802434                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               21145232                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents          2810415                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           403411912                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2534053104                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        350245362                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups         194900491                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            222582301                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.160942                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.384215                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 26238985                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              73050782                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  98117127                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              24314460                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 860947                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              6686817                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                134221                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              348541423                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               3410145                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 860947                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 42548430                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                23450678                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         285531                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 105165670                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              50271045                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              344601348                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               1453656                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               7084396                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  85832                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                7483674                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               23725025                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents          3279176                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           394880845                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2465405554                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        335914250                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups         192916662                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             372230051                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 31181861                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              16825                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          16811                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  55467243                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             92417326                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            88498414                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1663819                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1859064                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  353254299                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               27832                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 346438253                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           2301561                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        25470529                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     73751649                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           5712                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     232104140                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.492598                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.113201                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 22650794                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              11588                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          11554                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  57533645                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             89989968                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            84391268                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1975718                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1902358                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  343283622                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               22608                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 339469619                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            966789                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        15494628                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     40533427                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            488                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     222582301                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.525142                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.109331                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            47511464     20.47%     20.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            78618745     33.87%     54.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            60884809     26.23%     80.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            34936770     15.05%     95.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             9533364      4.11%     99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5              607804      0.26%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6               11184      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            42440680     19.07%     19.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            76122495     34.20%     53.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            59389973     26.68%     79.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            34692267     15.59%     95.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             9226095      4.15%     99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5              678749      0.30%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6               32042      0.01%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       232104140                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       222582301                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 9573854      7.69%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   7345      0.01%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd            255499      0.21%      7.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp            127544      0.10%      8.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt             93452      0.08%      8.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv             56991      0.05%      8.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc           707524      0.57%      8.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult           297297      0.24%      8.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc        683417      0.55%      9.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               53764278     43.17%     52.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              58976477     47.35%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 9228112      7.75%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   7358      0.01%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd            237798      0.20%      7.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp            147681      0.12%      8.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt             70485      0.06%      8.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv             67886      0.06%      8.19% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc           638269      0.54%      8.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult           297789      0.25%      8.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc        542439      0.46%      9.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.44% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               51542568     43.28%     52.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              56315471     47.29%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             110655125     31.94%     31.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              2148158      0.62%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd         6798099      1.96%     34.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         8667622      2.50%     37.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         3332487      0.96%     37.99% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv         1592703      0.46%     38.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       20931016      6.04%     44.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult        7182327      2.07%     46.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc      7148965      2.06%     48.63% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt         175286      0.05%     48.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             91923310     26.53%     75.21% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            85883155     24.79%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             108184507     31.87%     31.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              2148145      0.63%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     32.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd         6792731      2.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     34.50% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         8635726      2.54%     37.05% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         3210403      0.95%     37.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv         1592905      0.47%     38.46% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       20864008      6.15%     44.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult        7178651      2.11%     46.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc      7141492      2.10%     48.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt         175295      0.05%     48.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             90027492     26.52%     75.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            83518264     24.60%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              346438253                       # Type of FU issued
-system.cpu.iq.rate                           1.485884                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   124543678                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.359497                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          764166778                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         251741027                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    223260031                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads           287659107                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes          127022045                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses    117425060                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              303322253                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses               167659678                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          5063326                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              339469619                       # Type of FU issued
+system.cpu.iq.rate                           1.518831                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   119095856                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.350829                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          738018306                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         235153924                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    219171367                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads           283565878                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes          123658767                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses    116921576                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              293614389                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses               164951086                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          5389138                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6685051                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13552                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        10416                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      6122797                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      4257693                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7295                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11836                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2015651                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       155252                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        607596                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       126905                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        613909                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1620761                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 2118966                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                346415                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           353282999                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 860947                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1344821                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                736472                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           343307622                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              92417326                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             88498414                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              16799                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   8049                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                352915                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          10416                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1220605                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       439066                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1659671                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             342448265                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              90703428                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3989988                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              89989968                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             84391268                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              11575                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   7371                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                729404                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11836                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         437891                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       454375                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               892266                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             337441545                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              89439870                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           2028074                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                           868                       # number of nop insts executed
-system.cpu.iew.exec_refs                    175290651                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31753222                       # Number of branches executed
-system.cpu.iew.exec_stores                   84587223                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.468771                       # Inst execution rate
-system.cpu.iew.wb_sent                      340943350                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     340685091                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 153596503                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 266530182                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.461208                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.576282                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        23083392                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                          1392                       # number of nop insts executed
+system.cpu.iew.exec_refs                    172567373                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31555849                       # Number of branches executed
+system.cpu.iew.exec_stores                   83127503                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.509758                       # Inst execution rate
+system.cpu.iew.wb_sent                      336239137                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     336092943                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 151867680                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 263704827                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.503724                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.575900                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        14172678                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           22120                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1611406                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    228378913                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.435387                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.036441                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            850314                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    220392023                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.487405                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.078236                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     94653047     41.45%     41.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     70419351     30.83%     72.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     20855772      9.13%     81.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     13391170      5.86%     87.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8734239      3.82%     91.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      4529616      1.98%     93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      3006865      1.32%     94.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      2429241      1.06%     95.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     10359612      4.54%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     89247998     40.50%     40.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     67546822     30.65%     71.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     20918501      9.49%     80.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     13253983      6.01%     86.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      8642695      3.92%     90.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      4496391      2.04%     92.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3033426      1.38%     93.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      2604506      1.18%     95.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     10647701      4.83%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    228378913                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    220392023                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            273037832                       # Number of instructions committed
 system.cpu.commit.committedOps              327812214                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -653,395 +657,395 @@ system.cpu.commit.op_class_0::MemWrite       82375617     25.13%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         327812214                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              10359612                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    568912384                       # The number of ROB reads
-system.cpu.rob.rob_writes                   705520379                       # The number of ROB writes
-system.cpu.timesIdled                           58444                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                         1048856                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              10647701                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    551726691                       # The number of ROB reads
+system.cpu.rob.rob_writes                   686162246                       # The number of ROB writes
+system.cpu.timesIdled                           18335                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          924807                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   273037220                       # Number of Instructions Simulated
 system.cpu.committedOps                     327811602                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.853924                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.853924                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.171065                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.171065                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                331328732                       # number of integer regfile reads
-system.cpu.int_regfile_writes               136938455                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                 187108865                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                132177694                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                1297131127                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 80243114                       # number of cc regfile writes
-system.cpu.misc_regfile_reads              1183136277                       # number of misc regfile reads
+system.cpu.cpi                               0.818596                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.818596                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.221604                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.221604                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                325161919                       # number of integer regfile reads
+system.cpu.int_regfile_writes               134094717                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                 186641875                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                131668024                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                1279432977                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 80060950                       # number of cc regfile writes
+system.cpu.misc_regfile_reads              1175447344                       # number of misc regfile reads
 system.cpu.misc_regfile_writes               34421755                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           1533838                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.844582                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           163641356                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           1534350                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            106.651909                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          84508000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.844582                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999696                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999696                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           1542955                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.836799                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           162076726                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           1543467                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            105.008222                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          85416000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.836799                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999681                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999681                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          109                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          311                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2           91                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          112                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          309                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           90                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4            1                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         336640002                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        336640002                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     82608606                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        82608606                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     80940468                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       80940468                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        70474                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         70474                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        10911                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        10911                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses         333528119                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        333528119                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     81065236                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        81065236                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     80920030                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       80920030                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        69611                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         69611                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        10906                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        10906                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     163549074                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        163549074                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    163619548                       # number of overall hits
-system.cpu.dcache.overall_hits::total       163619548                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2799218                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2799218                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1112231                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1112231                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     161985266                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        161985266                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    162054877                       # number of overall hits
+system.cpu.dcache.overall_hits::total       162054877                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2782957                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2782957                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1132669                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1132669                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data           18                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total           18                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            5                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            5                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      3911449                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3911449                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3911467                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3911467                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  31000710000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  31000710000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   8973513996                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   8973513996                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       189000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       189000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  39974223996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  39974223996                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  39974223996                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  39974223996                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     85407824                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     85407824                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      3915626                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3915626                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3915644                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3915644                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  31092984500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  31092984500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9127104911                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9127104911                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       182000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       182000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  40220089411                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  40220089411                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  40220089411                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  40220089411                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     83848193                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     83848193                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     82052699                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     82052699                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data        70492                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total        70492                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10916                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        10916                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data        69629                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total        69629                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10910                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        10910                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    167460523                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    167460523                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    167531015                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    167531015                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032775                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.032775                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013555                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.013555                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000255                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.000255                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000458                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000458                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023357                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023357                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.023348                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.023348                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11074.775169                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11074.775169                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8068.030828                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  8068.030828                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        37800                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        37800                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.799362                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10219.799362                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.752332                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10219.752332                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data    165900892                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    165900892                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    165970521                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    165970521                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.033190                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.033190                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013804                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.013804                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.000259                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.000259                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000367                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000367                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.023602                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.023602                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.023592                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.023592                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11172.642804                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11172.642804                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8058.051303                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  8058.051303                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        45500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        45500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10271.688208                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10271.688208                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10271.640990                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10271.640990                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      1061203                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      1079488                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          134969                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          136770                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets     7.862568                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets     7.892725                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1533838                       # number of writebacks
-system.cpu.dcache.writebacks::total           1533838                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1485532                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1485532                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       891576                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       891576                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            5                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            5                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2377108                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2377108                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2377108                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2377108                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1313686                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1313686                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220655                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       220655                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      1542955                       # number of writebacks
+system.cpu.dcache.writebacks::total           1542955                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1460236                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1460236                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       911920                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       911920                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2372156                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2372156                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2372156                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2372156                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1322721                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1322721                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       220749                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       220749                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data           11                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total           11                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1534341                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1534341                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1534352                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1534352                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15231288500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  15231288500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1828348773                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1828348773                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       681500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       681500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17059637273                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17059637273                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17060318773                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  17060318773                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015381                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015381                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002689                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002689                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000156                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000156                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009162                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.009162                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009159                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.009159                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11594.314395                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11594.314395                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8286.006540                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8286.006540                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61954.545455                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61954.545455                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.543579                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.543579                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.908030                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.908030                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_misses::cpu.data      1543470                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1543470                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1543481                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1543481                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15298451500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  15298451500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1831859691                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1831859691                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       695500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       695500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17130311191                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17130311191                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17131006691                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17131006691                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015775                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015775                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002690                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002690                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.000158                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.000158                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.009304                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.009304                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.009300                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.009300                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11565.894471                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11565.894471                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8298.382738                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8298.382738                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 63227.272727                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 63227.272727                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11098.570877                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11098.570877                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11098.942385                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11098.942385                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            715978                       # number of replacements
-system.cpu.icache.tags.tagsinuse           511.829667                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            88375700                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            716490                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            123.345336                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         330590500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   511.829667                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.999667                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.999667                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            726201                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.803602                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            81470529                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            726713                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            112.108259                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         331355500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.803602                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999616                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999616                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          246                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           12                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          131                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          242                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3           14                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4           69                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         178912379                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        178912379                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     88375700                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        88375700                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      88375700                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         88375700                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     88375700                       # number of overall hits
-system.cpu.icache.overall_hits::total        88375700                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       722244                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        722244                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       722244                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         722244                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       722244                       # number of overall misses
-system.cpu.icache.overall_misses::total        722244                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   6486047445                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   6486047445                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   6486047445                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   6486047445                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   6486047445                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   6486047445                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     89097944                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     89097944                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     89097944                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     89097944                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     89097944                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     89097944                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008106                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.008106                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.008106                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.008106                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.008106                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.008106                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8980.410284                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8980.410284                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8980.410284                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8980.410284                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8980.410284                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8980.410284                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        66919                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         165133375                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        165133375                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     81470529                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        81470529                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      81470529                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         81470529                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     81470529                       # number of overall hits
+system.cpu.icache.overall_hits::total        81470529                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       732796                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        732796                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       732796                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         732796                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       732796                       # number of overall misses
+system.cpu.icache.overall_misses::total        732796                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   6565806949                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   6565806949                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   6565806949                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   6565806949                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   6565806949                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   6565806949                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     82203325                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     82203325                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     82203325                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     82203325                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     82203325                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     82203325                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008914                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.008914                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.008914                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.008914                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.008914                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.008914                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8959.938303                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8959.938303                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8959.938303                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8959.938303                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8959.938303                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8959.938303                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        64284                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           94                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              2190                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3051                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    30.556621                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    21.069813                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    31.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       715978                       # number of writebacks
-system.cpu.icache.writebacks::total            715978                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         5753                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         5753                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         5753                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         5753                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         5753                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         5753                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       716491                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       716491                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       716491                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       716491                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       716491                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       716491                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   6035135455                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   6035135455                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   6035135455                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   6035135455                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   6035135455                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   6035135455                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008042                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008042                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008042                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.008042                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008042                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.008042                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8423.183899                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8423.183899                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8423.183899                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  8423.183899                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8423.183899                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  8423.183899                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       726201                       # number of writebacks
+system.cpu.icache.writebacks::total            726201                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         6071                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         6071                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         6071                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         6071                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         6071                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         6071                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       726725                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       726725                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       726725                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       726725                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       726725                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       726725                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   6109081458                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   6109081458                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   6109081458                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   6109081458                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   6109081458                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   6109081458                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.008841                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.008841                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.008841                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.008841                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.008841                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.008841                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8406.318013                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  8406.318013                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8406.318013                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  8406.318013                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8406.318013                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  8406.318013                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       404830                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       404871                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit           38                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       402434                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       402547                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit          102                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        28177                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage        28085                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         5610.545509                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            3011470                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             6745                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs           446.474426                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         5603.177963                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            3041133                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             6750                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs           450.538222                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  5502.326450                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   108.219059                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.335835                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006605                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.342441                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          498                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         6247                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks  5495.535708                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   107.642255                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.335421                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006570                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.341991                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          497                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         6253                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0           16                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::1           22                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::2          344                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::3            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          114                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           73                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          906                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           71                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5055                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.030396                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.381287                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         68984443                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        68984443                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       965413                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       965413                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      1035068                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      1035068                       # number of WritebackClean hits
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          113                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          146                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          912                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3           72                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         5048                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.030334                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.381653                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         69530063                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        69530063                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       968360                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       968360                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      1046226                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      1046226                       # number of WritebackClean hits
 system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       219881                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       219881                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       706254                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       706254                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1242123                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1242123                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       706254                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      1462004                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2168258                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       706254                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      1462004                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2168258                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data          772                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          772                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9709                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         9709                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        71574                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        71574                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         9709                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        72346                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         82055                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         9709                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        72346                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        82055                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        19500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total        19500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     55912000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     55912000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    697540000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    697540000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   5069165500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   5069165500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    697540000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   5125077500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   5822617500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    697540000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   5125077500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   5822617500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       965413                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       965413                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      1035068                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      1035068                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            2                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            2                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       220653                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       220653                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       715963                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       715963                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1313697                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      1313697                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       715963                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      1534350                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2250313                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       715963                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      1534350                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2250313                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.500000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.500000                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003499                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.003499                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.013561                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.013561                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.054483                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.054483                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.013561                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.047151                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.036464                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.013561                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.047151                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.036464                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        19500                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        19500                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72424.870466                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72424.870466                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71844.680194                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71844.680194                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70824.119094                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70824.119094                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71844.680194                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70841.200619                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 70959.935409                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71844.680194                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70841.200619                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 70959.935409                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_hits::cpu.data       219964                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       219964                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       716938                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       716938                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1251135                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1251135                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       716938                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1471099                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2188037                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       716938                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1471099                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2188037                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           13                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           13                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          781                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          781                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9708                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         9708                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        71587                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        71587                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         9708                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        72368                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         82076                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         9708                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        72368                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        82076                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        40000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total        40000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56104500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     56104500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    688634000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    688634000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   5061315000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   5061315000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    688634000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   5117419500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   5806053500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    688634000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   5117419500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   5806053500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       968360                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       968360                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      1046226                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      1046226                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           14                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           14                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       220745                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       220745                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       726646                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       726646                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1322722                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      1322722                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       726646                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1543467                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2270113                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       726646                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1543467                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2270113                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.928571                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.928571                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003538                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.003538                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.013360                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.013360                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.054121                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.054121                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.013360                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.046887                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.036155                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.013360                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.046887                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.036155                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data  3076.923077                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total  3076.923077                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71836.747759                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71836.747759                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70934.693037                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70934.693037                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70701.593865                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70701.593865                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70934.693037                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70713.844517                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 70739.966616                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70934.693037                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70713.844517                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 70739.966616                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1050,151 +1054,151 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           44                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total           44                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data           51                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total           51                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           12                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           12                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           33                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total           33                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           34                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total           34                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst           12                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data           77                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           89                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           85                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           97                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst           12                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data           77                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           89                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        51610                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total        51610                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          728                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          728                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9697                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9697                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        71541                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        71541                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         9697                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        72269                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        81966                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         9697                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        72269                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        51610                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       133576                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    180856312                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    180856312                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        13500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        13500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     50141500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     50141500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    638754500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    638754500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4638052000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4638052000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    638754500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4688193500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   5326948000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    638754500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4688193500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    180856312                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   5507804312                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data           85                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           97                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher        51651                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total        51651                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           13                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           13                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          730                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          730                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9696                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9696                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        71553                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        71553                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         9696                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        72283                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        81979                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         9696                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        72283                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher        51651                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       133630                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher    178131300                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total    178131300                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       187000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       187000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     50303500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     50303500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    629910500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    629910500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   4630072500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   4630072500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    629910500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4680376000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5310286500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    629910500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4680376000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher    178131300                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5488417800                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.500000                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003299                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003299                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013544                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.054458                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.054458                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.047101                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.036424                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013544                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.047101                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.928571                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.928571                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.003307                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.003307                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.013343                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.013343                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.054095                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.054095                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.013343                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.046832                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.036112                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.013343                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.046832                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.059359                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3504.288161                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3504.288161                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        13500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        13500                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68875.686813                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68875.686813                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.351965                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.351965                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64830.684503                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64830.684503                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.351965                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64871.431734                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.727448                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.351965                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64871.431734                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3504.288161                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41233.487393                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.058865                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3448.748330                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total  3448.748330                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14384.615385                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14384.615385                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68908.904110                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68908.904110                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64966.016914                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64966.016914                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64708.293153                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64708.293153                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64966.016914                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64750.715936                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64776.180485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64966.016914                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64750.715936                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher  3448.748330                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41071.748859                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      4500659                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      2249836                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       249343                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       130206                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        52860                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        77346                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       2030188                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       965413                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      1284403                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        81238                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq        52998                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            2                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       220653                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       220653                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       716491                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      1313697                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2148432                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4602542                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           6750974                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     91644224                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    196364032                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          288008256                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      134764                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      2385079                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.191572                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.468754                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests      4539362                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      2269187                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       254586                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       130262                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops        52910                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        77352                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       2049447                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       968360                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      1300796                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        81249                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq        53022                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           14                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           14                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       220745                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       220745                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       726725                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      1322722                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2179572                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      4629917                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           6809489                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     92982208                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    197531008                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          290513216                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      134350                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      2404477                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.192237                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.468638                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            2005511     84.09%     84.09% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             302222     12.67%     96.76% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              77346      3.24%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            2019600     83.99%     83.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             307525     12.79%     96.78% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              77352      3.22%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        2385079                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     4500145500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          3.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    1075017936                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    2302043463                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          2.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              83880                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                1                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               728                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              728                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         83880                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       169217                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 169217                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      5414912                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                 5414912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoop_fanout::total        2404477                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     4538837000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          4.1                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    1090392888                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.0                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    2315538337                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp              83887                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               13                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               730                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              730                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         83887                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       169247                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 169247                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port      5415488                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                 5415488                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             84609                       # Request fanout histogram
+system.membus.snoop_fanout::samples             84630                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   84609    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   84630    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               84609                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           103435410                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               84630                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           108151910                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          446648668                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          445724357                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
index fb73a0a48..a78600dd4 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,69 +1,69 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.560955                       # Number of seconds simulated
-sim_ticks                                560955232000                       # Number of ticks simulated
-final_tick                               560955232000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.504258                       # Number of seconds simulated
+sim_ticks                                504258263000                       # Number of ticks simulated
+final_tick                               504258263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 326346                       # Simulator instruction rate (inst/s)
-host_op_rate                                   326346                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              197101410                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309500                       # Number of bytes of host memory used
-host_seconds                                  2846.02                       # Real time elapsed on the host
+host_inst_rate                                 397765                       # Simulator instruction rate (inst/s)
+host_op_rate                                   397765                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              215954385                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 262596                       # Number of bytes of host memory used
+host_seconds                                  2335.02                       # Real time elapsed on the host
 sim_insts                                   928789150                       # Number of instructions simulated
 sim_ops                                     928789150                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            184896                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18519872                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18704768                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       184896                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          184896                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            185088                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18520000                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18705088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       185088                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          185088                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2889                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289373                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292262                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2892                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289375                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292267                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               329609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             33014884                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                33344493                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          329609                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             329609                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7607937                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7607937                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7607937                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              329609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            33014884                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               40952430                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292262                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               367050                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             36727212                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                37094262                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          367050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             367050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8463346                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8463346                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8463346                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              367050                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            36727212                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               45557607                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292267                       # Number of read requests accepted
 system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      292262                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      292267                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18684608                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20160                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266752                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18704768                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18685248                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     19840                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4266176                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18705088                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      315                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      310                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               18033                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18359                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18363                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               18394                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18332                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18249                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18255                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18314                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18296                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18227                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18236                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18341                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18245                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18249                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18313                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18290                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18231                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18232                       # Per bank write bursts
 system.physmem.perBankRdBursts::10              18229                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              18376                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18263                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18132                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18061                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18191                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18272                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18137                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18064                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18188                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
@@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5                4099                       # Pe
 system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4192                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4183                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
@@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    560955150000                       # Total gap between requests
+system.physmem.totGap                    504258181000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292262                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292267                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,8 +97,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    291448                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       471                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    291455                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       474                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      933                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      934                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4044                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4049                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      936                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      937                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4051                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::20                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::21                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::22                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     4050                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::24                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4053                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4050                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4051                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4050                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4052                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4051                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4049                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4049                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,121 +193,125 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       104067                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      220.533003                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     142.789866                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     268.043159                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          38344     36.85%     36.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        44004     42.28%     79.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         8921      8.57%     87.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          721      0.69%     88.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1372      1.32%     89.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1145      1.10%     90.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          668      0.64%     91.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          598      0.57%     92.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8294      7.97%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         104067                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4050                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        71.768889                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.564435                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      763.185509                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4041     99.78%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.80% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            4      0.10%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-16383            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       103155                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      222.473443                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     144.311324                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     268.647767                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          37345     36.20%     36.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43741     42.40%     78.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9241      8.96%     87.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          735      0.71%     88.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         1396      1.35%     89.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1157      1.12%     90.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          662      0.64%     91.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          564      0.55%     91.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8314      8.06%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         103155                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4049                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        69.893801                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.549322                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      747.524050                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4041     99.80%     99.80% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::10240-11263            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::13312-14335            2      0.05%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            1      0.02%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::15360-16383            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-17407            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4050                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4050                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.461235                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.440549                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.842853                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3116     76.94%     76.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  1      0.02%     76.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                932     23.01%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4050                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2934449500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8408455750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1459735000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       10051.31                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4049                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4049                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.463077                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.442287                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.845052                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3113     76.88%     76.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                933     23.04%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  3      0.07%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4049                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3567632750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9041826500                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459785000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12219.72                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28801.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          33.31                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           7.61                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       33.34                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        7.61                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30969.72                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          37.05                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           8.46                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       37.09                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        8.46                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.32                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.26                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.36                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.29                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.62                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     202530                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     52011                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   69.37                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.00                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1562788.59                       # Average gap between requests
-system.physmem.pageHitRate                      70.98                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  392416920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  214116375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1140391200                       # Energy for read commands per rank (pJ)
+system.physmem.avgWrQLen                        24.27                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     203404                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52048                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   69.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.05                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1404814.55                       # Average gap between requests
+system.physmem.pageHitRate                      71.23                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  388939320                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  212218875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1140243000                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            36638696640                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           109486358955                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           240531047250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             388619465820                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              692.784540                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   399461576500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18731440000                       # Time in different power states
+system.physmem_0.refreshEnergy            32935362720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           104730111945                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           210683510250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             350306824590                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              694.703966                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   349825620000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     16838120000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    142759852250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    137589656250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  394276680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  215131125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1136522400                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215570160                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            36638696640                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           109506441195                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           240513431250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             388620069450                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              692.785616                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   399429681750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18731440000                       # Time in different power states
+system.physmem_1.actEnergy                  390829320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  213250125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1136538000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215511840                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            32935362720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           105447215835                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           210054471750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             350393179590                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              694.875219                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   348773258750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     16838120000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    142792236250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    138643034750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               125747709                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          81143389                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12156447                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            103980471                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83512685                       # Number of BTB hits
+system.cpu.branchPred.lookups               123840342                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          79869322                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            685088                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            102061444                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                68186680                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             80.315740                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18691016                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               9451                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             66.809441                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18691358                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               9446                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        14052117                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           14048642                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             3475                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        11780                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    237537764                       # DTB read hits
-system.cpu.dtb.read_misses                     198464                       # DTB read misses
+system.cpu.dtb.read_hits                    237538322                       # DTB read hits
+system.cpu.dtb.read_misses                     198467                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                237736228                       # DTB read accesses
-system.cpu.dtb.write_hits                    98304946                       # DTB write hits
-system.cpu.dtb.write_misses                      7177                       # DTB write misses
+system.cpu.dtb.read_accesses                237736789                       # DTB read accesses
+system.cpu.dtb.write_hits                    98305180                       # DTB write hits
+system.cpu.dtb.write_misses                      7178                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                98312123                       # DTB write accesses
-system.cpu.dtb.data_hits                    335842710                       # DTB hits
-system.cpu.dtb.data_misses                     205641                       # DTB misses
+system.cpu.dtb.write_accesses                98312358                       # DTB write accesses
+system.cpu.dtb.data_hits                    335843502                       # DTB hits
+system.cpu.dtb.data_misses                     205645                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                336048351                       # DTB accesses
-system.cpu.itb.fetch_hits                   316984906                       # ITB hits
-system.cpu.itb.fetch_misses                       120                       # ITB misses
+system.cpu.dtb.data_accesses                336049147                       # DTB accesses
+system.cpu.itb.fetch_hits                   285763790                       # ITB hits
+system.cpu.itb.fetch_misses                       119                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               316985026                       # ITB accesses
+system.cpu.itb.fetch_accesses               285763909                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -321,83 +325,118 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                       1121910464                       # number of cpu cycles simulated
+system.cpu.numCycles                       1008516526                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   928789150                       # Number of instructions committed
 system.cpu.committedOps                     928789150                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      30861351                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                        316849                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.207928                       # CPI: cycles per instruction
-system.cpu.ipc                               0.827864                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1059707465                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        62202999                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.085840                       # CPI: cycles per instruction
+system.cpu.ipc                               0.920946                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass            86206875      9.28%      9.28% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               486529511     52.38%     61.66% # Class of committed instruction
+system.cpu.op_class_0::IntMult                   7040      0.00%     61.67% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     61.67% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd              13018262      1.40%     63.07% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp               3826477      0.41%     63.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt               3187663      0.34%     63.82% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    4      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     63.82% # Class of committed instruction
+system.cpu.op_class_0::MemRead              237705247     25.59%     89.42% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              98308071     10.58%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                928789150                       # Class of committed instruction
+system.cpu.tickCycles                       957154131                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        51362395                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            776530                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.728000                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           322866540                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4092.342308                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           321596153                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            780626                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            413.599521                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         898816500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.728000                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999201                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999201                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            411.972126                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         901583500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.342308                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999107                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999107                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          204                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          951                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1242                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1642                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          214                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          956                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1398                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1472                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         648211872                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        648211872                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    224702494                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       224702494                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     98164046                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       98164046                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     322866540                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        322866540                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    322866540                       # number of overall hits
-system.cpu.dcache.overall_hits::total       322866540                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses         645671096                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        645671096                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    223432106                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       223432106                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     98164047                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       98164047                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     321596153                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        321596153                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    321596153                       # number of overall hits
+system.cpu.dcache.overall_hits::total       321596153                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       711929                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        711929                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137154                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137154                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       849083                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         849083                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       849083                       # number of overall misses
-system.cpu.dcache.overall_misses::total        849083                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24904735500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24904735500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9954481000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9954481000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34859216500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34859216500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34859216500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34859216500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    225414423                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    225414423                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data       137153                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137153                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       849082                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         849082                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       849082                       # number of overall misses
+system.cpu.dcache.overall_misses::total        849082                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  25457059500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  25457059500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10110916000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10110916000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35567975500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35567975500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35567975500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35567975500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    224144035                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    224144035                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    323715623                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    323715623                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    323715623                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    323715623                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003158                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003158                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    322445235                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    322445235                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    322445235                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    322445235                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003176                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003176                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001395                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001395                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002623                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002623                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.002623                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.002623                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34982.049474                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34982.049474                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72578.860259                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 72578.860259                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41055.134186                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41055.134186                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41055.134186                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41055.134186                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002633                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002633                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002633                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.002633                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35757.862792                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 35757.862792                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73719.976960                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73719.976960                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41889.918170                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41889.918170                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41889.918170                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41889.918170                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -406,16 +445,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88497                       # number of writebacks
-system.cpu.dcache.writebacks::total             88497                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks        88489                       # number of writebacks
+system.cpu.dcache.writebacks::total             88489                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          314                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          314                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68143                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68143                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        68457                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        68457                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        68457                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        68457                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68142                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68142                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        68456                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        68456                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        68456                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        68456                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data       711615                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       711615                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69011                       # number of WriteReq MSHR misses
@@ -424,85 +463,85 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       780626
 system.cpu.dcache.demand_mshr_misses::total       780626                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       780626                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       780626                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24185998000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24185998000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4992658500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   4992658500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29178656500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29178656500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29178656500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29178656500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003157                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003157                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24738054000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24738054000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5071007000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5071007000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29809061000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29809061000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29809061000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29809061000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003175                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003175                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000702                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000702                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002411                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002411                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002411                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002411                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33987.476374                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33987.476374                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72345.836171                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72345.836171                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37378.535304                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37378.535304                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37378.535304                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37378.535304                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002421                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002421                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002421                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002421                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34763.255412                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34763.255412                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73481.140688                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73481.140688                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38186.098080                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38186.098080                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38186.098080                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38186.098080                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             10567                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1685.376446                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           316972597                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             12308                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          25753.379672                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse          1686.158478                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           285751480                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             12309                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          23214.841173                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1685.376446                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.822938                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.822938                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1741                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1686.158478                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.823320                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.823320                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1742                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           62                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1572                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.850098                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         633982120                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        633982120                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    316972597                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       316972597                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     316972597                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        316972597                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    316972597                       # number of overall hits
-system.cpu.icache.overall_hits::total       316972597                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        12309                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         12309                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        12309                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          12309                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        12309                       # number of overall misses
-system.cpu.icache.overall_misses::total         12309                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    349738000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    349738000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    349738000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    349738000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    349738000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    349738000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    316984906                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    316984906                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    316984906                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    316984906                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    316984906                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    316984906                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000039                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000039                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000039                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000039                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000039                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000039                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28413.193598                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 28413.193598                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 28413.193598                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 28413.193598                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 28413.193598                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 28413.193598                       # average overall miss latency
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1574                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.850586                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         571539889                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        571539889                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    285751480                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       285751480                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     285751480                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        285751480                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    285751480                       # number of overall hits
+system.cpu.icache.overall_hits::total       285751480                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12310                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12310                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12310                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12310                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12310                       # number of overall misses
+system.cpu.icache.overall_misses::total         12310                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    352350500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    352350500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    352350500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    352350500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    352350500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    352350500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    285763790                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    285763790                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    285763790                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    285763790                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    285763790                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    285763790                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000043                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000043                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000043                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000043                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28623.111292                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 28623.111292                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 28623.111292                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 28623.111292                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 28623.111292                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 28623.111292                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -513,133 +552,133 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        10567                       # number of writebacks
 system.cpu.icache.writebacks::total             10567                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12309                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        12309                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        12309                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        12309                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        12309                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        12309                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    337430000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    337430000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    337430000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    337430000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    337430000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    337430000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000039                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27413.274840                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27413.274840                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27413.274840                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 27413.274840                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27413.274840                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 27413.274840                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12310                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        12310                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        12310                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        12310                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        12310                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        12310                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    340041500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    340041500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    340041500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    340041500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    340041500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    340041500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000043                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000043                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000043                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000043                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27623.192526                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27623.192526                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27623.192526                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 27623.192526                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27623.192526                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 27623.192526                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           259935                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32594.451091                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1218218                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           292671                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.162414                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           259940                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32579.649991                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1218214                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           292676                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.162330                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2600.597713                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    77.726752                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29916.126627                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.079364                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002372                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.912968                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994704                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2630.640415                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    79.297977                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29869.711599                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.080281                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002420                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.911551                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994252                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32736                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          277                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          272                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2660                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29372                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          154                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          280                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          305                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2976                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29021                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999023                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13001938                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13001938                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks        88497                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        88497                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.tag_accesses         13001951                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13001951                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks        88489                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total        88489                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        10567                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total        10567                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         2366                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         2366                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         9419                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         9419                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       488887                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       488887                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         9419                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       491253                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          500672                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         9419                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       491253                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         500672                       # number of overall hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         9417                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         9417                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       488885                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       488885                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         9417                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       491251                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          500668                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         9417                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       491251                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         500668                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66645                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66645                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2890                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2890                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222728                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       222728                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2890                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       289373                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        292263                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2890                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       289373                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       292263                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4864271500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4864271500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    220068500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    220068500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17985247000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  17985247000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    220068500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  22849518500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  23069587000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    220068500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  22849518500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  23069587000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks        88497                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        88497                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2893                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2893                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222730                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       222730                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2893                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       289375                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        292268                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2893                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       289375                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       292268                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4942620000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4942620000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    222699500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    222699500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18537323500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  18537323500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    222699500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  23479943500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  23702643000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    222699500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  23479943500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  23702643000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        88489                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        88489                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks        10567                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total        10567                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69011                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69011                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        12309                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        12309                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        12310                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        12310                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       711615                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total       711615                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        12309                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        12310                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       780626                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       792935                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        12309                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       792936                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        12310                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       780626                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       792935                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       792936                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.965716                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.965716                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.234788                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.234788                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312989                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312989                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.234788                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.370694                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.368584                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.234788                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.370694                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.368584                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.793533                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.793533                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76148.269896                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76148.269896                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80749.824899                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80749.824899                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76148.269896                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78962.164749                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78934.339961                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76148.269896                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78962.164749                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78934.339961                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.235012                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.235012                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312992                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312992                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.235012                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.370696                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.368590                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.235012                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.370696                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.368590                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74163.403106                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74163.403106                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76978.741791                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76978.741791                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83227.780272                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83227.780272                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76978.741791                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81140.193521                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81099.001601                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76978.741791                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81140.193521                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81099.001601                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -654,117 +693,117 @@ system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1
 system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66645                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66645                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2890                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2890                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222728                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222728                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2890                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       289373                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       292263                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2890                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       289373                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       292263                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4197821500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4197821500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    191178500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    191178500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15757967000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15757967000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    191178500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19955788500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20146967000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    191178500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19955788500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20146967000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2893                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2893                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222730                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222730                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2893                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289375                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292268                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2893                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289375                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292268                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4276170000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4276170000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    193779500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    193779500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16310023500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16310023500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    193779500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20586193500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20779973000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    193779500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20586193500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20779973000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965716                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.965716                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.234788                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.234788                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312989                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312989                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.234788                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370694                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.368584                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.234788                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370694                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.368584                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62987.793533                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62987.793533                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66151.730104                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66151.730104                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70749.824899                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70749.824899                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66151.730104                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68962.164749                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68934.374177                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66151.730104                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68962.164749                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68934.374177                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.235012                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.235012                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312992                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312992                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.235012                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370696                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.368590                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.235012                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370696                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.368590                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64163.403106                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64163.403106                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66982.198410                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66982.198410                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73227.780272                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73227.780272                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66982.198410                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71140.193521                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71099.035816                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66982.198410                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71140.193521                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71099.035816                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1580032                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1580033                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       787097                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2079                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2079                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2081                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2081                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        723923                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       155180                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        723924                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       155172                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        10567                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       881285                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       881298                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69011                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69011                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        12309                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        12310                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq       711615                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35184                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        35186                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2337782                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2372966                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1464000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55623872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           57087872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259935                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1052870                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001975                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.044393                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count::total           2372968                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1464064                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55623360                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           57087424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259940                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1052876                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001976                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.044414                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1050791     99.80%     99.80% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2079      0.20%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1050795     99.80%     99.80% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2081      0.20%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1052870                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      889080000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1052876                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      889072500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      18462000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      18463500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy    1170939499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225617                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225622                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191173                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191176                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66645                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66645                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225617                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842380                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 842380                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22972480                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22972480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225622                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842393                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842393                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22972800                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22972800                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            550118                       # Request fanout histogram
+system.membus.snoop_fanout::samples            550126                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  550118    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  550126    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              550118                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           918693000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              550126                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           918516000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1556459000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1556053500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
index 72a187780..f6b6cbb05 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,80 +1,80 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.276414                       # Number of seconds simulated
-sim_ticks                                276414065500                       # Number of ticks simulated
-final_tick                               276414065500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.174766                       # Number of seconds simulated
+sim_ticks                                174766258500                       # Number of ticks simulated
+final_tick                               174766258500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168860                       # Simulator instruction rate (inst/s)
-host_op_rate                                   168860                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               55408638                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309496                       # Number of bytes of host memory used
-host_seconds                                  4988.65                       # Real time elapsed on the host
+host_inst_rate                                 293073                       # Simulator instruction rate (inst/s)
+host_op_rate                                   293073                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               60802944                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263360                       # Number of bytes of host memory used
+host_seconds                                  2874.31                       # Real time elapsed on the host
 sim_insts                                   842382029                       # Number of instructions simulated
 sim_ops                                     842382029                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            172736                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18523584                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18696320                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       172736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          172736                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4267712                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4267712                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2699                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             289431                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                292130                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66683                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66683                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               624918                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             67013898                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                67638816                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          624918                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             624918                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          15439562                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               15439562                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          15439562                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              624918                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            67013898                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               83078377                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        292130                       # Number of read requests accepted
-system.physmem.writeReqs                        66683                       # Number of write requests accepted
-system.physmem.readBursts                      292130                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66683                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18675136                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     21184                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4266432                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18696320                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4267712                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      331                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            174016                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18524608                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18698624                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       174016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          174016                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4267648                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4267648                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               2719                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             289447                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                292166                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66682                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66682                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               995707                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            105996479                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               106992186                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          995707                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             995707                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          24419176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               24419176                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          24419176                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              995707                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           105996479                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              131411362                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        292166                       # Number of read requests accepted
+system.physmem.writeReqs                        66682                       # Number of write requests accepted
+system.physmem.readBursts                      292166                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66682                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 18677824                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20800                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4265792                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18698624                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4267648                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      325                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0               18006                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18321                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18379                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18333                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18240                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18219                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18314                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               18303                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18232                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18223                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              18219                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18380                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18258                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18122                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              18052                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18198                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18334                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18382                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18340                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18235                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18233                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18311                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               18302                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18233                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18227                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              18220                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18388                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18256                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18125                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              18057                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18192                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4125                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4164                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4223                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4160                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                4142                       # Per bank write bursts
 system.physmem.perBankWrBursts::5                4099                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                4262                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                4261                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4226                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4233                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4187                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4150                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4180                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4148                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4241                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4100                       # Per bank write bursts
@@ -82,28 +82,28 @@ system.physmem.perBankWrBursts::14               4096                       # Pe
 system.physmem.perBankWrBursts::15               4157                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    276413976000                       # Total gap between requests
+system.physmem.totGap                    174766169000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  292130                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  292166                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66683                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    215201                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     47067                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     29332                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       170                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66682                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    215310                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     46521                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     29810                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       168                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        26                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         5                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
@@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      899                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     2144                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4147                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4146                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4064                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4099                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4062                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4054                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      897                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      900                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     2345                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4058                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4081                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4077                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4068                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5046                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4085                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4061                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4063                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4089                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4404                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4053                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
@@ -193,120 +193,124 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        99419                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      230.737062                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     148.797862                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     278.058381                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          34339     34.54%     34.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        42571     42.82%     77.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9880      9.94%     87.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511          767      0.77%     88.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         1066      1.07%     89.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          606      0.61%     89.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          182      0.18%     89.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1419      1.43%     91.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8589      8.64%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          99419                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4054                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        70.841638                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.476950                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      763.295063                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4046     99.80%     99.80% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        96628                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      237.414911                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     153.615169                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     282.362382                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          31544     32.64%     32.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        41851     43.31%     75.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        11279     11.67%     87.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511          407      0.42%     88.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          349      0.36%     88.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          422      0.44%     88.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          656      0.68%     89.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1511      1.56%     91.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8609      8.91%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          96628                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4053                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        68.731557                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.520071                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      729.773377                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4045     99.80%     99.80% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::13312-14335            1      0.02%     99.85% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14336-15359            3      0.07%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-16383            2      0.05%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::7168-8191            1      0.02%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::14336-15359            5      0.12%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::30720-31743            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4054                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4054                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.443759                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.423618                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.831866                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3155     77.82%     77.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  1      0.02%     77.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                896     22.10%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                  2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4054                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     3656274250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9127505500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1458995000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       12530.11                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4053                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4053                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.445349                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.425120                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.833815                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3151     77.74%     77.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  3      0.07%     77.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                896     22.11%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                  2      0.05%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4053                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3659606000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9131624750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1459205000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12539.73                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31280.11                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          67.56                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          15.43                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       67.64                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       15.44                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31289.73                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         106.87                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          24.41                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      106.99                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       24.42                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.65                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.53                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.12                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.37                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     207034                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     52000                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   70.95                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  77.98                       # Row buffer hit rate for writes
-system.physmem.avgGap                       770356.64                       # Average gap between requests
-system.physmem.pageHitRate                      72.26                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  374197320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  204175125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1139463000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216438480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            18053880000                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            80208829935                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            95488658250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             195685642110                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              707.948810                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   158328598000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      9230000000                       # Time in different power states
+system.physmem.busUtil                           1.03                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.83                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.19                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.04                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.34                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     209802                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     52054                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   71.89                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.06                       # Row buffer hit rate for writes
+system.physmem.avgGap                       487020.04                       # Average gap between requests
+system.physmem.pageHitRate                      73.04                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  364626360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  198952875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1139346000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                216432000                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            11414629200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            63677219400                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            49000374750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             126011580585                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              721.044153                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    81102514500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      5835700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    108853550750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     87824440500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  377342280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  205891125                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1136187000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                215537760                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            18053880000                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            80561309670                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            95179465500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             195729613335                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              708.107889                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   157816922000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      9230000000                       # Time in different power states
+system.physmem_1.actEnergy                  365752800                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  199567500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1136265000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                215479440                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            11414629200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            63630052470                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            49041749250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             126003495660                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              720.997890                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    81165303250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      5835700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    109365226750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     87762226750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               192576024                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         126054494                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          11561226                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            137875105                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               126274367                       # Number of BTB hits
+system.cpu.branchPred.lookups               129267026                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          83048450                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            145225                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             93510959                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                70602364                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             91.586053                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                28678385                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                133                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             75.501700                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19428078                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1137                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        14846480                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           14819636                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            26844                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         4929                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    242441427                       # DTB read hits
-system.cpu.dtb.read_misses                     312020                       # DTB read misses
-system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                242753447                       # DTB read accesses
-system.cpu.dtb.write_hits                   135445847                       # DTB write hits
-system.cpu.dtb.write_misses                     31631                       # DTB write misses
+system.cpu.dtb.read_hits                    243602185                       # DTB read hits
+system.cpu.dtb.read_misses                     267667                       # DTB read misses
+system.cpu.dtb.read_acv                             2                       # DTB read access violations
+system.cpu.dtb.read_accesses                243869852                       # DTB read accesses
+system.cpu.dtb.write_hits                   101634527                       # DTB write hits
+system.cpu.dtb.write_misses                     39608                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               135477478                       # DTB write accesses
-system.cpu.dtb.data_hits                    377887274                       # DTB hits
-system.cpu.dtb.data_misses                     343651                       # DTB misses
-system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                378230925                       # DTB accesses
-system.cpu.itb.fetch_hits                   194827904                       # ITB hits
-system.cpu.itb.fetch_misses                       239                       # ITB misses
+system.cpu.dtb.write_accesses               101674135                       # DTB write accesses
+system.cpu.dtb.data_hits                    345236712                       # DTB hits
+system.cpu.dtb.data_misses                     307275                       # DTB misses
+system.cpu.dtb.data_acv                             2                       # DTB access violations
+system.cpu.dtb.data_accesses                345543987                       # DTB accesses
+system.cpu.itb.fetch_hits                   116217608                       # ITB hits
+system.cpu.itb.fetch_misses                      1594                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               194828143                       # ITB accesses
+system.cpu.itb.fetch_accesses               116219202                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -320,236 +324,236 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   37                       # Number of system calls
-system.cpu.numCycles                        552828132                       # number of cpu cycles simulated
+system.cpu.numCycles                        349532518                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          198849781                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1637321417                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   192576024                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          154952752                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     341932468                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                23591048                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  137                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          6961                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           11                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 194827904                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               7885927                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          552584882                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.963022                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.176483                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          116536228                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      973715519                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   129267026                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          104850078                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     232359516                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  756618                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  832                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         13025                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           28                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 116217608                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                170932                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          349287938                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.787716                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.090069                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                236070631     42.72%     42.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 29638226      5.36%     48.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 21699661      3.93%     52.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 35773155      6.47%     58.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 67709217     12.25%     70.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 21596173      3.91%     74.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 19328814      3.50%     78.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3978253      0.72%     78.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                116790752     21.14%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                152570668     43.68%     43.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 21852908      6.26%     49.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 15618674      4.47%     54.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 24569577      7.03%     61.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 38589117     11.05%     72.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 15690770      4.49%     76.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 12536709      3.59%     80.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3990160      1.14%     81.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 63869355     18.29%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            552584882                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.348347                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.961719                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                166809048                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              90546856                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 271205722                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              12234440                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               11788816                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             15468258                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                  6932                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1567837184                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 24953                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               11788816                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                173694356                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                60697364                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          13758                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 276538556                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              29852032                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1529249378                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  8057                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2407484                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               20532473                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                7206116                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1021410389                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1760087391                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1720201095                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          39886295                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            349287938                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.369828                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.785765                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 85729217                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              85771889                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 158922951                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              18492364                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 371517                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11932000                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                  7014                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              968678626                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 25475                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 371517                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 93246352                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                12124008                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          14162                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 169252951                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              74278948                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              966798475                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                   812                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               25198716                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               40147884                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                7202949                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           666569389                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1151537527                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1114498375                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          37039151                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             638967158                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                382443231                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1367                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             87                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   9068503                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            369184759                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           173801249                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          40216404                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         11112363                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1296784829                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  74                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1011355981                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           8787623                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       454402873                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    422535596                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             37                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     552584882                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.830227                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.913668                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                 27602231                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1366                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             86                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  87958062                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            245057270                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           102624029                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          35348443                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          4751860                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  877942600                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  76                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 871652294                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             10599                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        35560646                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     10943510                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             39                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     349287938                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.495512                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.135180                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           197292642     35.70%     35.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            90775823     16.43%     52.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            90545836     16.39%     68.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            58767814     10.64%     79.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            57065281     10.33%     89.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            29635375      5.36%     94.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            16880319      3.05%     97.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             7509205      1.36%     99.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             4112587      0.74%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            75519507     21.62%     21.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            61352705     17.57%     39.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            57497159     16.46%     55.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            51075272     14.62%     70.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            45041028     12.90%     83.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            20641156      5.91%     89.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            18147367      5.20%     94.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            10284591      2.94%     97.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             9729153      2.79%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       552584882                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       349287938                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2519786     10.56%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               15987276     67.00%     77.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               5353537     22.44%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 3589516     19.40%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11788826     63.72%     83.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3123532     16.88%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              1276      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             577738940     57.13%     57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                 7929      0.00%     57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd            13232476      1.31%     58.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp             3826543      0.38%     58.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             3339799      0.33%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            274563490     27.15%     86.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           138645524     13.71%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             505111201     57.95%     57.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                 7850      0.00%     57.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     57.95% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd            13300877      1.53%     59.48% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp             3826560      0.44%     59.91% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             3339807      0.38%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  4      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     60.30% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            244259904     28.02%     88.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           101804815     11.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1011355981                       # Type of FU issued
-system.cpu.iq.rate                           1.829422                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    23860599                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023593                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2536933524                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1709848613                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    936642568                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            71011542                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           41384153                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     34526963                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              998751721                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                36463583                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         49725864                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              871652294                       # Type of FU issued
+system.cpu.iq.rate                           2.493766                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    18501874                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.021226                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2041816444                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         876761594                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    835992532                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            69288555                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           36778587                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     34169821                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              855051836                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                35101056                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         65597329                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    131674162                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses      1208593                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        45366                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     75500049                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      7546673                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5138                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        37094                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      4322829                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2715                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          4217                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2714                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4439                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               11788816                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                59730385                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                188341                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1470365584                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             17995                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             369184759                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            173801249                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 74                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  15707                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                184002                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          45366                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       11555966                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect        14467                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             11570433                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             973002254                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             242753622                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          38353727                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 371517                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 4003286                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                617757                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           966013425                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             16652                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             245057270                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            102624029                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 76                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 538427                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 92920                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          37094                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         128203                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect        15937                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               144140                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             871030251                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             243869972                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            622043                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     173580681                       # number of nop insts executed
-system.cpu.iew.exec_refs                    378231388                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                128483769                       # Number of branches executed
-system.cpu.iew.exec_stores                  135477766                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.760045                       # Inst execution rate
-system.cpu.iew.wb_sent                      971735602                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     971169531                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 554965093                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 830941176                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.756730                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.667875                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       534547076                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                      88070749                       # number of nop insts executed
+system.cpu.iew.exec_refs                    345544428                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                127159642                       # Number of branches executed
+system.cpu.iew.exec_stores                  101674456                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.491986                       # Inst execution rate
+system.cpu.iew.wb_sent                      870623887                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     870162353                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 525000957                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 821946847                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       2.489503                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.638729                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        31811556                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          11554519                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    481220935                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.929649                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.612057                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            138434                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    345159794                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.690312                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     3.060061                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    204061483     42.40%     42.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    101508829     21.09%     63.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     52351815     10.88%     74.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     25424424      5.28%     79.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     20903892      4.34%     84.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      8988981      1.87%     85.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     10032197      2.08%     87.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      6246270      1.30%     89.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     51703044     10.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    109423104     31.70%     31.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     81928646     23.74%     55.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     29947333      8.68%     64.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     19779535      5.73%     69.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     17819278      5.16%     75.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      7961935      2.31%     77.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      3040960      0.88%     78.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      3978860      1.15%     79.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     71280143     20.65%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    481220935                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    345159794                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            928587628                       # Number of instructions committed
 system.cpu.commit.committedOps              928587628                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -595,351 +599,341 @@ system.cpu.commit.op_class_0::MemWrite       98301200     10.59%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         928587628                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              51703044                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1890031457                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2997634424                       # The number of ROB writes
-system.cpu.timesIdled                            3187                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          243250                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              71280143                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1231657697                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1924928764                       # The number of ROB writes
+system.cpu.timesIdled                            3152                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          244580                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   842382029                       # Number of Instructions Simulated
 system.cpu.committedOps                     842382029                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.656268                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.656268                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.523768                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.523768                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1234256884                       # number of integer regfile reads
-system.cpu.int_regfile_writes               703449505                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  36844868                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 24462479                       # number of floating regfile writes
+system.cpu.cpi                               0.414933                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.414933                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               2.410025                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         2.410025                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1104176449                       # number of integer regfile reads
+system.cpu.int_regfile_writes               635594518                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  36406853                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 24680531                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            777152                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.896824                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           288563683                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            781248                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            369.362460                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         369982500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.896824                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999242                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999242                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            776668                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4091.068449                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           273851879                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            780764                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            350.748599                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         371412500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4091.068449                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998796                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998796                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          296                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          968                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         2491                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4          256                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          421                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1011                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         2512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4           62                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         582801420                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        582801420                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    191154367                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       191154367                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     97409302                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       97409302                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           14                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           14                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     288563669                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        288563669                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    288563669                       # number of overall hits
-system.cpu.dcache.overall_hits::total       288563669                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1554504                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1554504                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       891898                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       891898                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      2446402                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2446402                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2446402                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2446402                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  83607056000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  83607056000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  61973215333                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  61973215333                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        82500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        82500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145580271333                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145580271333                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145580271333                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145580271333                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    192708871                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    192708871                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses         553379090                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        553379090                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    176443243                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       176443243                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     97408623                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       97408623                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           13                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           13                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     273851866                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        273851866                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    273851866                       # number of overall hits
+system.cpu.dcache.overall_hits::total       273851866                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1554707                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1554707                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       892577                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       892577                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2447284                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2447284                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2447284                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2447284                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  83708553000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  83708553000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  61914869831                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  61914869831                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 145623422831                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 145623422831                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 145623422831                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 145623422831                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    177997950                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    177997950                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     98301200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     98301200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           15                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           15                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    291010071                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    291010071                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    291010071                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    291010071                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008067                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.008067                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009073                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.009073                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.066667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.066667                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008407                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008407                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008407                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008407                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53783.750959                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53783.750959                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69484.644357                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69484.644357                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        82500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        82500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59507.910529                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59507.910529                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59507.910529                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59507.910529                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        23437                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        62248                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               339                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             517                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    69.135693                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   120.402321                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           13                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    276299150                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    276299150                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    276299150                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    276299150                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008734                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.008734                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009080                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.009080                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008857                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008857                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008857                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008857                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53842.012032                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53842.012032                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69366.418618                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69366.418618                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59504.096309                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59504.096309                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59504.096309                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59504.096309                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        22333                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        68716                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               347                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             519                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    64.360231                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   132.400771                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88616                       # number of writebacks
-system.cpu.dcache.writebacks::total             88616                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       842060                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       842060                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       823094                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       823094                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1665154                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1665154                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1665154                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1665154                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712444                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712444                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68804                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        68804                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       781248                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       781248                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       781248                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       781248                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24228621500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24228621500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5666649497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5666649497                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29895270997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29895270997                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29895270997                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29895270997                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003697                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003697                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000700                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000700                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002685                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002685                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002685                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.002685                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34007.755697                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34007.755697                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82359.303195                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82359.303195                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38266.044837                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 38266.044837                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38266.044837                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 38266.044837                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks        88604                       # number of writebacks
+system.cpu.dcache.writebacks::total             88604                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       842561                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       842561                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       823959                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       823959                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1666520                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1666520                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1666520                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1666520                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712146                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712146                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        68618                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        68618                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       780764                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       780764                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       780764                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       780764                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24226479500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24226479500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5661245497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5661245497                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29887724997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29887724997                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29887724997                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29887724997                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004001                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.004001                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000698                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000698                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002826                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002826                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002826                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.002826                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34018.978552                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34018.978552                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82503.796336                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82503.796336                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38280.101282                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38280.101282                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38280.101282                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38280.101282                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              4602                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1641.296070                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           194819661                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6304                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          30904.134042                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              4617                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1647.904441                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           116209358                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              6322                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          18381.739639                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1641.296070                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801414                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801414                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1702                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           83                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1647.904441                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.804641                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.804641                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1705                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           79                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1535                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.831055                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         389662112                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        389662112                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    194819661                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       194819661                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     194819661                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        194819661                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    194819661                       # number of overall hits
-system.cpu.icache.overall_hits::total       194819661                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         8243                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          8243                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         8243                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           8243                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         8243                       # number of overall misses
-system.cpu.icache.overall_misses::total          8243                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    351192999                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    351192999                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    351192999                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    351192999                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    351192999                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    351192999                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    194827904                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    194827904                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    194827904                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    194827904                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    194827904                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    194827904                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000042                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000042                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000042                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000042                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000042                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000042                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42604.998059                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42604.998059                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42604.998059                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42604.998059                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42604.998059                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42604.998059                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          510                       # number of cycles access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1541                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.832520                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         232441538                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        232441538                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    116209358                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       116209358                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     116209358                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        116209358                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    116209358                       # number of overall hits
+system.cpu.icache.overall_hits::total       116209358                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8250                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          8250                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         8250                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           8250                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         8250                       # number of overall misses
+system.cpu.icache.overall_misses::total          8250                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    354158499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    354158499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    354158499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    354158499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    354158499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    354158499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    116217608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    116217608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    116217608                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    116217608                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    116217608                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    116217608                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000071                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000071                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000071                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000071                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000071                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000071                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42928.302909                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42928.302909                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42928.302909                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42928.302909                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42928.302909                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42928.302909                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          738                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                11                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    46.363636                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    61.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         4602                       # number of writebacks
-system.cpu.icache.writebacks::total              4602                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1938                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1938                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1938                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1938                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1938                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1938                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6305                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         6305                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         6305                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         6305                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         6305                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         6305                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    261344999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    261344999                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    261344999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    261344999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    261344999                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    261344999                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000032                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000032                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41450.436003                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41450.436003                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41450.436003                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41450.436003                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41450.436003                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41450.436003                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         4617                       # number of writebacks
+system.cpu.icache.writebacks::total              4617                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1927                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1927                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1927                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1927                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1927                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1927                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6323                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         6323                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         6323                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         6323                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         6323                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         6323                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    263974500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    263974500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    263974500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    263974500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    263974500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    263974500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000054                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000054                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000054                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000054                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000054                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000054                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41748.299858                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41748.299858                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41748.299858                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 41748.299858                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41748.299858                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 41748.299858                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           259749                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32631.179257                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1207901                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           292487                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.129760                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           259794                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32576.626048                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1207042                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           292532                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.126188                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2522.721637                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    62.286398                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 30046.171221                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.076987                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001901                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.916936                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.995825                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2634.083249                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    68.428877                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29874.113923                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.080386                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002088                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.911686                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.994160                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32738                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          199                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          269                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          532                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5300                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        26438                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          211                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          294                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          859                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8617                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        22757                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999084                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         12915747                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        12915747                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks        88616                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        88616                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         4602                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         4602                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         2178                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         2178                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3605                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         3605                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       489639                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       489639                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3605                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       491817                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          495422                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3605                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       491817                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         495422                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data        66626                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        66626                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2700                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2700                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222805                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       222805                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2700                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       289431                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        292131                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2700                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       289431                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       292131                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5540303500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   5540303500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    213942000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    213942000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18012503500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  18012503500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    213942000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  23552807000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  23766749000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    213942000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  23552807000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  23766749000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks        88616                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        88616                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         4602                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         4602                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data        68804                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total        68804                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6305                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         6305                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       712444                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       712444                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6305                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       781248                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       787553                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6305                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       781248                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       787553                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.968345                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.968345                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.428232                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.428232                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312733                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312733                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.428232                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.370473                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.370935                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.428232                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.370473                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.370935                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83155.277219                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83155.277219                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79237.777778                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79237.777778                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80844.251700                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80844.251700                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79237.777778                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81376.241660                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81356.477060                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79237.777778                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81376.241660                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81356.477060                       # average overall miss latency
+system.cpu.l2cache.tags.tag_accesses         12908126                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        12908126                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks        88604                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total        88604                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         4617                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         4617                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         1993                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         1993                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3603                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         3603                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       489324                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       489324                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3603                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       491317                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          494920                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3603                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       491317                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         494920                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66625                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66625                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2720                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2720                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222822                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       222822                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2720                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       289447                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        292167                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2720                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       289447                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       292167                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5537092500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5537092500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    216561000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    216561000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18014278000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  18014278000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    216561000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  23551370500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  23767931500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    216561000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  23551370500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  23767931500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        88604                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        88604                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         4617                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         4617                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        68618                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        68618                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6323                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         6323                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       712146                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       712146                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6323                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       780764                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       787087                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6323                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       780764                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       787087                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.970955                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.970955                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.430176                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.430176                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312888                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312888                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.430176                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.370723                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.371200                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.430176                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.370723                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.371200                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83108.330206                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83108.330206                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79618.014706                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79618.014706                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80846.047518                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80846.047518                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79618.014706                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81366.780447                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81350.499885                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79618.014706                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81366.780447                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81350.499885                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -948,123 +942,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66683                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66683                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            2                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total            2                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66626                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        66626                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2700                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2700                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222805                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222805                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2700                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       289431                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       292131                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2700                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       289431                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       292131                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4874043500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4874043500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    186952000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    186952000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15784453500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15784453500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    186952000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20658497000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20845449000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    186952000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20658497000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20845449000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks        66682                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66682                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66625                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66625                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2720                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2720                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222822                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222822                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2720                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       289447                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       292167                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2720                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       289447                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       292167                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4870842500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4870842500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    189371000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    189371000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15786058000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15786058000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    189371000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20656900500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20846271500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    189371000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20656900500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20846271500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.968345                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.968345                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.428232                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.428232                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312733                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312733                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.428232                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370473                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.370935                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.428232                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370473                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.370935                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73155.277219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73155.277219                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69241.481481                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69241.481481                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70844.251700                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70844.251700                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69241.481481                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71376.241660                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71356.511291                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69241.481481                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71376.241660                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71356.511291                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.970955                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.970955                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.430176                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.430176                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312888                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312888                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.430176                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.370723                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.371200                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.430176                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.370723                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.371200                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73108.330206                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73108.330206                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69621.691176                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69621.691176                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70846.047518                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70846.047518                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69621.691176                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71366.780447                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71350.534112                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69621.691176                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71366.780447                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71350.534112                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1569307                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       781754                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1568372                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       781285                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1989                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1989                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2003                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2003                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        718748                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       155299                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         4602                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       881602                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq        68804                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp        68804                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         6305                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       712444                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17211                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2339648                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2356859                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       697984                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55671296                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           56369280                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      259749                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1047302                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.001899                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.043538                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        718468                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       155286                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         4617                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       881176                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq        68618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp        68618                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         6323                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       712146                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        17262                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2338196                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2355458                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       700096                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55639552                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           56339648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      259794                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1046881                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.001913                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.043699                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1045313     99.81%     99.81% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1989      0.19%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1044878     99.81%     99.81% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2003      0.19%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1047302                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      877871500                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       9456000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1046881                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      877407000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          0.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy       9483000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1171872499                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225504                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        66683                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           191079                       # Transaction distribution
-system.membus.trans_dist::ReadExReq             66626                       # Transaction distribution
-system.membus.trans_dist::ReadExResp            66626                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225504                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842022                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 842022                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22964032                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22964032                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.respLayer1.occupancy    1171146499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          0.7                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp             225541                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66682                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           191110                       # Transaction distribution
+system.membus.trans_dist::ReadExReq             66625                       # Transaction distribution
+system.membus.trans_dist::ReadExResp            66625                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        225541                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       842124                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 842124                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22966272                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22966272                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            549892                       # Request fanout histogram
+system.membus.snoop_fanout::samples            549958                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  549892    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  549958    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              549892                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           880924000                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1551641250                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              0.6                       # Layer utilization (%)
+system.membus.snoop_fanout::total              549958                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           877671500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         1551270000                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
index 5f2d8e18a..35b8ed937 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
@@ -1,95 +1,95 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.542265                       # Number of seconds simulated
-sim_ticks                                542265386500                       # Number of ticks simulated
-final_tick                               542265386500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.489946                       # Number of seconds simulated
+sim_ticks                                489945697500                       # Number of ticks simulated
+final_tick                               489945697500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 173269                       # Simulator instruction rate (inst/s)
-host_op_rate                                   213317                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              146659072                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 328008                       # Number of bytes of host memory used
-host_seconds                                  3697.46                       # Real time elapsed on the host
+host_inst_rate                                 199747                       # Simulator instruction rate (inst/s)
+host_op_rate                                   245915                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              152758149                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280032                       # Number of bytes of host memory used
+host_seconds                                  3207.33                       # Real time elapsed on the host
 sim_insts                                   640655085                       # Number of instructions simulated
 sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            163584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          18474304                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             18637888                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       163584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          163584                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst            163712                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          18473856                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             18637568                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       163712                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          163712                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               2556                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             288661                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                291217                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               2558                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             288654                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                291212                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               301668                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             34068750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                34370418                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          301668                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             301668                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           7801110                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                7801110                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           7801110                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              301668                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            34068750                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               42171528                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        291217                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst               334143                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             37705926                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                38040069                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          334143                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             334143                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           8634165                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                8634165                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           8634165                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              334143                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            37705926                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               46674234                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        291212                       # Number of read requests accepted
 system.physmem.writeReqs                        66098                       # Number of write requests accepted
-system.physmem.readBursts                      291217                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                      291212                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 18617600                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     20288                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4228800                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  18637888                       # Total read bytes from the system interface side
+system.physmem.bytesReadDRAM                 18617024                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20544                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4228864                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  18637568                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      317                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                      321                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               18283                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               18129                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               18220                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               18184                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               18283                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               18405                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               18181                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               17993                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               18030                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               18058                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               18282                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               18130                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               18217                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               18178                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               18288                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               18411                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               18177                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               17990                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               18028                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               18056                       # Per bank write bursts
 system.physmem.perBankRdBursts::10              18107                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              18199                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              18220                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              18271                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              18202                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              18216                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              18274                       # Per bank write bursts
 system.physmem.perBankRdBursts::14              18077                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              18260                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              18258                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                4099                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4223                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4222                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               4095                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    542265292000                       # Total gap between requests
+system.physmem.totGap                    489945603000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  291217                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  291212                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    290512                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       374                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        14                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                    290509                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       369                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      894                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4016                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      903                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      903                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4014                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4019                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::30                     4019                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4018                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4018                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4017                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
@@ -193,95 +193,98 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       111115                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      205.591972                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     133.871353                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     256.553383                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          45879     41.29%     41.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        43676     39.31%     80.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         9414      8.47%     89.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1626      1.46%     90.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          693      0.62%     91.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          670      0.60%     91.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          515      0.46%     92.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          551      0.50%     92.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         8091      7.28%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         111115                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4018                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        48.511200                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       34.259636                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      506.474106                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           4016     99.95%     99.95% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples       110179                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      207.337369                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     135.107709                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     257.005441                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          44928     40.78%     40.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        43473     39.46%     80.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         9308      8.45%     88.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1919      1.74%     90.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          694      0.63%     91.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          753      0.68%     91.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          467      0.42%     92.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          575      0.52%     92.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         8062      7.32%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         110179                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4017                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        48.520538                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       34.272045                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      506.481387                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           4015     99.95%     99.95% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4018                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4018                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.444749                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.424614                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.831636                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3124     77.75%     77.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  1      0.02%     77.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                893     22.22%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4018                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     2873170250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8327545250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   1454500000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        9876.83                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            4017                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4017                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.449091                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.428808                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.834669                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3115     77.55%     77.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                902     22.45%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4017                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     3297540750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8751747000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   1454455000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       11336.00                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  28626.83                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          34.33                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           7.80                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       34.37                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        7.80                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30086.00                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          38.00                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                           8.63                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       38.04                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                        8.63                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           0.33                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       0.27                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.06                       # Data bus utilization in percentage for writes
+system.physmem.busUtil                           0.36                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       0.30                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.34                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     194203                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     51643                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   66.76                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  78.13                       # Row buffer hit rate for writes
-system.physmem.avgGap                      1517611.33                       # Average gap between requests
-system.physmem.pageHitRate                      68.86                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  420789600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  229597500                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                1136101200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                215537760                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            35417644080                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           107646010785                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           230928516000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             375994196925                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              693.386081                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   383467912500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     18107180000                       # Time in different power states
+system.physmem.avgWrQLen                        22.85                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     195161                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     51618                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   67.09                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  78.09                       # Row buffer hit rate for writes
+system.physmem.avgGap                      1371205.96                       # Average gap between requests
+system.physmem.pageHitRate                      69.13                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  417417840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  227757750                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                1136210400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                215563680                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            32000629440                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           104435392590                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           202355359500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             340788331200                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              695.568361                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   335944764000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     16360240000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    140682990000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    137638069000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  419141520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  228698250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1132419600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212628240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            35417644080                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           107856715275                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           230743687500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             376010934465                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              693.416947                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   383162755000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     18107180000                       # Time in different power states
+system.physmem_1.actEnergy                  415474920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  226697625                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1132396200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212608800                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            32000629440                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           104010891930                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           202727728500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             340726427415                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              695.442012                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   336564996750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     16360240000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    140991278500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    137017032000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               154805774                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         105138294                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          12875884                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             90693368                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                83089320                       # Number of BTB hits
+system.cpu.branchPred.lookups               144591747                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          96197702                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect             97552                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             81370677                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                61978792                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             91.615652                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                19277596                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               1316                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             76.168461                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                19276085                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               1317                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        15994685                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           15989167                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             5518                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         8032                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -400,99 +403,134 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                       1084530773                       # number of cpu cycles simulated
+system.cpu.numCycles                        979891395                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   640655085                       # Number of instructions committed
 system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      23906784                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       6653282                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.692847                       # CPI: cycles per instruction
-system.cpu.ipc                               0.590721                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1025899528                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        58631245                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            778339                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4092.484104                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           378456435                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            782435                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            483.690575                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         792553500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4092.484104                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999142                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999142                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.529515                       # CPI: cycles per instruction
+system.cpu.ipc                               0.653802                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               385757467     48.91%     48.91% # Class of committed instruction
+system.cpu.op_class_0::IntMult                5173441      0.66%     49.56% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     49.56% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd            637528      0.08%     49.65% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     49.65% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp           3187668      0.40%     50.05% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt           2550131      0.32%     50.37% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     50.37% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc         10203074      1.29%     51.67% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     51.67% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     51.67% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     51.67% # Class of committed instruction
+system.cpu.op_class_0::MemRead              252240938     31.98%     83.65% # Class of committed instruction
+system.cpu.op_class_0::MemWrite             128980497     16.35%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                788730744                       # Class of committed instruction
+system.cpu.tickCycles                       924243701                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        55647694                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            778302                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4092.104499                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           378448234                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            782398                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            483.702967                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         792959500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4092.104499                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999049                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999049                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          170                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          964                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3         1346                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1585                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          182                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          971                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3         1499                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1413                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         759398763                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        759398763                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    249627706                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       249627706                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    128813765                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      128813765                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data         3486                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total          3486                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses         759382252                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        759382252                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    249619506                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       249619506                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    128813766                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      128813766                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data         3484                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total          3484                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     378441471                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        378441471                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    378444957                       # number of overall hits
-system.cpu.dcache.overall_hits::total       378444957                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       713876                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        713876                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       137712                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       137712                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     378433272                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        378433272                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    378436756                       # number of overall hits
+system.cpu.dcache.overall_hits::total       378436756                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       713841                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        713841                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       137711                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       137711                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data          141                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total          141                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       851588                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         851588                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       851729                       # number of overall misses
-system.cpu.dcache.overall_misses::total        851729                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  24770851500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  24770851500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10105356000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10105356000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  34876207500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  34876207500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  34876207500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  34876207500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    250341582                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    250341582                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       851552                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         851552                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       851693                       # number of overall misses
+system.cpu.dcache.overall_misses::total        851693                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  25188260500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  25188260500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10109820000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10109820000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35298080500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35298080500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35298080500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35298080500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    250333347                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    250333347                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         3627                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         3627                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3625                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         3625                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    379293059                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    379293059                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    379296686                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    379296686                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    379284824                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    379284824                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    379288449                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    379288449                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002852                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.002852                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001068                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.001068                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038875                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.038875                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038897                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.038897                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.002245                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002246                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002246                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34699.095501                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34699.095501                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73380.359010                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73380.359010                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40954.320047                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40954.320047                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40947.540239                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40947.540239                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35285.533473                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 35285.533473                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73413.307579                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73413.307579                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41451.468025                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41451.468025                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41444.605627                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -501,109 +539,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        88693                       # number of writebacks
-system.cpu.dcache.writebacks::total             88693                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          902                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          902                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68390                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        68390                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        69292                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        69292                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        69292                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        69292                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712974                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       712974                       # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks        88712                       # number of writebacks
+system.cpu.dcache.writebacks::total             88712                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          904                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          904                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68389                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        68389                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        69293                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        69293                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        69293                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        69293                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712937                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       712937                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       782296                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       782296                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       782435                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       782435                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24041947500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  24041947500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5067670500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5067670500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       782259                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       782259                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       782398                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       782398                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24459771500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24459771500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5070040000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5070040000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1788000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1788000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29109618000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  29109618000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29111406000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  29111406000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29529811500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  29529811500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29531599500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  29531599500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038324                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038324                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.002063                       # mshr miss rate for demand accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038345                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038345                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33720.651104                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33720.651104                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73103.351029                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73103.351029                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34308.461337                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34308.461337                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37210.490658                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 37210.490658                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37206.165368                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 37206.165368                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             23591                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1713.095631                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           291576507                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             25342                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          11505.662813                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             24859                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1712.892625                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           252585994                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             26612                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           9491.432211                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1713.095631                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.836472                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.836472                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1751                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           93                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4         1600                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.854980                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         583229042                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        583229042                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    291576507                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       291576507                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     291576507                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        291576507                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    291576507                       # number of overall hits
-system.cpu.icache.overall_hits::total       291576507                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        25343                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         25343                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        25343                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          25343                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        25343                       # number of overall misses
-system.cpu.icache.overall_misses::total         25343                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    498728500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    498728500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    498728500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    498728500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    498728500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    498728500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    291601850                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    291601850                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    291601850                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    291601850                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    291601850                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    291601850                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000087                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000087                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000087                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000087                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000087                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000087                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19679.142169                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19679.142169                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19679.142169                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19679.142169                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19679.142169                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19679.142169                       # average overall miss latency
+system.cpu.icache.tags.occ_blocks::cpu.inst  1712.892625                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.836373                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.836373                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1753                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4         1599                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.855957                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         505251826                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        505251826                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    252585994                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       252585994                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     252585994                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        252585994                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    252585994                       # number of overall hits
+system.cpu.icache.overall_hits::total       252585994                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        26613                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         26613                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        26613                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          26613                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        26613                       # number of overall misses
+system.cpu.icache.overall_misses::total         26613                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    516729500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    516729500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    516729500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    516729500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    516729500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    516729500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    252612607                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    252612607                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    252612607                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    252612607                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    252612607                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    252612607                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000105                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000105                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000105                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000105                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000105                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000105                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19416.431819                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19416.431819                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19416.431819                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19416.431819                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19416.431819                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -612,135 +650,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        23591                       # number of writebacks
-system.cpu.icache.writebacks::total             23591                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        25343                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        25343                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        25343                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        25343                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        25343                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        25343                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    473386500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    473386500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    473386500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    473386500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    473386500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    473386500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000087                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000087                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18679.181628                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18679.181628                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18679.181628                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18679.181628                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18679.181628                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18679.181628                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        24859                       # number of writebacks
+system.cpu.icache.writebacks::total             24859                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        26613                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        26613                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        26613                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        26613                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        26613                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        26613                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    490117500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    490117500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    490117500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    490117500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    490117500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    490117500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000105                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000105                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000105                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000105                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000105                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000105                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           258813                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        32576.208282                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1245284                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           291557                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.271151                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           258808                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        32560.749490                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1247790                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           291552                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.279820                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  2603.470497                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    85.754116                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 29886.983669                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.079452                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002617                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.912078                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.994147                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  2632.544658                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    88.421700                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.783132                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.080339                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002698                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.910638                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.993675                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          126                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          199                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          288                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2812                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4        29319                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          326                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3136                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        28951                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         13211735                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        13211735                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks        88693                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        88693                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        22257                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        22257                       # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses         13231738                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        13231738                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks        88712                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total        88712                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        23528                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        23528                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         3231                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         3231                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        22781                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        22781                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490516                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       490516                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        22781                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       493747                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          516528                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        22781                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       493747                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         516528                       # number of overall hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        24049                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        24049                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490486                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       490486                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        24049                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       493717                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          517766                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        24049                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       493717                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         517766                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data        66091                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        66091                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2562                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         2562                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222597                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       222597                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         2562                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       288688                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        291250                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         2562                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       288688                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       291250                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4929759500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   4929759500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    194891500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    194891500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  17821559500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  17821559500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    194891500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  22751319000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  22946210500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    194891500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  22751319000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  22946210500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks        88693                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        88693                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        22257                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        22257                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2564                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         2564                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222590                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       222590                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2564                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       288681                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        291245                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2564                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       288681                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       291245                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4932129000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4932129000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    196405000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    196405000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18239788500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  18239788500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    196405000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  23171917500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  23368322500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    196405000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  23171917500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  23368322500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        88712                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        88712                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        23528                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        23528                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        69322                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        69322                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        25343                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        25343                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       713113                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       713113                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        25343                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       782435                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       807778                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        25343                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       782435                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       807778                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        26613                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        26613                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       713076                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       713076                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        26613                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       782398                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       809011                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        26613                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       782398                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       809011                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953391                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.953391                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.101093                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.101093                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312148                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312148                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.101093                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.368961                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.360557                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.101093                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.368961                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.360557                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74590.481306                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74590.481306                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76070.062451                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76070.062451                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80061.993198                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80061.993198                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76070.062451                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78809.368592                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78785.272103                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76070.062451                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78809.368592                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78785.272103                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.096344                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.096344                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312155                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312155                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.096344                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.368970                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.360001                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.096344                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.368970                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.360001                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.333389                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.333389                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76601.014041                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76601.014041                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81943.431870                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81943.431870                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76601.014041                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80268.245919                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 80235.961132                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76601.014041                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -763,115 +801,115 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data           27
 system.cpu.l2cache.overall_mshr_hits::total           32                       # number of overall MSHR hits
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66091                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        66091                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2557                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2557                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222570                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222570                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         2557                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       288661                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       291218                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         2557                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       288661                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       291218                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4268849500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4268849500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    169007000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    169007000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  15594098500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  15594098500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    169007000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  19862948000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  20031955000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    169007000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  19862948000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  20031955000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2559                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2559                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222563                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222563                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2559                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       288654                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       291213                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2559                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       288654                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       291213                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4271219000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4271219000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    170500500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    170500500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16012410500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16012410500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    170500500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20283629500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  20454130000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    170500500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20283629500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  20454130000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.100896                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.100896                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312110                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312110                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.100896                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368926                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.360517                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.100896                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368926                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.360517                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64590.481306                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64590.481306                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66095.815409                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66095.815409                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70063.793413                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70063.793413                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66095.815409                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68810.639470                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68786.802327                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66095.815409                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68810.639470                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68786.802327                       # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.096156                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096156                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312117                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312117                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.096156                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368935                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.359962                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.096156                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368935                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.359962                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1609708                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       801990                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3351                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         2028                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2013                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests      1612172                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       803221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3314                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         2027                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2012                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           15                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        738455                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       154791                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        23591                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       882361                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp        739688                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       154810                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        24859                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       882300                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        25343                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       713113                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        74276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2343209                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2417485                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3131712                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55752192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           58883904                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      258813                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1066591                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.005113                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.071523                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        26613                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       713076                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        78084                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2343098                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2421182                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3294144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55751040                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           59045184                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      258808                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1067819                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.005072                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.071235                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            1061152     99.49%     99.49% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               5424      0.51%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            1062418     99.49%     99.49% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               5386      0.50%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                 15      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1066591                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      917138000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1067819                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      919657000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      38015495                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      39920495                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    1173665973                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy    1173610473                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             225126                       # Transaction distribution
+system.membus.trans_dist::ReadResp             225121                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        66098                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           190686                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           190682                       # Transaction distribution
 system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
 system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        225126                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839218                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 839218                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22868160                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                22868160                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq        225121                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839204                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 839204                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22867840                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                22867840                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            548001                       # Request fanout histogram
+system.membus.snoop_fanout::samples            547992                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  548001    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  547992    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              548001                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           918049500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              547992                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           916865000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         1554665000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy         1554037500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index e148c082a..4c772ec0f 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -1,120 +1,120 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.452564                       # Number of seconds simulated
-sim_ticks                                452563515000                       # Number of ticks simulated
-final_tick                               452563515000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.326731                       # Number of seconds simulated
+sim_ticks                                326731324000                       # Number of ticks simulated
+final_tick                               326731324000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  57394                       # Simulator instruction rate (inst/s)
-host_op_rate                                    70660                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               40544083                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306292                       # Number of bytes of host memory used
-host_seconds                                 11162.26                       # Real time elapsed on the host
+host_inst_rate                                 133673                       # Simulator instruction rate (inst/s)
+host_op_rate                                   164569                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               68173047                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 277340                       # Number of bytes of host memory used
+host_seconds                                  4792.68                       # Real time elapsed on the host
 sim_insts                                   640649299                       # Number of instructions simulated
 sim_ops                                     788724958                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            234304                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          48000768                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     12823616                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             61058688                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       234304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          234304                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4243456                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           4243456                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3661                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             750012                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       200369                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                954042                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66304                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                66304                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               517726                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            106064158                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     28335506                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               134917389                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          517726                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             517726                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           9376487                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                9376487                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           9376487                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              517726                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           106064158                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     28335506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              144293877                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        954043                       # Number of read requests accepted
-system.physmem.writeReqs                        66304                       # Number of write requests accepted
-system.physmem.readBursts                      954043                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      66304                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 61040512                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     18240                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   4238400                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  61058752                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                4243456                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      285                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      53                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst            227072                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          47957824                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     12822400                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             61007296                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       227072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          227072                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4245376                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           4245376                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3548                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             749341                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       200350                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                953239                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66334                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                66334                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               694981                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            146780613                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     39244477                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               186720071                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          694981                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             694981                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          12993477                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               12993477                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          12993477                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              694981                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           146780613                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     39244477                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              199713548                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        953240                       # Number of read requests accepted
+system.physmem.writeReqs                        66334                       # Number of write requests accepted
+system.physmem.readBursts                      953240                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      66334                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 60987072                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     20288                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   4240192                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  61007360                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                4245376                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      317                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      64                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               19632                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               19241                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              656774                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               20103                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               19565                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               20788                       # Per bank write bursts
-system.physmem.perBankRdBursts::6               19429                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               19781                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               19292                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               19805                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              19337                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              19452                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              19407                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              20952                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              19359                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              20841                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                4254                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                4107                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               19685                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               19287                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              657567                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               20052                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               19480                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               20770                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               19386                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               19760                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               19321                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               19768                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              19303                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              19444                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              19433                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              20871                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              19269                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              19527                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                4288                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                4110                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                4140                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                4154                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                4243                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                4230                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                4242                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                4232                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                4174                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                4093                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                4095                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               4095                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               4098                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               4095                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               4155                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               4146                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    452563504500                       # Total gap between requests
+system.physmem.totGap                    326731313500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  954043                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  953240                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  66304                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    760089                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    121450                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     14329                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                      6788                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6461                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      7610                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      8751                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      9237                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      8035                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      3854                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     2788                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                     1992                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                     1474                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      900                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  66334                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    759877                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    120823                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     14314                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                      6736                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6450                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      7728                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      8758                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      9260                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      8005                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      3769                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     2825                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                     2023                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                     1473                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      882                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
@@ -148,47 +148,47 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      585                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      609                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                      994                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     1786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2649                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3332                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     3816                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     4180                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     4468                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     4679                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     4997                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5020                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     4895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     4192                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     4082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     4082                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      139                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      103                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       93                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      576                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      601                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1013                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     1770                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3363                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     3862                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     4189                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     4478                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     4705                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     4914                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5084                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5227                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5048                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     4894                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     4176                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     4054                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     4028                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      114                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       81                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       85                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       81                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                       77                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                       85                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                       74                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                       76                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45                       67                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46                       65                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47                       61                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49                       52                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50                       54                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51                       55                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52                       49                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53                       39                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54                       37                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55                       18                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       80                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       97                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                       86                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                       82                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                       75                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45                       72                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46                       71                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47                       64                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48                       66                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49                       58                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50                       65                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51                       53                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53                       44                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54                       42                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55                       19                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::56                        3                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
@@ -197,112 +197,117 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples       205577                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      317.529062                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     201.622998                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     287.021434                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          59787     29.08%     29.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        62582     30.44%     59.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        15931      7.75%     67.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3214      1.56%     68.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         3392      1.65%     70.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        47997     23.35%     93.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7735      3.76%     97.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1172      0.57%     98.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         3767      1.83%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total         205577                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          4029                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean       209.250931                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean       40.553257                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev     2756.803776                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-4095           4005     99.40%     99.40% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4096-8191           12      0.30%     99.70% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-12287            3      0.07%     99.78% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::12288-16383            4      0.10%     99.88% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::24576-28671            2      0.05%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::61440-65535            1      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::94208-98303            1      0.02%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::114688-118783            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            4029                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          4029                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.437081                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.396271                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.276876                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               3401     84.41%     84.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  9      0.22%     84.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                462     11.47%     96.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                 50      1.24%     97.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 36      0.89%     98.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 16      0.40%     98.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 18      0.45%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 10      0.25%     99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  6      0.15%     99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  6      0.15%     99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  4      0.10%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  4      0.10%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  3      0.07%     99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29                  2      0.05%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  2      0.05%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            4029                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    15078460254                       # Total ticks spent queuing
-system.physmem.totMemAccLat               32961422754                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   4768790000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       15809.52                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples       187141                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      348.533437                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     199.264052                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     368.938471                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          57976     30.98%     30.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        60329     32.24%     63.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        15964      8.53%     71.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2811      1.50%     73.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2834      1.51%     74.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2850      1.52%     76.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2680      1.43%     77.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023        20043     10.71%     88.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        21654     11.57%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total         187141                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          4039                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean       232.424858                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::gmean       40.579593                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev     3031.486386                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095           4013     99.36%     99.36% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4096-8191           12      0.30%     99.65% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8192-12287            1      0.02%     99.68% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-16383            4      0.10%     99.78% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::16384-20479            4      0.10%     99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::24576-28671            1      0.02%     99.90% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::53248-57343            1      0.02%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::57344-61439            1      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::106496-110591            1      0.02%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::118784-122879            1      0.02%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total            4039                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          4039                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.403318                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.369585                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.145225                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               3419     84.65%     84.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 15      0.37%     85.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                455     11.27%     96.29% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                 68      1.68%     97.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 26      0.64%     98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 15      0.37%     98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 15      0.37%     99.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  7      0.17%     99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  9      0.22%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  4      0.10%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  3      0.07%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.02%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            4039                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    12733277648                       # Total ticks spent queuing
+system.physmem.totMemAccLat               30600583898                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   4764615000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13362.34                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  34559.52                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         134.88                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                           9.37                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      134.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                        9.38                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32112.34                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         186.66                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          12.98                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      186.72                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       12.99                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.13                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       1.05                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.08                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.40                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     788510                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     25885                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   82.67                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.07                       # Row buffer hit rate for writes
-system.physmem.avgGap                       443538.82                       # Average gap between requests
-system.physmem.pageHitRate                      79.84                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 1031660280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  562909875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                6203308800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                216399600                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            29559032880                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           305467849845                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             3582027000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             346623188280                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              765.915744                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE     4235605578                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     15111980000                       # Time in different power states
+system.physmem.busUtil                           1.56                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      0.10                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.09                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        25.20                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     805882                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     26140                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   84.57                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  39.44                       # Row buffer hit rate for writes
+system.physmem.avgGap                       320458.66                       # Average gap between requests
+system.physmem.pageHitRate                      81.64                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  905544360                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  494096625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                6208534800                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                216665280                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            21340194720                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           220053154905                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             3007065000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             252225255690                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              771.975754                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE     3732596290                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     10910120000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    433212896922                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    312084210210                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  522411120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  285045750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                1235535600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                212738400                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            29559032880                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            96975747585                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           186469836000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             315260347335                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              696.614859                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   309568131397                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     15111980000                       # Time in different power states
+system.physmem_1.actEnergy                  509143320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  277806375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                1223765400                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                212654160                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            21340194720                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            86358123315                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           120283389750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             230205077040                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              704.579541                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   199538723813                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     10910120000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    127880371103                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    116279470187                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               234612924                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         162473080                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15514448                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            121580360                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               107626063                       # Number of BTB hits
+system.cpu.branchPred.lookups               174663372                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         119116658                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           4015834                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             96720842                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                67756635                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             88.522573                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                25035646                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect            1300027                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             70.053810                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18785000                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect            1299597                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        16716087                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits           16701520                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            14567                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted      1279491                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -421,232 +426,232 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  673                       # Number of system calls
-system.cpu.numCycles                        905127031                       # number of cpu cycles simulated
+system.cpu.numCycles                        653462649                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           85998683                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1202051079                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   234612924                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          132661709                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     803240111                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                31064493                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 1917                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            31                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles         3269                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 370084311                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                652880                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          904776257                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.657297                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.229901                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           34330546                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      824287133                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   174663372                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          103243155                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     614749504                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 8068361                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2074                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            17                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles         3172                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 247743048                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 12728                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          653119493                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.556506                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.252668                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                222804793     24.63%     24.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                224059137     24.76%     49.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 98313262     10.87%     60.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                359599065     39.74%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                191049151     29.25%     29.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                148339787     22.71%     51.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 72947000     11.17%     63.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                240783555     36.87%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            904776257                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.259204                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.328047                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                121900634                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             244061321                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 484657119                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              38638613                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               15518570                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             24546046                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 13813                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             1248144936                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              39968729                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               15518570                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                178911503                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               163289745                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         206869                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 464319515                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              82530055                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1190655236                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              24276259                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              24947259                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2269584                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents               41529012                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                1706231                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1226042317                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            5813738555                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1358185798                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          40876436                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            653119493                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.267289                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.261414                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 75090408                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             234264663                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 277765642                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              61977614                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4021166                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             20809487                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 13114                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              924578192                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              11804661                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4021166                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                118033326                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               133536652                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         207511                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 294559211                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             102761627                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              906540244                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts               6891569                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              27986936                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2218724                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents               49336465                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 494906                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           980929615                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4376071754                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1001832293                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          34457071                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             874778230                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                351264087                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               7264                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           7257                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 108789745                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            367388846                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           236095095                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1811043                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          5312656                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1169837126                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               12332                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1017086167                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          18990404                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       381124500                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1038523748                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            178                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     904776257                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.124130                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.093860                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                106151385                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               6850                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           6837                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 138811891                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            271881167                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           160584857                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           6164108                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         12154940                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  899826382                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               12579                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 860025252                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           9216952                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       111114003                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    248251839                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            425                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     653119493                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.316796                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.093773                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           347117204     38.36%     38.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           227104713     25.10%     63.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           217802755     24.07%     87.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            96630403     10.68%     98.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            16121175      1.78%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                   7      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           190460700     29.16%     29.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           182404327     27.93%     57.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           175564310     26.88%     83.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            92270630     14.13%     98.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12417215      1.90%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                2311      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       904776257                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       653119493                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                63882217     18.87%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                  18143      0.01%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt            636889      0.19%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              158029640     46.67%     65.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite             116058922     34.27%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                66606660     24.62%     24.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                  18142      0.01%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     24.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt            636889      0.24%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     24.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              134118538     49.58%     74.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              69109914     25.55%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             456367665     44.87%     44.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult              5195678      0.51%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     45.38% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.06%     45.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     45.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp         3187675      0.31%     45.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt         2550147      0.25%     46.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     46.01% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc       11478996      1.13%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.14% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            322074351     31.67%     78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           215594127     21.20%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             413086253     48.03%     48.03% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult              5187655      0.60%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     48.64% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd          637528      0.07%     48.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     48.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp         3187674      0.37%     49.08% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt         2550149      0.30%     49.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     49.38% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc       11478193      1.33%     50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     50.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            266665790     31.01%     81.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           157232010     18.28%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1017086167                       # Type of FU issued
-system.cpu.iq.rate                           1.123694                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   338625811                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.332937                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3234688378                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1507427240                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    934273902                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            61876428                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes           43565689                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses     26152450                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1321902233                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                33809745                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          9959480                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              860025252                       # Type of FU issued
+system.cpu.iq.rate                           1.316105                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   270490143                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.314514                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         2595335329                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         980330228                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    820077465                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            57541763                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           30641547                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses     24878664                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1098495276                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                32020119                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         13987051                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    115147908                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         1093                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        18974                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    107114599                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     19640229                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses          121                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        18814                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     31604361                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      2065775                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         19869                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      1918936                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         18556                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               15518570                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                35329075                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 27772                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1169855013                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                4021166                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                10589336                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 14351                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           899849213                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             367388846                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            236095095                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               6592                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     88                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 30218                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          18974                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       15437101                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3784620                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19221721                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             974751329                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             303296690                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          42334838                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             271881167                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            160584857                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               6839                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                    943                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 11501                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          18814                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3295227                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3290376                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              6585603                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             850170088                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             263374256                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           9855164                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          5555                       # number of nop insts executed
-system.cpu.iew.exec_refs                    497768330                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                150610966                       # Number of branches executed
-system.cpu.iew.exec_stores                  194471640                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.076922                       # Inst execution rate
-system.cpu.iew.wb_sent                      963724922                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     960426352                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 536046741                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 893290325                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.061096                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.600081                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       357426439                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         10252                       # number of nop insts executed
+system.cpu.iew.exec_refs                    416063199                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                143379422                       # Number of branches executed
+system.cpu.iew.exec_stores                  152688943                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.301023                       # Inst execution rate
+system.cpu.iew.wb_sent                      846292107                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     844956129                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 487338276                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 808096579                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.293044                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.603069                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       103168329                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           12154                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15500772                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    853952830                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.923623                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.715196                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           4002820                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    638538795                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.235211                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.072799                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    515313788     60.34%     60.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    174402011     20.42%     80.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     72937800      8.54%     89.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     32899590      3.85%     93.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      8538808      1.00%     94.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     14259214      1.67%     95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      7267758      0.85%     96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      5975049      0.70%     97.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     22358812      2.62%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    348204518     54.53%     54.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    137237104     21.49%     76.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     51340026      8.04%     84.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     28219441      4.42%     88.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     14379877      2.25%     90.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     14774087      2.31%     93.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      7871873      1.23%     94.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      6561542      1.03%     95.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     29950327      4.69%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    853952830                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    638538795                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            640654411                       # Number of instructions committed
 system.cpu.commit.committedOps              788730070                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -692,387 +697,387 @@ system.cpu.commit.op_class_0::MemWrite      128980496     16.35%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         788730070                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              22358812                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   1977741776                       # The number of ROB reads
-system.cpu.rob.rob_writes                  2343140199                       # The number of ROB writes
-system.cpu.timesIdled                          648615                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          350774                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              29950327                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   1500478116                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1798380886                       # The number of ROB writes
+system.cpu.timesIdled                            9234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          343156                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   640649299                       # Number of Instructions Simulated
 system.cpu.committedOps                     788724958                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.412828                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.412828                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.707800                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.707800                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                995808121                       # number of integer regfile reads
-system.cpu.int_regfile_writes               567906123                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  31889839                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 22959494                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                3794435958                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                384896498                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               715821566                       # number of misc regfile reads
+system.cpu.cpi                               1.020001                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.020001                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.980392                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.980392                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                868460109                       # number of integer regfile reads
+system.cpu.int_regfile_writes               500697086                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  30616061                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 22959483                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                3322370942                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                369203387                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               632347857                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                6386808                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           2756183                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.937153                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           414216547                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           2756695                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            150.258388                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         267553000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.937153                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.999877                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.999877                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2756452                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.912722                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           371048240                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2756964                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            134.585813                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         268220000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.912722                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999830                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999830                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          218                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          198                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          252                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          164                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         839347867                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        839347867                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    286293756                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       286293756                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    127906808                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      127906808                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         751744798                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        751744798                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    243125245                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       243125245                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    127906950                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      127906950                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data         3157                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total          3157                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data         5737                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total         5737                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         5738                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         5738                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     414200564                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414200564                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    414203721                       # number of overall hits
-system.cpu.dcache.overall_hits::total       414203721                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      3035071                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       3035071                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1044669                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1044669                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data          646                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total          646                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data     371032195                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        371032195                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    371035352                       # number of overall hits
+system.cpu.dcache.overall_hits::total       371035352                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2401911                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2401911                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1044527                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1044527                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          647                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          647                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      4079740                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        4079740                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      4080386                       # number of overall misses
-system.cpu.dcache.overall_misses::total       4080386                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  76845731000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  76845731000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10002174850                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10002174850                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       187500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total       187500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  86847905850                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  86847905850                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  86847905850                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  86847905850                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    289328827                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    289328827                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      3446438                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3446438                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3447085                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3447085                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  68215511500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  68215511500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10001211350                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10001211350                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       165500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       165500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  78216722850                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  78216722850                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  78216722850                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  78216722850                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    245527156                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    245527156                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data         3803                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total         3803                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5740                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total         5740                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data         3804                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total         3804                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5741                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         5741                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    418280304                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    418280304                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    418284107                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    418284107                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010490                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.010490                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008101                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.008101                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.169866                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.169866                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    374478633                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    374478633                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    374482437                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    374482437                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009783                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.009783                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.008100                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.008100                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.170084                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.170084                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000523                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.000523                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.009754                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.009754                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.009755                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.009755                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25319.253158                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25319.253158                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9574.491873                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  9574.491873                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        62500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        62500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 21287.607997                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 21287.607997                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21284.237778                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21284.237778                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.009203                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.009203                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.009205                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.009205                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28400.515881                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28400.515881                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  9574.871066                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  9574.871066                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 55166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 55166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22694.945579                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22694.945579                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22690.685855                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22690.685855                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets       351058                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets       351776                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets            4882                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets            4812                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    71.908644                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    73.103907                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2756183                       # number of writebacks
-system.cpu.dcache.writebacks::total           2756183                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       999866                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       999866                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       323646                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       323646                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      2756452                       # number of writebacks
+system.cpu.dcache.writebacks::total           2756452                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       366436                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       366436                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       323495                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       323495                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1323512                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1323512                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1323512                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1323512                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035205                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      2035205                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       721023                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       721023                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          641                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total          641                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2756228                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2756228                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2756869                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2756869                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  65547149000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  65547149000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5956550350                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5956550350                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5499000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5499000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  71503699350                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  71503699350                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  71509198350                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  71509198350                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.007034                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.007034                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data       689931                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       689931                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       689931                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       689931                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      2035475                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      2035475                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       721032                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       721032                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          642                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          642                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2756507                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2756507                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2757149                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2757149                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  63009195000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  63009195000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5955069850                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5955069850                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      5660000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      5660000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  68964264850                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  68964264850                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  68969924850                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  68969924850                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.008290                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.008290                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005591                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005591                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168551                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168551                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006589                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006589                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006591                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006591                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32206.656823                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32206.656823                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8261.248740                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8261.248740                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8578.783151                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8578.783151                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25942.592322                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25942.592322                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25938.555060                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25938.555060                       # average overall mshr miss latency
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.168770                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.168770                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.007361                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.007361                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.007363                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.007363                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30955.523895                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30955.523895                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  8259.092315                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  8259.092315                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8816.199377                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8816.199377                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25018.715661                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 25018.715661                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25014.942917                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 25014.942917                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements           5169029                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.720775                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           364910405                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs           5169539                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             70.588578                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle         257528500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.720775                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997502                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997502                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements           1979880                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.626245                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           245759391                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs           1980390                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            124.096461                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle         258109500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.626245                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997317                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997317                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          510                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           60                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          121                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          327                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           61                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          113                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          333                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.996094                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         745338281                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        745338281                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    364910416                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       364910416                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     364910416                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        364910416                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    364910416                       # number of overall hits
-system.cpu.icache.overall_hits::total       364910416                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      5173868                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       5173868                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      5173868                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        5173868                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      5173868                       # number of overall misses
-system.cpu.icache.overall_misses::total       5173868                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  41967552420                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  41967552420                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  41967552420                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  41967552420                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  41967552420                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  41967552420                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    370084284                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    370084284                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    370084284                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    370084284                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    370084284                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    370084284                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013980                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013980                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013980                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013980                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013980                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013980                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8111.446295                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  8111.446295                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  8111.446295                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  8111.446295                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  8111.446295                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  8111.446295                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        79493                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          135                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              3635                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         497466609                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        497466609                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    245759426                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       245759426                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     245759426                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        245759426                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    245759426                       # number of overall hits
+system.cpu.icache.overall_hits::total       245759426                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1983591                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1983591                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1983591                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1983591                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1983591                       # number of overall misses
+system.cpu.icache.overall_misses::total       1983591                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16128682925                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16128682925                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16128682925                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16128682925                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16128682925                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16128682925                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    247743017                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    247743017                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    247743017                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    247743017                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    247743017                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    247743017                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.008007                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.008007                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.008007                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.008007                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.008007                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.008007                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8131.052684                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  8131.052684                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8131.052684                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  8131.052684                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8131.052684                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  8131.052684                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        75472                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           75                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              2912                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.868776                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           27                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    25.917582                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets           15                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks      5169029                       # number of writebacks
-system.cpu.icache.writebacks::total           5169029                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4153                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         4153                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         4153                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         4153                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         4153                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         4153                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      5169715                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      5169715                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      5169715                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      5169715                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      5169715                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      5169715                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  39342077434                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  39342077434                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  39342077434                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  39342077434                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  39342077434                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  39342077434                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013969                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013969                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013969                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013969                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013969                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013969                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7610.105670                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7610.105670                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7610.105670                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  7610.105670                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7610.105670                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  7610.105670                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks      1979880                       # number of writebacks
+system.cpu.icache.writebacks::total           1979880                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3014                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3014                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3014                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3014                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3014                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3014                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1980577                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1980577                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1980577                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1980577                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1980577                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1980577                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  15098139938                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  15098139938                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  15098139938                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  15098139938                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  15098139938                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  15098139938                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.007994                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.007994                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.007994                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.007994                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.007994                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.007994                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  7623.101721                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  7623.101721                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  7623.101721                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  7623.101721                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  7623.101721                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  7623.101721                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued      1350427                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified      1355108                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         4095                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued      1350865                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified      1355053                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         3664                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4790132                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           301513                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16356.090183                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           13598662                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           317875                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            42.779904                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      60356537500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  9848.276079                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6507.814104                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.601091                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.397205                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.998297                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022         6290                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        10072                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           16                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2          146                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1301                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4827                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          135                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          205                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         1956                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         7712                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.383911                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.614746                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        244370866                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       244370866                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       735261                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       735261                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks      6545775                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total      6545775                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       718468                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       718468                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      5165879                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total      5165879                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1286323                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      1286323                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst      5165879                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2004791                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7170670                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst      5165879                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2004791                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7170670                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          174                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          174                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         2381                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         2381                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3663                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3663                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data       749523                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total       749523                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3663                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       751904                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        755567                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3663                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       751904                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       755567                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    195784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    195784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    268224500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    268224500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  54132437000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total  54132437000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    268224500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  54328221000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  54596445500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    268224500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  54328221000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  54596445500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       735261                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       735261                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks      6545775                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total      6545775                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          174                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          174                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       720849                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       720849                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      5169542                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total      5169542                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2035846                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      2035846                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst      5169542                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2756695                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      7926237                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst      5169542                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2756695                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      7926237                       # number of overall (read+write) accesses
+system.cpu.l2cache.prefetcher.pfSpanPage      4790051                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           301370                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16350.432681                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            7222107                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           317734                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            22.730041                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      44242160500                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks  9843.702780                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  6506.729901                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.600812                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.397139                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.997951                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022         6334                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        10030                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           17                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2          193                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3         1704                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4         4420                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          146                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          303                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         2583                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         6932                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.386597                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.612183                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        142338236                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       142338236                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       736314                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       736314                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks      3356496                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total      3356496                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       718501                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       718501                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst      1976843                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total      1976843                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      1287256                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      1287256                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst      1976843                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2005757                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         3982600                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst      1976843                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2005757                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        3982600                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          185                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          185                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         2346                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2346                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3550                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3550                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data       748861                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total       748861                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3550                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       751207                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        754757                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3550                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       751207                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       754757                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    195074000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    195074000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    261372000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    261372000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  51585571000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total  51585571000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    261372000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  51780645000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  52042017000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    261372000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  51780645000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  52042017000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       736314                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       736314                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks      3356496                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total      3356496                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          185                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          185                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       720847                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       720847                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst      1980393                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total      1980393                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      2036117                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      2036117                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst      1980393                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2756964                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      4737357                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst      1980393                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2756964                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      4737357                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003303                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.003303                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.000709                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.000709                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.368163                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.368163                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.000709                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.272756                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.095325                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.000709                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.272756                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.095325                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82227.635447                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82227.635447                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73225.361725                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73225.361725                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 72222.516187                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 72222.516187                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73225.361725                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72254.198674                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 72258.906887                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73225.361725                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72254.198674                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 72258.906887                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.003255                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.003255                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.001793                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.001793                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.367789                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.367789                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.001793                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.272476                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.159320                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.001793                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.272476                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.159320                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83151.747656                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83151.747656                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73625.915493                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73625.915493                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 68885.375257                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 68885.375257                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73625.915493                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68929.928768                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 68952.016344                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73625.915493                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68929.928768                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 68952.016344                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1081,155 +1086,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        66304                       # number of writebacks
-system.cpu.l2cache.writebacks::total            66304                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         1019                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         1019                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.unused_prefetches             2695                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks        66334                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66334                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data          963                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total          963                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          873                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total          873                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          903                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total          903                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         1892                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         1893                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         1866                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         1867                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         1892                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         1893                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       200459                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       200459                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          174                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          174                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1362                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1362                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3662                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3662                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       748650                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total       748650                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3662                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       750012                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       753674                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3662                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       750012                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       200459                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       954133                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  16513318471                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  16513318471                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2453000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2453000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    133666500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    133666500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    246204000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    246204000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  49598643500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  49598643500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    246204000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  49732310000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  49978514000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    246204000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  49732310000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  16513318471                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  66491832471                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data         1866                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         1867                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       200438                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       200438                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          185                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          185                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1383                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1383                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3549                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3549                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       747958                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total       747958                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3549                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       749341                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       752890                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3549                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       749341                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       200438                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       953328                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  16667426112                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  16667426112                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      2605000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      2605000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    137246500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    137246500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    240029500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    240029500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  47054888500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  47054888500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    240029500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  47192135000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  47432164500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    240029500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  47192135000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  16667426112                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  64099590612                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001889                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001889                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.000708                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.000708                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.367734                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.367734                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.000708                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.272069                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.095086                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.000708                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.272069                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.001919                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.001919                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.001792                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.001792                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.367345                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.367345                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.001792                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.271799                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.158926                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.001792                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.271799                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.120377                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82377.535910                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14097.701149                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14097.701149                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 98139.867841                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 98139.867841                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67232.113599                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67232.113599                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66250.776064                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66250.776064                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67232.113599                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66308.685728                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66313.172539                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67232.113599                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66308.685728                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69688.222157                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.201236                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 83155.021064                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14081.081081                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14081.081081                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99238.250181                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99238.250181                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67632.995210                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67632.995210                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62911.137390                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62911.137390                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67632.995210                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62978.183497                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63000.125516                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67632.995210                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62978.183497                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 83155.021064                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67237.708965                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     15851796                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      7925416                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests       644350                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops       760180                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops       116881                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops       643299                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7205559                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       801565                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean      7189951                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict       987519                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       243847                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          174                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          174                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       720849                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       720849                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq      5169715                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      2035846                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     15508284                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8269921                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          23778205                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    661668416                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    352824192                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         1014492608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1297843                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      9224254                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.222027                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.558758                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests      9474058                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      4736544                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests       643707                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops       759527                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops       116739                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops       642788                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp       4016692                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       802648                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean      4000018                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict       986541                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       243725                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       720847                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       720847                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq      1980577                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      2036117                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5940848                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      8270750                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          14211598                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    253457344                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    352858624                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          606315968                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1296784                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      6034326                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.339099                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.661177                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0            7819520     84.77%     84.77% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             761435      8.25%     93.03% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2             643299      6.97%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0            4630880     76.74%     76.74% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             760658     12.61%     89.35% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2             642788     10.65%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        9224254                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    15851110000                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization          3.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy    7754813511                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy    4135160937                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization          0.9                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             952680                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        66304                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           227429                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              174                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1362                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1362                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        952681                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2201992                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                2201992                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     65302144                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                65302144                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoop_fanout::total        6034326                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     9473361000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization          2.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy    2970865494                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          0.9                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy    4135548979                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization          1.3                       # Layer utilization (%)
+system.membus.trans_dist::ReadResp             951856                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        66334                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           227102                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              185                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1383                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1383                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        951857                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      2200100                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                2200100                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     65252672                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                65252672                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           1247950                       # Request fanout histogram
+system.membus.snoop_fanout::samples           1246861                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 1247950    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 1246861    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             1247950                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          1752348040                       # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization               0.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy         5020538027                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              1.1                       # Layer utilization (%)
+system.membus.snoop_fanout::total             1246861                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          1754485252                       # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization               0.5                       # Layer utilization (%)
+system.membus.respLayer1.occupancy         5014122383                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
index 2126b1202..7a3a9c70d 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,105 +1,105 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.059474                       # Number of seconds simulated
-sim_ticks                                 59473862000                       # Number of ticks simulated
-final_tick                                59473862000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.059447                       # Number of seconds simulated
+sim_ticks                                 59447065000                       # Number of ticks simulated
+final_tick                                59447065000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 330532                       # Simulator instruction rate (inst/s)
-host_op_rate                                   330532                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              222279677                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308876                       # Number of bytes of host memory used
-host_seconds                                   267.56                       # Real time elapsed on the host
+host_inst_rate                                 412945                       # Simulator instruction rate (inst/s)
+host_op_rate                                   412945                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              277576735                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 261724                       # Number of bytes of host memory used
+host_seconds                                   214.16                       # Real time elapsed on the host
 sim_insts                                    88438073                       # Number of instructions simulated
 sim_ops                                      88438073                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            432448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10149376                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             10581824                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       432448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          432448                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7325760                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7325760                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6757                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             158584                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                165341                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114465                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114465                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              7271228                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            170652715                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               177923942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         7271228                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            7271228                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         123176127                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              123176127                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         123176127                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             7271228                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           170652715                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              301100070                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        165341                       # Number of read requests accepted
-system.physmem.writeReqs                       114465                       # Number of write requests accepted
-system.physmem.readBursts                      165341                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114465                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                 10581376                       # Total number of bytes read from DRAM
+system.physmem.bytes_read::cpu.inst            432832                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10149568                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             10582400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       432832                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          432832                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7326016                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7326016                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               6763                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             158587                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                165350                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          114469                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114469                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              7280965                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            170732870                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               178013835                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         7280965                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            7280965                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         123235958                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              123235958                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         123235958                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             7280965                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           170732870                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              301249793                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        165350                       # Number of read requests accepted
+system.physmem.writeReqs                       114469                       # Number of write requests accepted
+system.physmem.readBursts                      165350                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                     114469                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                 10581952                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7323904                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                  10581824                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7325760                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   7323968                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                  10582400                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                7326016                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10312                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10359                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10315                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10360                       # Per bank write bursts
 system.physmem.perBankRdBursts::2               10206                       # Per bank write bursts
 system.physmem.perBankRdBursts::3               10057                       # Per bank write bursts
 system.physmem.perBankRdBursts::4               10348                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10339                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9776                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10343                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9775                       # Per bank write bursts
 system.physmem.perBankRdBursts::7               10207                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10534                       # Per bank write bursts
-system.physmem.perBankRdBursts::9               10607                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10498                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10536                       # Per bank write bursts
+system.physmem.perBankRdBursts::9               10606                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10500                       # Per bank write bursts
 system.physmem.perBankRdBursts::11              10228                       # Per bank write bursts
-system.physmem.perBankRdBursts::12              10274                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10561                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10464                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10564                       # Per bank write bursts
+system.physmem.perBankRdBursts::12              10273                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10559                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10465                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10565                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7163                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                7274                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7296                       # Per bank write bursts
 system.physmem.perBankWrBursts::3                7002                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7187                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7186                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6833                       # Per bank write bursts
 system.physmem.perBankWrBursts::7                7099                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                7225                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7000                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7115                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                7226                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6999                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7117                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               7034                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               6992                       # Per bank write bursts
 system.physmem.perBankWrBursts::13               7299                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               7308                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               7483                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     59473838000                       # Total gap between requests
+system.physmem.totGap                     59447041000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  165341                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  165350                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114465                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    163748                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1560                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        26                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114469                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    163735                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1580                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        28                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      772                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      786                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     6204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     7009                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     7043                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     7065                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     7061                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     7072                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7067                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7070                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7119                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7112                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7212                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     7227                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     7132                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7341                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     7097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     7041                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       13                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      750                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      772                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     6187                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     7002                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     7044                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     7073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     7064                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     7070                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7073                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7076                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7124                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7113                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7242                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     7218                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     7141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7356                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     7098                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     7043                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -193,120 +193,126 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        54714                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      327.237051                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     194.297949                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     330.344141                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          19597     35.82%     35.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        11811     21.59%     57.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5572     10.18%     67.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         3684      6.73%     74.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2893      5.29%     79.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         2049      3.74%     83.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1621      2.96%     86.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1502      2.75%     89.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         5985     10.94%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          54714                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          7041                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.479761                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      336.363256                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           7038     99.96%     99.96% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        54692                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      327.365172                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     194.328231                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     330.549756                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          19615     35.86%     35.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        11787     21.55%     57.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5586     10.21%     67.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         3666      6.70%     74.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2860      5.23%     79.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         2087      3.82%     83.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1603      2.93%     86.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1458      2.67%     88.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         6030     11.03%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          54692                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          7042                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.476853                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      336.379045                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           7039     99.96%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            7041                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          7041                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.252805                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.237164                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.745060                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6251     88.78%     88.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 16      0.23%     89.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                606      8.61%     97.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                134      1.90%     99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 28      0.40%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  4      0.06%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            7041                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1980163000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                5080175500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    826670000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       11976.74                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            7042                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          7042                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.250639                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.234557                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.758479                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6275     89.11%     89.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 11      0.16%     89.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                574      8.15%     97.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                150      2.13%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 18      0.26%     99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  9      0.13%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  2      0.03%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.01%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            7042                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1988923000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                5089104250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    826715000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       12029.07                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  30726.74                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         177.92                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         123.14                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      177.92                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      123.18                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  30779.07                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         178.01                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         123.20                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      178.01                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      123.24                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.35                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.39                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.96                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.98                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     143867                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81182                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.02                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  70.92                       # Row buffer hit rate for writes
-system.physmem.avgGap                       212553.83                       # Average gap between requests
-system.physmem.pageHitRate                      80.43                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  199175760                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  108677250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 636448800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                369204480                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3884381280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            12421725570                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            24786732000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              42406345140                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              713.051581                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    41087166750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1985880000                       # Time in different power states
+system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        23.77                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     143858                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81218                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.01                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  70.95                       # Row buffer hit rate for writes
+system.physmem.avgGap                       212448.19                       # Average gap between requests
+system.physmem.pageHitRate                      80.44                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  199274040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  108730875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 636347400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                369068400                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3882347040                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            12411408285                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            24777095250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              42384271290                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              713.053838                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    41070575000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1984840000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     16398707250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     16385091250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  214341120                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  116952000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 652938000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                372237120                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3884381280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            13062187260                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24224923500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              42527960280                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              715.096508                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40147172500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1985880000                       # Time in different power states
+system.physmem_1.actEnergy                  213940440                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  116733375                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 652860000                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                372152880                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3882347040                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            13085746785                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24185582250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              42509362770                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              715.158080                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40083292000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1984840000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     17338598750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     17372590500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14666171                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9489023                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            386095                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9897790                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6385525                       # Number of BTB hits
+system.cpu.branchPred.lookups                14660042                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9484785                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            381684                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9866507                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6346497                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             64.514654                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1708105                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              84877                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             64.323646                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1708762                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              84355                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           37443                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              31778                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             5665                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         7605                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20569903                       # DTB read hits
-system.cpu.dtb.read_misses                      97320                       # DTB read misses
-system.cpu.dtb.read_acv                            10                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20667223                       # DTB read accesses
-system.cpu.dtb.write_hits                    14665328                       # DTB write hits
-system.cpu.dtb.write_misses                      9407                       # DTB write misses
+system.cpu.dtb.read_hits                     20565775                       # DTB read hits
+system.cpu.dtb.read_misses                      97355                       # DTB read misses
+system.cpu.dtb.read_acv                             8                       # DTB read access violations
+system.cpu.dtb.read_accesses                 20663130                       # DTB read accesses
+system.cpu.dtb.write_hits                    14665271                       # DTB write hits
+system.cpu.dtb.write_misses                      9409                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                14674735                       # DTB write accesses
-system.cpu.dtb.data_hits                     35235231                       # DTB hits
-system.cpu.dtb.data_misses                     106727                       # DTB misses
-system.cpu.dtb.data_acv                            10                       # DTB access violations
-system.cpu.dtb.data_accesses                 35341958                       # DTB accesses
-system.cpu.itb.fetch_hits                    25606544                       # ITB hits
-system.cpu.itb.fetch_misses                      5228                       # ITB misses
+system.cpu.dtb.write_accesses                14674680                       # DTB write accesses
+system.cpu.dtb.data_hits                     35231046                       # DTB hits
+system.cpu.dtb.data_misses                     106764                       # DTB misses
+system.cpu.dtb.data_acv                             8                       # DTB access violations
+system.cpu.dtb.data_accesses                 35337810                       # DTB accesses
+system.cpu.itb.fetch_hits                    25585531                       # ITB hits
+system.cpu.itb.fetch_misses                      5208                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                25611772                       # ITB accesses
+system.cpu.itb.fetch_accesses                25590739                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -320,81 +326,116 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                        118947724                       # number of cpu cycles simulated
+system.cpu.numCycles                        118894130                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    88438073                       # Number of instructions committed
 system.cpu.committedOps                      88438073                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1106117                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1097381                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.344983                       # CPI: cycles per instruction
-system.cpu.ipc                               0.743504                       # IPC: instructions per cycle
-system.cpu.tickCycles                        91473408                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        27474316                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.344377                       # CPI: cycles per instruction
+system.cpu.ipc                               0.743839                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass             8748916      9.89%      9.89% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                44394799     50.20%     60.09% # Class of committed instruction
+system.cpu.op_class_0::IntMult                  41101      0.05%     60.14% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     60.14% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                114304      0.13%     60.27% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                    84      0.00%     60.27% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                113640      0.13%     60.40% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                   50      0.00%     60.40% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                 37764      0.04%     60.44% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     60.44% # Class of committed instruction
+system.cpu.op_class_0::MemRead               20366786     23.03%     83.47% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              14620629     16.53%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                 88438073                       # Class of committed instruction
+system.cpu.tickCycles                        91425505                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        27468625                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            200766                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.683377                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            34616213                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4070.673886                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            34612040                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            204862                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            168.973324                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         687575500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.683377                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993819                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993819                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.avg_refs            168.952954                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         687650500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.673886                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993817                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993817                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           48                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          687                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         3361                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         3360                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70176360                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70176360                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20282952                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20282952                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     14333261                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       14333261                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      34616213                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         34616213                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     34616213                       # number of overall hits
-system.cpu.dcache.overall_hits::total        34616213                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89420                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89420                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       280116                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       280116                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       369536                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         369536                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       369536                       # number of overall misses
-system.cpu.dcache.overall_misses::total        369536                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   4768019500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   4768019500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  21708920500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  21708920500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  26476940000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  26476940000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  26476940000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  26476940000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20372372                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20372372                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70168000                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70168000                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20278781                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20278781                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     14333259                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14333259                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      34612040                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34612040                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34612040                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34612040                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89411                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89411                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       280118                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       280118                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       369529                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         369529                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       369529                       # number of overall misses
+system.cpu.dcache.overall_misses::total        369529                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4770299000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4770299000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21700228000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21700228000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  26470527000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  26470527000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  26470527000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  26470527000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20368192                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20368192                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     34985749                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     34985749                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     34985749                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     34985749                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004389                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004389                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.019168                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.010562                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.010562                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.010562                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.010562                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53321.622679                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 53321.622679                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77499.751889                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 77499.751889                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71649.149203                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71649.149203                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71649.149203                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71649.149203                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     34981569                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34981569                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     34981569                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34981569                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004390                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004390                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.019169                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.019169                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.010564                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.010564                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.010564                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.010564                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53352.484594                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 53352.484594                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77468.166987                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 77468.166987                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 71633.151931                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 71633.151931                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 71633.151931                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 71633.151931                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -403,103 +444,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168423                       # number of writebacks
-system.cpu.dcache.writebacks::total            168423                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28115                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        28115                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136559                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       136559                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       164674                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       164674                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       164674                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       164674                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61305                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        61305                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143557                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143557                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       168424                       # number of writebacks
+system.cpu.dcache.writebacks::total            168424                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        28112                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        28112                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       136555                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       136555                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       164667                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       164667                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       164667                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       164667                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        61299                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        61299                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143563                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143563                       # number of WriteReq MSHR misses
 system.cpu.dcache.demand_mshr_misses::cpu.data       204862                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total       204862                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       204862                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       204862                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2680071500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   2680071500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10970928000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  10970928000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13650999500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13650999500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13650999500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13650999500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003009                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003009                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2681247500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2681247500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  10975422500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  10975422500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13656670000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  13656670000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13656670000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  13656670000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009824                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009824                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.005856                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005856                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.005856                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43717.013294                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43717.013294                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76422.104112                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76422.104112                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66635.098261                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66635.098261                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66635.098261                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 66635.098261                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43740.477006                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43740.477006                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76450.216978                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76450.216978                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66662.777870                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66662.777870                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66662.777870                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            152856                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1932.301021                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            25451639                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            154904                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            164.305886                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       42254913500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1932.301021                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.943506                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.943506                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            152872                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1932.382407                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            25430610                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            154920                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            164.153176                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       42235793500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1932.382407                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.943546                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.943546                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           49                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          159                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1041                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1039                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          798                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          51367992                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         51367992                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     25451639                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25451639                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25451639                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25451639                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25451639                       # number of overall hits
-system.cpu.icache.overall_hits::total        25451639                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       154905                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        154905                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       154905                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         154905                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       154905                       # number of overall misses
-system.cpu.icache.overall_misses::total        154905                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2479923000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2479923000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2479923000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2479923000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2479923000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2479923000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25606544                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25606544                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25606544                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25606544                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25606544                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25606544                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006049                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.006049                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.006049                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.006049                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.006049                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.006049                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16009.315387                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16009.315387                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16009.315387                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16009.315387                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16009.315387                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16009.315387                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          51325982                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         51325982                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     25430610                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25430610                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25430610                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25430610                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25430610                       # number of overall hits
+system.cpu.icache.overall_hits::total        25430610                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       154921                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        154921                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       154921                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         154921                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       154921                       # number of overall misses
+system.cpu.icache.overall_misses::total        154921                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2483739000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2483739000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2483739000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2483739000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2483739000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2483739000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25585531                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25585531                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25585531                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25585531                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25585531                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25585531                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006055                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.006055                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.006055                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.006055                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.006055                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.006055                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16032.293879                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16032.293879                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16032.293879                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16032.293879                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16032.293879                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16032.293879                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -508,135 +549,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       152856                       # number of writebacks
-system.cpu.icache.writebacks::total            152856                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154905                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       154905                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       154905                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       154905                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       154905                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       154905                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2325019000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2325019000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2325019000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2325019000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2325019000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2325019000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006049                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006049                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006049                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006049                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15009.321842                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15009.321842                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15009.321842                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 15009.321842                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15009.321842                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 15009.321842                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       152872                       # number of writebacks
+system.cpu.icache.writebacks::total            152872                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       154921                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       154921                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       154921                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       154921                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       154921                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       154921                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2328819000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2328819000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2328819000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2328819000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2328819000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2328819000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006055                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006055                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006055                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006055                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006055                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006055                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15032.300334                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15032.300334                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15032.300334                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15032.300334                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 15032.300334                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           133370                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30430.165732                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             403981                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           165480                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.441268                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           133382                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30429.048447                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             403995                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           165492                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.441175                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26353.973497                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2093.222263                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1982.969972                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.804259                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.063880                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.060515                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.928655                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 26350.763451                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2094.967777                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1983.317219                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.804161                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.063933                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.060526                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.928621                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        32110                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          165                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1089                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11867                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        18864                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          125                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1093                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11874                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        18854                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          124                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.979919                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          6016150                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         6016150                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       168423                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       168423                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       152856                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       152856                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12675                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12675                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       148147                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       148147                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        33603                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        33603                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       148147                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46278                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          194425                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       148147                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46278                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         194425                       # number of overall hits
+system.cpu.l2cache.tags.tag_accesses          6016424                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         6016424                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       168424                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       168424                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       152872                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       152872                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12681                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12681                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       148157                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       148157                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        33594                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        33594                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       148157                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46275                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          194432                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       148157                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        46275                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         194432                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data       130883                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       130883                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6758                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         6758                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27701                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        27701                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         6758                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data       158584                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        165342                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         6758                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data       158584                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       165342                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10622451000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  10622451000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    536913000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    536913000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2234805000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2234805000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    536913000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  12857256000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  13394169000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    536913000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  12857256000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  13394169000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       168423                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       168423                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       152856                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       152856                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143558                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143558                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       154905                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       154905                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        61304                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        61304                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       154905                       # number of demand (read+write) accesses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6764                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         6764                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27704                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        27704                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         6764                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       158587                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        165351                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         6764                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       158587                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       165351                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  10626878000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  10626878000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    540586000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    540586000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2236085500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2236085500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    540586000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  12862963500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  13403549500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    540586000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  12862963500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  13403549500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       168424                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       168424                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       152872                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       152872                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143564                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143564                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       154921                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       154921                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        61298                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        61298                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       154921                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data       204862                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       359767                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       154905                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       359783                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       154921                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data       204862                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       359767                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911708                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.911708                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.043627                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.043627                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.451863                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.451863                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.043627                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.774102                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.459581                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.043627                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.774102                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.459581                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81159.898535                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81159.898535                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79448.505475                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79448.505475                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80675.968377                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80675.968377                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79448.505475                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81075.366998                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81008.872519                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79448.505475                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81075.366998                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81008.872519                       # average overall miss latency
+system.cpu.l2cache.overall_accesses::total       359783                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.911670                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.911670                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.043661                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.043661                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.451956                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.451956                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.043661                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.774116                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.459585                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.043661                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.774116                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.459585                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81193.722638                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81193.722638                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79921.052632                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79921.052632                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80713.452931                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80713.452931                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79921.052632                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81109.822999                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81061.194066                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79921.052632                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81109.822999                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81061.194066                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -645,123 +686,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114465                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114465                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks       114469                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114469                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          115                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          115                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130883                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       130883                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6758                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6758                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27701                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27701                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         6758                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data       158584                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       165342                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         6758                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data       158584                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       165342                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9313621000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9313621000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    469343000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    469343000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1957795000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1957795000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    469343000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11271416000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  11740759000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    469343000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11271416000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  11740759000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6764                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6764                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27704                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27704                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         6764                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       158587                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       165351                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         6764                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       158587                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       165351                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9318048000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9318048000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    472956000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    472956000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1959045500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1959045500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    472956000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  11277093500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  11750049500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    472956000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  11277093500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  11750049500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911708                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911708                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.043627                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.043627                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.451863                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451863                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.043627                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.774102                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.459581                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.043627                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.774102                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.459581                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71159.898535                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71159.898535                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69449.985203                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69449.985203                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70675.968377                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70675.968377                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69449.985203                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71075.366998                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71008.932999                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69449.985203                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71075.366998                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71008.932999                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.911670                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.911670                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.043661                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.043661                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.451956                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.451956                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.043661                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.774116                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.459585                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.043661                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.774116                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.459585                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71193.722638                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71193.722638                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69922.531047                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69922.531047                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70713.452931                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70713.452931                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69922.531047                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71109.822999                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71061.254543                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.531047                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71109.822999                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71061.254543                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       713389                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       353622                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests       713421                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       353638                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         4036                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4036                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         4037                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4037                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        216208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       282888                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       152856                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        51248                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143558                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143558                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       154905                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        61304                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       462665                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp        216218                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       282893                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       152872                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        51255                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143564                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143564                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       154921                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        61298                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       462713                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       610490                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           1073155                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     19696640                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23890240                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           43586880                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      133370                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       493137                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.008184                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.090096                       # Request fanout histogram
+system.cpu.toL2Bus.pkt_count::total           1073203                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     19698688                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23890304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           43588992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      133382                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       493165                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.008186                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.090105                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             489101     99.18%     99.18% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               4036      0.82%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             489128     99.18%     99.18% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               4037      0.82%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         493137                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      677973500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         493165                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      678006500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     232357497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     232381497                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     307299487                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     307297491                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.5                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              34458                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       114465                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            14983                       # Transaction distribution
+system.membus.trans_dist::ReadResp              34467                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       114469                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14990                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            130883                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           130883                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         34458                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       460130                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 460130                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17907584                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17907584                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq         34467                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       460159                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 460159                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17908416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17908416                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            294789                       # Request fanout histogram
+system.membus.snoop_fanout::samples            294809                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  294789    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  294809    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              294789                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           822943500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              294809                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           822950500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.4                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          872924250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          872961750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.5                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
index 5beee1623..8a6383ef9 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.022297                       # Number of seconds simulated
-sim_ticks                                 22296591500                       # Number of ticks simulated
-final_tick                                22296591500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.022275                       # Number of seconds simulated
+sim_ticks                                 22275010500                       # Number of ticks simulated
+final_tick                                22275010500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 210659                       # Simulator instruction rate (inst/s)
-host_op_rate                                   210659                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               59013272                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309644                       # Number of bytes of host memory used
-host_seconds                                   377.82                       # Real time elapsed on the host
+host_inst_rate                                 279038                       # Simulator instruction rate (inst/s)
+host_op_rate                                   279038                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               78093188                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 263768                       # Number of bytes of host memory used
+host_seconds                                   285.24                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
 sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -18,71 +18,71 @@ system.physmem.bytes_read::cpu.data          10153216                       # Nu
 system.physmem.bytes_read::total             10563200                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst       409984                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total          409984                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7322432                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7322432                       # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks      7322816                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7322816                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.inst               6406                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data             158644                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                165050                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          114413                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               114413                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             18387743                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            455370768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               473758511                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        18387743                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           18387743                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         328410376                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              328410376                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         328410376                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            18387743                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           455370768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              802168888                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::writebacks          114419                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               114419                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             18405558                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            455811951                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               474217509                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        18405558                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           18405558                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         328745793                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              328745793                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         328745793                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            18405558                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           455811951                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              802963303                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        165050                       # Number of read requests accepted
-system.physmem.writeReqs                       114413                       # Number of write requests accepted
+system.physmem.writeReqs                       114419                       # Number of write requests accepted
 system.physmem.readBursts                      165050                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                     114413                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.writeBursts                     114419                       # Number of DRAM write bursts, including those merged in the write queue
 system.physmem.bytesReadDRAM                 10562816                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   7320896                       # Total number of bytes written to DRAM
+system.physmem.bytesWritten                   7320960                       # Total number of bytes written to DRAM
 system.physmem.bytesReadSys                  10563200                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                7322432                       # Total written bytes from the system interface side
+system.physmem.bytesWrittenSys                7322816                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0               10292                       # Per bank write bursts
-system.physmem.perBankRdBursts::1               10329                       # Per bank write bursts
-system.physmem.perBankRdBursts::2               10209                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               10020                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10344                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10314                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9779                       # Per bank write bursts
-system.physmem.perBankRdBursts::7               10195                       # Per bank write bursts
-system.physmem.perBankRdBursts::8               10531                       # Per bank write bursts
+system.physmem.perBankRdBursts::0               10290                       # Per bank write bursts
+system.physmem.perBankRdBursts::1               10331                       # Per bank write bursts
+system.physmem.perBankRdBursts::2               10206                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               10021                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10343                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               10313                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                9783                       # Per bank write bursts
+system.physmem.perBankRdBursts::7               10190                       # Per bank write bursts
+system.physmem.perBankRdBursts::8               10528                       # Per bank write bursts
 system.physmem.perBankRdBursts::9               10599                       # Per bank write bursts
-system.physmem.perBankRdBursts::10              10453                       # Per bank write bursts
-system.physmem.perBankRdBursts::11              10204                       # Per bank write bursts
+system.physmem.perBankRdBursts::10              10456                       # Per bank write bursts
+system.physmem.perBankRdBursts::11              10208                       # Per bank write bursts
 system.physmem.perBankRdBursts::12              10247                       # Per bank write bursts
-system.physmem.perBankRdBursts::13              10532                       # Per bank write bursts
-system.physmem.perBankRdBursts::14              10447                       # Per bank write bursts
-system.physmem.perBankRdBursts::15              10549                       # Per bank write bursts
+system.physmem.perBankRdBursts::13              10535                       # Per bank write bursts
+system.physmem.perBankRdBursts::14              10446                       # Per bank write bursts
+system.physmem.perBankRdBursts::15              10548                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                7163                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                7267                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                7268                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                7294                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                7000                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                7001                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                7127                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                7180                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                7177                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                6836                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                7102                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                7101                       # Per bank write bursts
 system.physmem.perBankWrBursts::8                7221                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                7001                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               7100                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               7020                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6992                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               7297                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                7003                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               7101                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               7022                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6991                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               7296                       # Per bank write bursts
 system.physmem.perBankWrBursts::14               7307                       # Per bank write bursts
 system.physmem.perBankWrBursts::15               7482                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     22296560500                       # Total gap between requests
+system.physmem.totGap                     22274979500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -96,13 +96,13 @@ system.physmem.writePktSize::2                      0                       # Wr
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                 114413                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     51457                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     43023                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     38384                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     32167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                 114419                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     51518                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     43059                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     38387                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     32071                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -144,32 +144,32 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      838                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      874                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1898                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     3531                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     4839                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     6052                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     6591                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     6876                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     7135                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     7308                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     7518                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7900                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     7742                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8305                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    10160                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     8364                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     9639                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     8083                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      381                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      175                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      104                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       44                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       28                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        5                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      830                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      876                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1910                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     3461                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     4816                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     6066                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     6564                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     6883                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     7150                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     7278                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     7547                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7867                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     7697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8298                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    10179                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     8300                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     9731                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     8127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      391                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                      198                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      127                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       69                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       25                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        8                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
@@ -193,124 +193,126 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        52310                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      341.858612                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     200.924906                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     342.625607                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          18434     35.24%     35.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        10645     20.35%     55.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         5863     11.21%     66.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2906      5.56%     72.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2975      5.69%     78.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1493      2.85%     80.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         2022      3.87%     84.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          988      1.89%     86.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         6984     13.35%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          52310                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples        52304                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      341.896604                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     200.837447                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     342.790414                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          18483     35.34%     35.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        10568     20.20%     55.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         5879     11.24%     66.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2936      5.61%     72.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2943      5.63%     78.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1490      2.85%     80.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         2026      3.87%     84.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          952      1.82%     86.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         7027     13.43%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          52304                       # Bytes accessed per row activation
 system.physmem.rdPerTurnAround::samples          6990                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        23.610300                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      338.218951                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           6987     99.96%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047            2      0.03%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        23.609728                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      338.236069                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           6988     99.97%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047            1      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::27648-28671            1      0.01%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::total            6990                       # Reads before turning the bus around for writes
 system.physmem.wrPerTurnAround::samples          6990                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.364664                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.334270                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.064891                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               6098     87.24%     87.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 26      0.37%     87.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                456      6.52%     94.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                208      2.98%     97.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                103      1.47%     98.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 57      0.82%     99.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 21      0.30%     99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 10      0.14%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  8      0.11%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.01%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.01%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.01%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.364807                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.334911                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.053834                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               6086     87.07%     87.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 35      0.50%     87.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                455      6.51%     94.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                219      3.13%     97.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                100      1.43%     98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 53      0.76%     99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 22      0.31%     99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 11      0.16%     99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  7      0.10%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  2      0.03%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::total            6990                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     5731685000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                8826260000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat                     5740232250                       # Total ticks spent queuing
+system.physmem.totMemAccLat                8834807250                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                    825220000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       34728.22                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                       34780.01                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  53478.22                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         473.74                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         328.34                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      473.76                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      328.41                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  53530.01                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         474.20                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         328.66                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      474.22                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      328.75                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           6.27                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       3.70                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      2.57                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.93                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.49                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     145441                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     81669                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   88.12                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  71.38                       # Row buffer hit rate for writes
-system.physmem.avgGap                        79783.59                       # Average gap between requests
+system.physmem.avgWrQLen                        24.33                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     145488                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     81629                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   88.15                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  71.34                       # Row buffer hit rate for writes
+system.physmem.avgGap                        79704.65                       # Average gap between requests
 system.physmem.pageHitRate                      81.27                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  190375920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  103875750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 635356800                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                369036000                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             6553881090                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             7626357750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              16934890590                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              759.674656                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    12601715000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       744380000                       # Time in different power states
+system.physmem_0.actEnergy                  190428840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  103904625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 635177400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                368951760                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             1454481600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             6564184695                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             7603330500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              16920459420                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              759.821975                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    12566232250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       743600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      8946212500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      8959159250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  204815520                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  111754500                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  204618960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  111647250                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 651565200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                371893680                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1456007280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             6747677955                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             7456388250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              17000102385                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              762.598381                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    12320846000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       744380000                       # Time in different power states
+system.physmem_1.writeEnergy                371861280                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             1454481600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             6822625545                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             7376602500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              16993402335                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              763.098971                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    12188749750                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       743600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      9227273000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      9336732250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16493971                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          10685365                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            327092                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8977635                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7282355                       # Number of BTB hits
+system.cpu.branchPred.lookups                16474744                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          10670267                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            324432                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8918177                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7235165                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             81.116630                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1973286                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect               2952                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             81.128296                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1973322                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect               3328                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           39379                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              31470                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             7909                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted         2657                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     22518673                       # DTB read hits
-system.cpu.dtb.read_misses                     225961                       # DTB read misses
-system.cpu.dtb.read_acv                            15                       # DTB read access violations
-system.cpu.dtb.read_accesses                 22744634                       # DTB read accesses
-system.cpu.dtb.write_hits                    15824450                       # DTB write hits
-system.cpu.dtb.write_misses                     44763                       # DTB write misses
+system.cpu.dtb.read_hits                     22508484                       # DTB read hits
+system.cpu.dtb.read_misses                     226837                       # DTB read misses
+system.cpu.dtb.read_acv                            16                       # DTB read access violations
+system.cpu.dtb.read_accesses                 22735321                       # DTB read accesses
+system.cpu.dtb.write_hits                    15806842                       # DTB write hits
+system.cpu.dtb.write_misses                     44564                       # DTB write misses
 system.cpu.dtb.write_acv                            4                       # DTB write access violations
-system.cpu.dtb.write_accesses                15869213                       # DTB write accesses
-system.cpu.dtb.data_hits                     38343123                       # DTB hits
-system.cpu.dtb.data_misses                     270724                       # DTB misses
-system.cpu.dtb.data_acv                            19                       # DTB access violations
-system.cpu.dtb.data_accesses                 38613847                       # DTB accesses
-system.cpu.itb.fetch_hits                    13750650                       # ITB hits
-system.cpu.itb.fetch_misses                     29320                       # ITB misses
+system.cpu.dtb.write_accesses                15851406                       # DTB write accesses
+system.cpu.dtb.data_hits                     38315326                       # DTB hits
+system.cpu.dtb.data_misses                     271401                       # DTB misses
+system.cpu.dtb.data_acv                            20                       # DTB access violations
+system.cpu.dtb.data_accesses                 38586727                       # DTB accesses
+system.cpu.itb.fetch_hits                    13727245                       # ITB hits
+system.cpu.itb.fetch_misses                     29559                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                13779970                       # ITB accesses
+system.cpu.itb.fetch_accesses                13756804                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -324,141 +326,141 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
-system.cpu.numCycles                         44593188                       # number of cpu cycles simulated
+system.cpu.numCycles                         44550025                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           15564341                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      105145283                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16493971                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9255641                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      27572822                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                  891924                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                        262                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 4803                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        325760                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           89                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13750650                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                190232                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles           15536362                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      105039044                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16474744                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9239957                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      27563903                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                  886514                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        244                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 4722                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        331564                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles           78                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13727245                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                187963                       # Number of outstanding Icache misses that were squashed
 system.cpu.fetch.ItlbSquashes                       1                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples           43914039                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.394343                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.128103                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples           43880130                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.393772                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.128235                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 24384273     55.53%     55.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1520929      3.46%     58.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1376099      3.13%     62.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1504413      3.43%     65.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4198532      9.56%     75.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1828676      4.16%     79.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   668520      1.52%     80.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1050487      2.39%     83.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  7382110     16.81%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 24375049     55.55%     55.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1515026      3.45%     59.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1375639      3.13%     62.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1503768      3.43%     65.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  4189647      9.55%     75.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1825739      4.16%     79.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   668569      1.52%     80.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1050805      2.39%     83.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  7375888     16.81%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43914039                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.369876                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.357878                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 14911775                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               9756593                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  18301996                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                594945                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 348730                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3706760                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 98994                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              103174683                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                312811                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 348730                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 15258388                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4434115                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          96788                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18534618                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               5241400                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              102158813                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  5649                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  94745                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                 345515                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                4735615                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            61411273                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             123213365                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        122896091                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            317273                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43880130                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.369803                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.357777                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 14899233                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               9760394                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  18283223                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                591754                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 345526                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3700749                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 99293                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              103056970                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                314917                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 345526                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 15243567                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4452634                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          97322                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18515033                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               5226048                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              102057831                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  7235                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  94720                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                 348136                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                4717245                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            61355857                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             123078605                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        122759511                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            319093                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              52546881                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  8864392                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               5712                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           5765                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   2362727                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             23149705                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            16384887                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1256801                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           494099                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   90814957                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5561                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  88678954                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             70817                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        11228761                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      4483589                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            978                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43914039                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.019376                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.246135                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  8808976                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               5695                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           5747                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   2360993                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             23135657                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            16359365                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1252776                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           502701                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   90727911                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                5569                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  88607473                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             70141                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        11141723                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      4452155                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            986                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43880130                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.019307                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.245631                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            17441953     39.72%     39.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             5726957     13.04%     52.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5104887     11.62%     64.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             4381256      9.98%     74.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4320313      9.84%     84.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2639459      6.01%     90.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1947949      4.44%     94.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1377906      3.14%     97.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              973359      2.22%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17424086     39.71%     39.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             5721163     13.04%     52.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5107482     11.64%     64.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             4378378      9.98%     74.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4320360      9.85%     84.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2636536      6.01%     90.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1944467      4.43%     94.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1375974      3.14%     97.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              971684      2.21%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43914039                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43880130                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  242855      9.63%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1163309     46.14%     55.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               1115010     44.23%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  243434      9.65%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1167545     46.27%     55.92% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               1112329     44.08%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49423838     55.73%     55.73% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                43986      0.05%     55.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49382948     55.73%     55.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                43980      0.05%     55.78% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     55.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              121174      0.14%     55.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              121151      0.14%     55.92% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                  92      0.00%     55.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt              120676      0.14%     56.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 62      0.00%     56.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv               39089      0.04%     56.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt              120663      0.14%     56.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 62      0.00%     56.05% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv               39093      0.04%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     56.10% # Type of FU issued
@@ -480,82 +482,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.10% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.10% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             22912706     25.84%     81.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            16017331     18.06%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             22902831     25.85%     81.95% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            15996653     18.05%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               88678954                       # Type of FU issued
-system.cpu.iq.rate                           1.988621                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2521174                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.028430                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          223254204                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         101651163                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     86893480                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              609734                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             418232                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       299390                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               90895107                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  305021                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1671418                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               88607473                       # Type of FU issued
+system.cpu.iq.rate                           1.988943                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2523308                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.028477                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          223077288                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         101475255                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     86832445                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              611237                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             420100                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       299852                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               90825011                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  305770                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1671661                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      2873067                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         5610                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        20361                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1771510                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      2859019                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         5476                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        20375                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1745988                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3045                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        204833                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3024                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        205293                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 348730                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1277507                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               2721681                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           100319642                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            124919                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              23149705                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             16384887                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5561                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3725                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               2720217                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          20361                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         118662                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       150973                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               269635                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              87973235                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              22745315                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            705719                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 345526                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1271875                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               2754338                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           100226384                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            125320                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              23135657                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             16359365                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5569                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3722                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               2752972                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          20375                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         115768                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       151556                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               267324                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              87911556                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              22736014                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            695917                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       9499124                       # number of nop insts executed
-system.cpu.iew.exec_refs                     38614853                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 15126858                       # Number of branches executed
-system.cpu.iew.exec_stores                   15869538                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.972795                       # Inst execution rate
-system.cpu.iew.wb_sent                       87594856                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87192870                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  33852684                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  44279326                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.955296                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.764526                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         8765402                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                       9492904                       # number of nop insts executed
+system.cpu.iew.exec_refs                     38587764                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 15119893                       # Number of branches executed
+system.cpu.iew.exec_stores                   15851750                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.973322                       # Inst execution rate
+system.cpu.iew.wb_sent                       87534383                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87132297                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  33840523                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  44256350                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.955830                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.764648                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         8655398                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            229860                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     42628268                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.072350                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.885151                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            226701                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     42610108                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.073233                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.886041                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     21157300     49.63%     49.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      6282680     14.74%     64.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      2903206      6.81%     71.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1743375      4.09%     75.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1680050      3.94%     79.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1128930      2.65%     81.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1204133      2.82%     84.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       796945      1.87%     86.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      5731649     13.45%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     21149437     49.63%     49.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      6275459     14.73%     64.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      2900348      6.81%     71.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1740796      4.09%     75.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1682035      3.95%     79.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1127009      2.64%     81.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1202859      2.82%     84.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       795530      1.87%     86.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      5736635     13.46%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     42628268                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     42610108                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
 system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -601,339 +603,339 @@ system.cpu.commit.op_class_0::MemWrite       14613377     16.54%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          88340672                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               5731649                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    132685351                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195501271                       # The number of ROB writes
-system.cpu.timesIdled                           46319                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          679149                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               5736635                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    132552201                       # The number of ROB reads
+system.cpu.rob.rob_writes                   195265380                       # The number of ROB writes
+system.cpu.timesIdled                           45343                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          669895                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
 system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.560274                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.560274                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.784841                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.784841                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                116453986                       # number of integer regfile reads
-system.cpu.int_regfile_writes                57709287                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    255067                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   240450                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                   38270                       # number of misc regfile reads
+system.cpu.cpi                               0.559732                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.559732                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.786570                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.786570                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                116366061                       # number of integer regfile reads
+system.cpu.int_regfile_writes                57668563                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    255567                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   240367                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                   38271                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            201399                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4070.676822                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            33995451                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            205495                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            165.432011                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements            201418                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4070.642288                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            33984828                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            205514                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            165.365026                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         229821500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4070.676822                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.993818                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.993818                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4070.642288                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.993809                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.993809                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2778                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         1242                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2776                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         1244                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          70838999                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         70838999                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20434147                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20434147                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     13561246                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       13561246                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data           58                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total           58                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      33995393                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         33995393                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     33995393                       # number of overall hits
-system.cpu.dcache.overall_hits::total        33995393                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       269170                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        269170                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1052131                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1052131                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1321301                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1321301                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1321301                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1321301                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  17282869000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  17282869000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  89120990413                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  89120990413                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 106403859413                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 106403859413                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 106403859413                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 106403859413                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20703317                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20703317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses          70818146                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         70818146                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20423642                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20423642                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13561123                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13561123                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           63                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           63                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      33984765                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         33984765                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     33984765                       # number of overall hits
+system.cpu.dcache.overall_hits::total        33984765                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       269234                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        269234                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1052254                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1052254                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1321488                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1321488                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1321488                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1321488                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  17321162000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  17321162000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  89091667377                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  89091667377                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 106412829377                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 106412829377                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 106412829377                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 106412829377                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20692876                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20692876                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data           58                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total           58                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     35316694                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     35316694                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     35316694                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     35316694                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.013001                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.013001                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.071998                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.071998                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037413                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037413                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037413                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037413                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64208.006093                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 64208.006093                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84705.222461                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 84705.222461                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 80529.613928                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 80529.613928                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 80529.613928                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 80529.613928                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs      6870751                       # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           63                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           63                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35306253                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35306253                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35306253                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35306253                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.013011                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.013011                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.072006                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.072006                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037429                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037429                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037429                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037429                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64334.972552                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 64334.972552                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84667.454224                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 84667.454224                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 80525.006188                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 80525.006188                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 80525.006188                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 80525.006188                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs      6873080                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          275                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             89149                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             89218                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.070421                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    77.036921                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets   137.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       168802                       # number of writebacks
-system.cpu.dcache.writebacks::total            168802                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207068                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       207068                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908738                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       908738                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1115806                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1115806                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1115806                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1115806                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62102                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        62102                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143393                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       143393                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       205495                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       205495                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       205495                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       205495                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3198491500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3198491500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14240616218                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  14240616218                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17439107718                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  17439107718                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17439107718                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  17439107718                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003000                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003000                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks       168806                       # number of writebacks
+system.cpu.dcache.writebacks::total            168806                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       207108                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       207108                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       908866                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       908866                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1115974                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1115974                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1115974                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1115974                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62126                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62126                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143388                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143388                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205514                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205514                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205514                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205514                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3205966000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3205966000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  14246299714                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  14246299714                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  17452265714                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  17452265714                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  17452265714                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  17452265714                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003002                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.003002                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009812                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.009812                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005819                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.005819                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005819                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.005819                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51503.840456                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51503.840456                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99311.794983                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99311.794983                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84863.902859                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 84863.902859                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84863.902859                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 84863.902859                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005821                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.005821                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005821                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.005821                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51604.255867                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51604.255867                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99354.895207                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99354.895207                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84920.081912                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 84920.081912                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84920.081912                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 84920.081912                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             91476                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1915.700741                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            13644579                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             93524                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            145.893878                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       18771424500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1915.700741                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.935401                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.935401                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             90292                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1916.963164                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            13622372                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             92340                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            147.524063                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       18757985500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  1916.963164                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.936017                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.936017                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           68                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           98                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          105                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2           25                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3         1477                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          380                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3         1468                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          384                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          27594820                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         27594820                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     13644579                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        13644579                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      13644579                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         13644579                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     13644579                       # number of overall hits
-system.cpu.icache.overall_hits::total        13644579                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       106069                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        106069                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       106069                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         106069                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       106069                       # number of overall misses
-system.cpu.icache.overall_misses::total        106069                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1942429499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1942429499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1942429499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1942429499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1942429499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1942429499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13750648                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13750648                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13750648                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13750648                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13750648                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13750648                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007714                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.007714                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.007714                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.007714                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.007714                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.007714                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18312.885942                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 18312.885942                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 18312.885942                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 18312.885942                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 18312.885942                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 18312.885942                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs         1399                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          27546828                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         27546828                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     13622372                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13622372                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13622372                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13622372                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13622372                       # number of overall hits
+system.cpu.icache.overall_hits::total        13622372                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       104872                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        104872                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       104872                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         104872                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       104872                       # number of overall misses
+system.cpu.icache.overall_misses::total        104872                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1921920999                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1921920999                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1921920999                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1921920999                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1921920999                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1921920999                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13727244                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13727244                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13727244                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13727244                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13727244                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13727244                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.007640                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.007640                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.007640                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.007640                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.007640                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.007640                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18326.350208                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 18326.350208                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18326.350208                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 18326.350208                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18326.350208                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 18326.350208                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          573                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                14                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                12                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    99.928571                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    47.750000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        91476                       # number of writebacks
-system.cpu.icache.writebacks::total             91476                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12544                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        12544                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        12544                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        12544                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        12544                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        12544                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        93525                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        93525                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        93525                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        93525                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        93525                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        93525                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1588807000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1588807000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1588807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1588807000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1588807000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1588807000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006801                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.006801                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006801                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.006801                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16988.045977                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16988.045977                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16988.045977                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16988.045977                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        90292                       # number of writebacks
+system.cpu.icache.writebacks::total             90292                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        12531                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        12531                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        12531                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        12531                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        12531                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        12531                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        92341                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        92341                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        92341                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        92341                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        92341                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        92341                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1570228500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1570228500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1570228500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1570228500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1570228500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1570228500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006727                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.006727                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006727                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.006727                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006727                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.006727                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17004.672897                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17004.672897                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17004.672897                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17004.672897                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17004.672897                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17004.672897                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements           133079                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30599.466713                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             282960                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           165171                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.713134                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements           133082                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30595.837110                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             280630                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           165175                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.698986                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26801.500889                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1873.610433                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1924.355391                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.817917                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.057178                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.058727                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.933822                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        32092                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          235                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3119                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28323                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 26800.034004                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1869.508141                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1926.294965                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.817872                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.057053                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.058786                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.933711                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        32093                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          232                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         3131                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        28315                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          361                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4           54                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.979370                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          5043725                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         5043725                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       168802                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       168802                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        91476                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        91476                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data        12610                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total        12610                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        87118                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        87118                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34241                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        34241                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        87118                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        46851                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          133969                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        87118                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        46851                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         133969                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       130784                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       130784                       # number of ReadExReq misses
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.979401                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          5025086                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         5025086                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       168806                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       168806                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        90292                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        90292                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12611                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12611                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        85934                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        85934                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        34259                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        34259                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        85934                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        46870                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          132804                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        85934                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        46870                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         132804                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       130780                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       130780                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         6407                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total         6407                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27860                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        27860                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        27864                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        27864                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         6407                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data       158644                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total        165051                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         6407                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       158644                       # number of overall misses
 system.cpu.l2cache.overall_misses::total       165051                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13888951000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  13888951000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    529244000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    529244000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2740840500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2740840500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    529244000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  16629791500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  17159035500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    529244000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  16629791500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  17159035500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       168802                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       168802                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        91476                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        91476                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       143394                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       143394                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        93525                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        93525                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        62101                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        93525                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       205495                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       299020                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        93525                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       205495                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       299020                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912060                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.912060                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.068506                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.068506                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.448624                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.448624                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.068506                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.772009                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.551973                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.068506                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.772009                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.551973                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106197.631209                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106197.631209                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82604.026846                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82604.026846                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98379.055994                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98379.055994                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82604.026846                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104824.585235                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 103962.020830                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82604.026846                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104824.585235                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 103962.020830                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  13894688000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  13894688000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    524890500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    524890500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2748099000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   2748099000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    524890500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  16642787000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  17167677500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    524890500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  16642787000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  17167677500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       168806                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       168806                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        90292                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        90292                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143391                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143391                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        92341                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        92341                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        62123                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        62123                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        92341                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       205514                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       297855                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        92341                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       205514                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       297855                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.912052                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.912052                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.069384                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.069384                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.448530                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.448530                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.069384                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771938                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.554132                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.069384                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771938                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.554132                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106244.746903                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106244.746903                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81924.535664                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81924.535664                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98625.430663                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98625.430663                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81924.535664                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104906.501349                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 104014.380404                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81924.535664                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104906.501349                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 104014.380404                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -942,123 +944,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       114413                       # number of writebacks
-system.cpu.l2cache.writebacks::total           114413                       # number of writebacks
-system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          112                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.CleanEvict_mshr_misses::total          112                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130784                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       130784                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks       114419                       # number of writebacks
+system.cpu.l2cache.writebacks::total           114419                       # number of writebacks
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          111                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.CleanEvict_mshr_misses::total          111                       # number of CleanEvict MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       130780                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       130780                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         6407                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total         6407                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27860                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27860                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        27864                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        27864                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         6407                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data       158644                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total       165051                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         6407                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       158644                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       165051                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12581111000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12581111000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    465184000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    465184000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2462240500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2462240500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    465184000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15043351500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  15508535500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    465184000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15043351500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  15508535500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  12586888000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  12586888000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    460830500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    460830500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2469459000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2469459000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    460830500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  15056347000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  15517177500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    460830500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  15056347000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  15517177500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912060                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912060                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.068506                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.448624                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.448624                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.772009                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.551973                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.068506                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.772009                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.551973                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96197.631209                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96197.631209                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72605.587639                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88379.055994                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88379.055994                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94824.585235                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 93962.081417                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72605.587639                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94824.585235                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93962.081417                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.912052                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.912052                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.069384                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.069384                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.448530                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.448530                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.069384                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771938                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.554132                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.069384                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771938                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.554132                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96244.746903                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96244.746903                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71926.096457                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71926.096457                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88625.430663                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88625.430663                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71926.096457                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94906.501349                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94014.440991                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71926.096457                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94906.501349                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94014.440991                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       591895                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       292875                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests       589565                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       291710                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         4047                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4047                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         4045                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         4045                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        155625                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       283215                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        91476                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        51263                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       143394                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       143394                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        93525                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        62101                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       278525                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612389                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            890914                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11840000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23955008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           35795008                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      133079                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       432099                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.009366                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.096323                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp        154463                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       283225                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        90292                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        51275                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       143391                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       143391                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        92341                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        62123                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       274973                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       612446                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            887419                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     11688448                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     23956480                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           35644928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      133082                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       430937                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.009387                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.096428                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             428052     99.06%     99.06% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               4047      0.94%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             426892     99.06%     99.06% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               4045      0.94%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         432099                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      556225500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         430937                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      553880500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          2.5                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     140299972                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     138521976                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.6                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     308258967                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     308281978                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              34266                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty       114413                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            14730                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            130784                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           130784                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         34266                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       459243                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 459243                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17885632                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                17885632                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              34270                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty       114419                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            14728                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            130780                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           130780                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         34270                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       459247                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 459247                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17886016                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                17886016                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            294193                       # Request fanout histogram
+system.membus.snoop_fanout::samples            294197                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  294193    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  294197    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              294193                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           777045500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              294197                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           776999500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          852834000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          852713250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.8                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
index 357735e21..ec22c8c38 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.056966                       # Number of seconds simulated
-sim_ticks                                 56966152500                       # Number of ticks simulated
-final_tick                                56966152500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.056803                       # Number of seconds simulated
+sim_ticks                                 56802974500                       # Number of ticks simulated
+final_tick                                56802974500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  83103                       # Simulator instruction rate (inst/s)
-host_op_rate                                   106277                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               66756773                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309512                       # Number of bytes of host memory used
-host_seconds                                   853.34                       # Real time elapsed on the host
+host_inst_rate                                 208655                       # Simulator instruction rate (inst/s)
+host_op_rate                                   266840                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              167132713                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 280072                       # Number of bytes of host memory used
+host_seconds                                   339.87                       # Real time elapsed on the host
 sim_insts                                    70915150                       # Number of instructions simulated
 sim_ops                                      90690106                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            285184                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            285504                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7924672                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              8209856                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       285184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          285184                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      5517504                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           5517504                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               4456                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total              8210176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       285504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          285504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      5517760                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           5517760                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               4461                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data             123823                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                128279                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           86211                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                86211                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              5006201                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            139111940                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               144118141                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         5006201                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            5006201                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          96855830                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               96855830                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          96855830                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             5006201                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           139111940                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              240973971                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        128279                       # Number of read requests accepted
-system.physmem.writeReqs                        86211                       # Number of write requests accepted
-system.physmem.readBursts                      128279                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      86211                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  8209472                       # Total number of bytes read from DRAM
+system.physmem.num_reads::total                128284                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           86215                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                86215                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst              5026216                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            139511567                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               144537783                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         5026216                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            5026216                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          97138575                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               97138575                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          97138575                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             5026216                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           139511567                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              241676358                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        128284                       # Number of read requests accepted
+system.physmem.writeReqs                        86215                       # Number of write requests accepted
+system.physmem.readBursts                      128284                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      86215                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  8209792                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                       384                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   5515584                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   8209856                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                5517504                       # Total written bytes from the system interface side
+system.physmem.bytesWritten                   5515904                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   8210176                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                5517760                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        6                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                8061                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                8314                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                8062                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                8315                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                8233                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                8140                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                8142                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                8284                       # Per bank write bursts
 system.physmem.perBankRdBursts::5                8403                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                8055                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                7915                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                7916                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                8035                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                7587                       # Per bank write bursts
 system.physmem.perBankRdBursts::10               7763                       # Per bank write bursts
@@ -64,16 +64,16 @@ system.physmem.perBankRdBursts::12               7871                       # Pe
 system.physmem.perBankRdBursts::13               7867                       # Per bank write bursts
 system.physmem.perBankRdBursts::14               7968                       # Per bank write bursts
 system.physmem.perBankRdBursts::15               7962                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5394                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5395                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                5541                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                5468                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                5335                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                5336                       # Per bank write bursts
 system.physmem.perBankWrBursts::4                5366                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                5559                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                5560                       # Per bank write bursts
 system.physmem.perBankWrBursts::6                5257                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5180                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5155                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                5101                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5179                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5154                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                5105                       # Per bank write bursts
 system.physmem.perBankWrBursts::10               5292                       # Per bank write bursts
 system.physmem.perBankWrBursts::11               5270                       # Per bank write bursts
 system.physmem.perBankWrBursts::12               5531                       # Per bank write bursts
@@ -82,24 +82,24 @@ system.physmem.perBankWrBursts::14               5703                       # Pe
 system.physmem.perBankWrBursts::15               5432                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     56966120500                       # Total gap between requests
+system.physmem.totGap                     56802942500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  128279                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  128284                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  86211                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                    116084                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     12167                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        22                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  86215                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                    116125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     12132                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        21                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,34 +144,34 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                      648                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                      663                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     4078                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     5185                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     5288                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     5314                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     5318                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5319                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                      631                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                      643                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     4122                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     5183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     5277                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     5318                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     5309                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5314                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::23                     5323                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     5324                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     5352                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     5373                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     5466                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     5451                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     5471                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     5868                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     5446                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     5300                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                        8                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     5321                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     5353                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     5383                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     5464                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     5436                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     5495                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     5851                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     5447                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     5305                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
@@ -193,102 +193,105 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        38803                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      353.679870                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     214.740030                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     335.847890                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          12299     31.70%     31.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         8268     21.31%     53.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4108     10.59%     63.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         2801      7.22%     70.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639         2598      6.70%     77.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         1655      4.27%     81.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         1337      3.45%     85.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         1145      2.95%     88.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4592     11.83%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          38803                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5292                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        24.235639                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      352.487123                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023           5289     99.94%     99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        38880                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      352.990947                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     214.489872                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     335.589979                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          12269     31.56%     31.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         8336     21.44%     53.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         4191     10.78%     63.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         2845      7.32%     71.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639         2490      6.40%     77.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         1681      4.32%     81.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         1302      3.35%     85.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         1149      2.96%     88.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4617     11.88%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          38880                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5294                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        24.227616                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      352.423208                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023           5291     99.94%     99.94% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::24576-25599            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5292                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5292                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.285147                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.266957                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        0.809216                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4635     87.59%     87.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                  6      0.11%     87.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                507      9.58%     97.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                117      2.21%     99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                 17      0.32%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                  4      0.08%     99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                  3      0.06%     99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.02%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5292                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     1670425750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                4075544500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    641365000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13022.43                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5294                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5294                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.279940                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.260845                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        0.856304                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4659     88.01%     88.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                  4      0.08%     88.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                483      9.12%     97.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                119      2.25%     99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                 16      0.30%     99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                  8      0.15%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                  3      0.06%     99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.02%     99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::42                  1      0.02%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5294                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     1681541750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                4086754250                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    641390000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13108.57                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  31772.43                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         144.11                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          96.82                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      144.12                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       96.86                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  31858.57                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         144.53                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          97.11                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      144.54                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       97.14                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           1.88                       # Data bus utilization in percentage
+system.physmem.busUtil                           1.89                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.13                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        23.35                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     111858                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     63787                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   87.20                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  73.99                       # Row buffer hit rate for writes
-system.physmem.avgGap                       265588.70                       # Average gap between requests
-system.physmem.pageHitRate                      81.89                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  152953920                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   83457000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 510065400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                279210240                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             3720624960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            11616680655                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            23988608250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              40351600425                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              708.364424                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    39782190750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1902160000                       # Time in different power states
+system.physmem.avgWrQLen                        23.24                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     111837                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     63741                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   87.18                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  73.93                       # Row buffer hit rate for writes
+system.physmem.avgGap                       264816.82                       # Average gap between requests
+system.physmem.pageHitRate                      81.86                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  153127800                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   83551875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 510073200                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                279223200                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             3709945200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            11545672905                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            23952789000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              40234383180                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              708.339923                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    39720213500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1896700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     15280128000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     15184054000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  140358960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                   76584750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy                  140767200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                   76807500                       # Energy for precharge commands per rank (pJ)
 system.physmem_1.readEnergy                 490315800                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                279138960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             3720624960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            10974085740                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            24552288000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              40233397170                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              706.289389                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    40717988750                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1902160000                       # Time in different power states
+system.physmem_1.writeEnergy                279158400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             3709945200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            11005773750                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            24426384750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              40129152600                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              706.487303                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    40510168000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1896700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     14344414250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     14394586000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                14806373                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           9910083                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            383814                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9538678                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 6734058                       # Number of BTB hits
+system.cpu.branchPred.lookups                14774616                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           9890616                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            339334                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9548677                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 6547888                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             70.597393                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1715002                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                  3                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             68.573772                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1714315                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                  4                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          174550                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             157999                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            16551                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        24800                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -407,97 +410,132 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        113932305                       # number of cpu cycles simulated
+system.cpu.numCycles                        113605949                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    70915150                       # Number of instructions committed
 system.cpu.committedOps                      90690106                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       1148486                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       1137741                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.606600                       # CPI: cycles per instruction
-system.cpu.ipc                               0.622432                       # IPC: instructions per cycle
-system.cpu.tickCycles                        95622082                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                        18310223                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements            156441                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4067.130215                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42625643                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            160537                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            265.519120                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         822760500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4067.130215                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.992952                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.992952                       # Average percentage of cache occupancy
+system.cpu.cpi                               1.601998                       # CPI: cycles per instruction
+system.cpu.ipc                               0.624220                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                47187979     52.03%     52.03% # Class of committed instruction
+system.cpu.op_class_0::IntMult                  80119      0.09%     52.12% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                7      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     52.12% # Class of committed instruction
+system.cpu.op_class_0::MemRead               22866262     25.21%     77.33% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              20555739     22.67%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                 90690106                       # Class of committed instruction
+system.cpu.tickCycles                        95311103                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                        18294846                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements            156448                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4067.225830                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            42620314                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            160544                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            265.474350                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         820768500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4067.225830                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.992975                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.992975                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           44                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1097                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2955                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1099                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2953                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          86019473                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         86019473                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22868200                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22868200                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     19642188                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       19642188                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        83417                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         83417                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          86009120                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         86009120                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22862903                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22862903                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19642172                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19642172                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        83401                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         83401                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      42510388                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         42510388                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     42593805                       # number of overall hits
-system.cpu.dcache.overall_hits::total        42593805                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        51522                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         51522                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       207713                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       207713                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        44590                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        44590                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data       259235                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         259235                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       303825                       # number of overall misses
-system.cpu.dcache.overall_misses::total        303825                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1488627000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1488627000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  16793358000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  16793358000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18281985000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18281985000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18281985000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18281985000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22919722                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22919722                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      42505075                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         42505075                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     42588476                       # number of overall hits
+system.cpu.dcache.overall_hits::total        42588476                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        51661                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         51661                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       207729                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       207729                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        44584                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        44584                       # number of SoftPFReq misses
+system.cpu.dcache.demand_misses::cpu.data       259390                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         259390                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       303974                       # number of overall misses
+system.cpu.dcache.overall_misses::total        303974                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1490194000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1490194000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  16811157000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  16811157000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  18301351000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  18301351000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  18301351000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  18301351000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22914564                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22914564                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128007                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128007                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       127985                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       127985                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42769623                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42769623                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42897630                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42897630                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002248                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.002248                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.010464                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.348340                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.348340                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.006061                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.006061                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007083                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007083                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28893.035985                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28893.035985                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80848.853948                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 80848.853948                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70522.826779                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70522.826779                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60172.747470                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60172.747470                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     42764465                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42764465                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42892450                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42892450                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002255                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.002255                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010465                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.010465                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.348353                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.348353                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006066                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.006066                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007087                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007087                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28845.628230                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 28845.628230                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80928.310443                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 80928.310443                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70555.345233                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70555.345233                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60206.961780                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -506,110 +544,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       128384                       # number of writebacks
-system.cpu.dcache.writebacks::total            128384                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22002                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        22002                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100685                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       100685                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       122687                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       122687                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       122687                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       122687                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29520                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        29520                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107028                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       107028                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23989                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        23989                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       136548                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       136548                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       160537                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       160537                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    575604000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    575604000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8480832000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8480832000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1713530500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1713530500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9056436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   9056436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10769966500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  10769966500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks       128389                       # number of writebacks
+system.cpu.dcache.writebacks::total            128389                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        22138                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        22138                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       100695                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       100695                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       122833                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       122833                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       122833                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       122833                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        29523                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        29523                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107034                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107034                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        23987                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        23987                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       136557                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       136557                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       160544                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       160544                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    578329500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    578329500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8490118500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8490118500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1713467500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1713467500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9068448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9068448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10781915500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10781915500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001288                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187404                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187404                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.187420                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.187420                       # mshr miss rate for SoftPFReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003193                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.003193                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.003742                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19498.780488                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19498.780488                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79239.376612                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79239.376612                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71429.842845                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71429.842845                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66324.193690                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 66324.193690                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67087.129447                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 67087.129447                       # average overall mshr miss latency
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003743                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.003743                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19589.116960                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19589.116960                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             42871                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1852.494475                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            24951243                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             44913                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs            555.546123                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             43497                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1852.676989                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            24844377                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             45539                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs            545.562639                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1852.494475                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.904538                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.904538                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1852.676989                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.904627                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.904627                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2042                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           76                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           44                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          917                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           46                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          915                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1005                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.997070                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          50037227                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         50037227                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     24951243                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24951243                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      24951243                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         24951243                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     24951243                       # number of overall hits
-system.cpu.icache.overall_hits::total        24951243                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        44914                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         44914                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        44914                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          44914                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        44914                       # number of overall misses
-system.cpu.icache.overall_misses::total         44914                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    896931500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    896931500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    896931500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    896931500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    896931500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    896931500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     24996157                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     24996157                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     24996157                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     24996157                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     24996157                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     24996157                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001797                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001797                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001797                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001797                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001797                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001797                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19969.975954                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19969.975954                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19969.975954                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19969.975954                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19969.975954                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19969.975954                       # average overall miss latency
+system.cpu.icache.tags.tag_accesses          49825373                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         49825373                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     24844377                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        24844377                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      24844377                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         24844377                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     24844377                       # number of overall hits
+system.cpu.icache.overall_hits::total        24844377                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        45540                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         45540                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        45540                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          45540                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        45540                       # number of overall misses
+system.cpu.icache.overall_misses::total         45540                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    905103000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    905103000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    905103000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    905103000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    905103000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    905103000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     24889917                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     24889917                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     24889917                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     24889917                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     24889917                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     24889917                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001830                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001830                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001830                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001830                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001830                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001830                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19874.901186                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 19874.901186                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 19874.901186                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 19874.901186                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 19874.901186                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -618,135 +656,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        42871                       # number of writebacks
-system.cpu.icache.writebacks::total             42871                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        44914                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        44914                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        44914                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        44914                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        44914                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        44914                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    852018500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    852018500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    852018500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    852018500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    852018500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    852018500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001797                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001797                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001797                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001797                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18969.998219                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18969.998219                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18969.998219                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 18969.998219                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18969.998219                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 18969.998219                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        43497                       # number of writebacks
+system.cpu.icache.writebacks::total             43497                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        45540                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        45540                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        45540                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        45540                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        45540                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        45540                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    859564000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    859564000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    859564000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    859564000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    859564000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    859564000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001830                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001830                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001830                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001830                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001830                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001830                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements            96387                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        29871.556792                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             162176                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           127540                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.271570                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements            96391                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        29870.997301                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             163417                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           127542                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.281280                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 26781.739932                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1431.627084                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1658.189777                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.817314                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043690                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.050604                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.911608                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        31153                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1433.103835                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1656.072920                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.817316                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.043735                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.050539                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.911590                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        31151                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          191                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1857                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12727                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        15784                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          594                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.950714                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3410152                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3410152                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       128384                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       128384                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        39291                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        39291                       # number of WritebackClean hits
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1859                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12725                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        15781                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          595                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.950653                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3420152                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3420152                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       128389                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       128389                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        39908                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        39908                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data         4752                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total         4752                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        40444                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        40444                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        31900                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        31900                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        40444                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        36652                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           77096                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        40444                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        36652                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          77096                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       102276                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       102276                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         4470                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         4470                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        21609                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        21609                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         4470                       # number of demand (read+write) misses
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        41065                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        41065                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        31907                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        31907                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        41065                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        36659                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           77724                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        41065                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        36659                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          77724                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       102282                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       102282                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         4475                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         4475                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        21603                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        21603                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         4475                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data       123885                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        128355                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         4470                       # number of overall misses
+system.cpu.l2cache.demand_misses::total        128360                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         4475                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       123885                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       128355                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8270346500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   8270346500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    356128000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    356128000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1869505500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   1869505500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    356128000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  10139852000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  10495980000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    356128000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  10139852000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  10495980000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       128384                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       128384                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        39291                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        39291                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       107028                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       107028                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        44914                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        44914                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        53509                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        53509                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        44914                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       160537                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       205451                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        44914                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       160537                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       205451                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955600                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.955600                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.099524                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.099524                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.403839                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.403839                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.099524                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.771691                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.624748                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.099524                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.771691                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.624748                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80863.022605                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80863.022605                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79670.693512                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79670.693512                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86515.132584                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86515.132584                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79670.693512                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81848.908262                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81773.051303                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79670.693512                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81848.908262                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81773.051303                       # average overall miss latency
+system.cpu.l2cache.overall_misses::total       128360                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8279623500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8279623500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    356201500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    356201500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   1872087500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   1872087500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    356201500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  10151711000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  10507912500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    356201500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  10151711000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  10507912500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       128389                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       128389                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        39908                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        39908                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       107034                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       107034                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        45540                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        45540                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        53510                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        53510                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        45540                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       160544                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       206084                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        45540                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       160544                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       206084                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955603                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.955603                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.098265                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.098265                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.403719                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.403719                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.098265                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.771658                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.622853                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.098265                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.771658                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.622853                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80948.979293                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80948.979293                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79598.100559                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79598.100559                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86658.681665                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86658.681665                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79598.100559                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81944.634136                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81862.827205                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79598.100559                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -755,8 +793,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        86211                       # number of writebacks
-system.cpu.l2cache.writebacks::total            86211                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks        86215                       # number of writebacks
+system.cpu.l2cache.writebacks::total            86215                       # number of writebacks
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           13                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total           13                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           62                       # number of ReadSharedReq MSHR hits
@@ -769,119 +807,119 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data           62
 system.cpu.l2cache.overall_mshr_hits::total           75                       # number of overall MSHR hits
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks           96                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total           96                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102276                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       102276                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         4457                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         4457                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        21547                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        21547                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         4457                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102282                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102282                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         4462                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         4462                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        21541                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        21541                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         4462                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data       123823                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       128280                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         4457                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       128285                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         4462                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       123823                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       128280                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7247586500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7247586500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    310540000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    310540000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1649696000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1649696000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    310540000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8897282500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   9207822500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    310540000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8897282500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total   9207822500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total       128285                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7256803500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7256803500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    310457000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    310457000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   1652012000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   1652012000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    310457000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8908815500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9219272500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    310457000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8908815500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9219272500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955600                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955600                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.099234                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.099234                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.402680                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.402680                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.099234                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771305                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.624382                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.099234                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771305                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.624382                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70863.022605                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70863.022605                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69674.669060                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69674.669060                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76562.676939                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76562.676939                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69674.669060                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71854.845223                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71779.096508                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69674.669060                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71854.845223                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71779.096508                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955603                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955603                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.097980                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.097980                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.402560                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.402560                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.097980                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.771271                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.622489                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.097980                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.771271                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.622489                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70948.979293                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70948.979293                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69577.991932                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69577.991932                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       404763                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       199348                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7815                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         3362                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3333                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests       406029                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       199980                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests         7832                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         3359                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3330                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           29                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         98422                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       214595                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        42871                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        38233                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       107028                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       107028                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        44914                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        53509                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       132698                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       477515                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            610213                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5618176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18490944                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           24109120                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       96387                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       301838                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.037245                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.189869                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp         99049                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       214604                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        43497                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        38235                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       107034                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       107034                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        45540                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        53510                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       134576                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       477536                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            612112                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      5698304                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18491712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           24190016                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       96391                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       302475                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.037210                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.189781                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             290625     96.29%     96.29% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              11184      3.71%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             291249     96.29%     96.29% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              11197      3.70%     99.99% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                 29      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         301838                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      373636500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         302475                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      374900500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.7                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      67388961                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      68328959                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     240839931                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     240850431                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.4                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              26003                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        86211                       # Transaction distribution
-system.membus.trans_dist::CleanEvict             6909                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            102276                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           102276                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         26003                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       349678                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 349678                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13727360                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                13727360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              26002                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        86215                       # Transaction distribution
+system.membus.trans_dist::CleanEvict             6912                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            102282                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           102282                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         26002                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       349695                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 349695                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13727936                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                13727936                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            221399                       # Request fanout histogram
+system.membus.snoop_fanout::samples            221411                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  221399    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  221411    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              221399                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           590619000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              221411                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           590704500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          676896750                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy          676958000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.2                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 7ec2ce465..5ae3909df 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,119 +1,119 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.033709                       # Number of seconds simulated
-sim_ticks                                 33708718000                       # Number of ticks simulated
-final_tick                                33708718000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.033525                       # Number of seconds simulated
+sim_ticks                                 33524756000                       # Number of ticks simulated
+final_tick                                33524756000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  58097                       # Simulator instruction rate (inst/s)
-host_op_rate                                    74299                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               27618733                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 312228                       # Number of bytes of host memory used
-host_seconds                                  1220.50                       # Real time elapsed on the host
+host_inst_rate                                 145211                       # Simulator instruction rate (inst/s)
+host_op_rate                                   185708                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               68655135                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 282260                       # Number of bytes of host memory used
+host_seconds                                   488.31                       # Real time elapsed on the host
 sim_insts                                    70907652                       # Number of instructions simulated
 sim_ops                                      90682607                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            642112                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           2851904                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher      6180288                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              9674304                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       642112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          642112                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      6216192                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6216192                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              10033                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              44561                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher        96567                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                151161                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           97128                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                97128                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             19048841                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             84604345                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher    183343905                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               286997091                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        19048841                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           19048841                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         184409030                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              184409030                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         184409030                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            19048841                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            84604345                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher    183343905                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              471406121                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                        151162                       # Number of read requests accepted
-system.physmem.writeReqs                        97128                       # Number of write requests accepted
-system.physmem.readBursts                      151162                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                      97128                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                  9665216                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                      9152                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                   6214528                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                   9674368                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys                6216192                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                      143                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst            697984                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           2927552                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher      6172096                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              9797632                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       697984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          697984                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      6216960                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6216960                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              10906                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              45743                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher        96439                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                153088                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           97140                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                97140                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst             20819958                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             87325080                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher    184105620                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               292250658                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        20819958                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           20819958                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         185443855                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              185443855                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         185443855                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            20819958                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            87325080                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher    184105620                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              477694513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                        153089                       # Number of read requests accepted
+system.physmem.writeReqs                        97140                       # Number of write requests accepted
+system.physmem.readBursts                      153089                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                      97140                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                  9788224                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                      9472                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                   6215872                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                   9797696                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys                6216960                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                      148                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                9070                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                9361                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                9561                       # Per bank write bursts
-system.physmem.perBankRdBursts::3               11292                       # Per bank write bursts
-system.physmem.perBankRdBursts::4               10590                       # Per bank write bursts
-system.physmem.perBankRdBursts::5               10416                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                9949                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                8975                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                9423                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                9187                       # Per bank write bursts
-system.physmem.perBankRdBursts::10               9162                       # Per bank write bursts
-system.physmem.perBankRdBursts::11               8879                       # Per bank write bursts
-system.physmem.perBankRdBursts::12               8652                       # Per bank write bursts
-system.physmem.perBankRdBursts::13               8689                       # Per bank write bursts
-system.physmem.perBankRdBursts::14               8733                       # Per bank write bursts
-system.physmem.perBankRdBursts::15               9080                       # Per bank write bursts
-system.physmem.perBankWrBursts::0                5971                       # Per bank write bursts
-system.physmem.perBankWrBursts::1                6177                       # Per bank write bursts
-system.physmem.perBankWrBursts::2                6109                       # Per bank write bursts
-system.physmem.perBankWrBursts::3                6172                       # Per bank write bursts
-system.physmem.perBankWrBursts::4                6049                       # Per bank write bursts
-system.physmem.perBankWrBursts::5                6259                       # Per bank write bursts
-system.physmem.perBankWrBursts::6                6017                       # Per bank write bursts
-system.physmem.perBankWrBursts::7                5953                       # Per bank write bursts
-system.physmem.perBankWrBursts::8                5939                       # Per bank write bursts
-system.physmem.perBankWrBursts::9                6100                       # Per bank write bursts
-system.physmem.perBankWrBursts::10               6208                       # Per bank write bursts
-system.physmem.perBankWrBursts::11               5866                       # Per bank write bursts
-system.physmem.perBankWrBursts::12               6052                       # Per bank write bursts
-system.physmem.perBankWrBursts::13               6067                       # Per bank write bursts
-system.physmem.perBankWrBursts::14               6159                       # Per bank write bursts
-system.physmem.perBankWrBursts::15               6004                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                9103                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                9407                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                9452                       # Per bank write bursts
+system.physmem.perBankRdBursts::3               11458                       # Per bank write bursts
+system.physmem.perBankRdBursts::4               10748                       # Per bank write bursts
+system.physmem.perBankRdBursts::5               11390                       # Per bank write bursts
+system.physmem.perBankRdBursts::6               10031                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                8920                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                9321                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                9437                       # Per bank write bursts
+system.physmem.perBankRdBursts::10               9070                       # Per bank write bursts
+system.physmem.perBankRdBursts::11               9080                       # Per bank write bursts
+system.physmem.perBankRdBursts::12               8731                       # Per bank write bursts
+system.physmem.perBankRdBursts::13               8724                       # Per bank write bursts
+system.physmem.perBankRdBursts::14               9025                       # Per bank write bursts
+system.physmem.perBankRdBursts::15               9044                       # Per bank write bursts
+system.physmem.perBankWrBursts::0                5968                       # Per bank write bursts
+system.physmem.perBankWrBursts::1                6230                       # Per bank write bursts
+system.physmem.perBankWrBursts::2                6083                       # Per bank write bursts
+system.physmem.perBankWrBursts::3                6155                       # Per bank write bursts
+system.physmem.perBankWrBursts::4                6058                       # Per bank write bursts
+system.physmem.perBankWrBursts::5                6286                       # Per bank write bursts
+system.physmem.perBankWrBursts::6                6021                       # Per bank write bursts
+system.physmem.perBankWrBursts::7                5958                       # Per bank write bursts
+system.physmem.perBankWrBursts::8                5969                       # Per bank write bursts
+system.physmem.perBankWrBursts::9                6064                       # Per bank write bursts
+system.physmem.perBankWrBursts::10               6185                       # Per bank write bursts
+system.physmem.perBankWrBursts::11               5907                       # Per bank write bursts
+system.physmem.perBankWrBursts::12               6058                       # Per bank write bursts
+system.physmem.perBankWrBursts::13               6089                       # Per bank write bursts
+system.physmem.perBankWrBursts::14               6121                       # Per bank write bursts
+system.physmem.perBankWrBursts::15               5971                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     33708706500                       # Total gap between requests
+system.physmem.totGap                     33524744500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                  151162                       # Read request sizes (log2)
+system.physmem.readPktSize::6                  153089                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                  97128                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     48274                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                     54259                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     13865                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     10322                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                      6132                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                      5295                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                      4724                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                      4390                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                      3645                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                        73                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                  97140                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                     50282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                     54410                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     13705                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     10264                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                      6125                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                      5282                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                      4726                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                      4368                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                      3666                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                        71                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                       33                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                        6                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                        7                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                        2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
@@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                     1199                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                     1243                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                     1720                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                     2271                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                     2935                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                     3759                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                     4746                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                     5409                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                     5932                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                     6426                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                     6856                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                     7461                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                     8097                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                     8693                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                     9095                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                     7779                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                     6737                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                     6264                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      232                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                      117                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       50                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                       30                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                       23                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       16                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       10                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                        7                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        6                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                     1229                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                     1284                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                     1769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                     2313                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                     2958                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                     3844                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                     4769                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                     5371                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                     5945                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                     6375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                     6905                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                     7468                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                     8082                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                     8760                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                     9125                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                     7620                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                     6645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                     6222                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      195                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       85                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       63                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                       40                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                       13                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       10                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        8                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42                        4                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
@@ -197,104 +197,104 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples        94915                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      167.290734                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     105.391717                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     236.347458                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127          59184     62.35%     62.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255        22349     23.55%     85.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383         4070      4.29%     90.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511         1460      1.54%     91.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639          942      0.99%     92.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767          824      0.87%     93.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895          583      0.61%     94.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023          753      0.79%     95.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151         4750      5.00%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total          94915                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples          5848                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        25.821990                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      198.480384                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511            5847     99.98%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples        96335                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      166.118316                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     104.810468                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     234.858667                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127          60546     62.85%     62.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255        22368     23.22%     86.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383         3987      4.14%     90.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511         1542      1.60%     91.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639          931      0.97%     92.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767          863      0.90%     93.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895          636      0.66%     94.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023          773      0.80%     95.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151         4689      4.87%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total          96335                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples          5845                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        26.165269                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      198.412430                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511            5844     99.98%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14848-15359            1      0.02%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total            5848                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples          5848                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.604309                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.557483                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.326112                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16               4590     78.49%     78.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17                 34      0.58%     79.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18                732     12.52%     91.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19                206      3.52%     95.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                140      2.39%     97.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 85      1.45%     98.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 32      0.55%     99.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 13      0.22%     99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  5      0.09%     99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                  7      0.12%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  1      0.02%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  1      0.02%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  1      0.02%     99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30                  1      0.02%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total            5848                       # Writes before turning the bus around for reads
-system.physmem.totQLat                     6766168330                       # Total ticks spent queuing
-system.physmem.totMemAccLat                9597774580                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                    755095000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       44803.42                       # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total            5845                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples          5845                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.616424                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.570046                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.313075                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16               4545     77.76%     77.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17                 48      0.82%     78.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18                753     12.88%     91.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19                215      3.68%     95.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                127      2.17%     97.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 88      1.51%     98.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 42      0.72%     99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 17      0.29%     99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  5      0.09%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  5      0.09%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total            5845                       # Writes before turning the bus around for reads
+system.physmem.totQLat                     6714977565                       # Total ticks spent queuing
+system.physmem.totMemAccLat                9582621315                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                    764705000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       43905.67                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  63553.42                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         286.73                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         184.36                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      287.00                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      184.41                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  62655.67                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         291.97                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         185.41                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      292.25                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      185.44                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil                           3.68                       # Data bus utilization in percentage
-system.physmem.busUtilRead                       2.24                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.44                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.45                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.44                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     120218                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                     32977                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.60                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  33.95                       # Row buffer hit rate for writes
-system.physmem.avgGap                       135763.45                       # Average gap between requests
-system.physmem.pageHitRate                      61.74                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                  372428280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                  203209875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                 617682000                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy                315563040                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             2201556240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            14512366440                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy             7494015750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              25716821625                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              762.953400                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    12364292410                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      1125540000                       # Time in different power states
+system.physmem.busUtil                           3.73                       # Data bus utilization in percentage
+system.physmem.busUtilRead                       2.28                       # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite                      1.45                       # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen                         1.43                       # Average read queue length when enqueuing
+system.physmem.avgWrQLen                        24.45                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     120882                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                     32837                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   79.04                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  33.80                       # Row buffer hit rate for writes
+system.physmem.avgGap                       133976.26                       # Average gap between requests
+system.physmem.pageHitRate                      61.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                  378438480                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                  206489250                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                 627572400                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy                315854640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy             2189350800                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            15155251200                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy             6817959750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              25690916520                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              766.433942                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    11238384768                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      1119300000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     20217117590                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     21162395232                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                  345038400                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                  188265000                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                 559977600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy                313554240                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             2201556240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy            13559944320                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy             8329473750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              25497809550                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              756.455863                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    13760038430                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      1125540000                       # Time in different power states
+system.physmem_1.actEnergy                  349513920                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                  190707000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                 564751200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy                313295040                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy             2189350800                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy            13737724470                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy             8061404250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              25406746680                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              757.956338                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    13314860915                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      1119300000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT     18821462070                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT     19085999585                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                17213709                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11523003                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            650148                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              9341134                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7678896                       # Number of BTB hits
+system.cpu.branchPred.lookups                17055826                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11447804                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            598855                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              9258903                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7371283                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             82.205180                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1872990                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             101556                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             79.612920                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1853216                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             101575                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          232758                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             195217                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            37541                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        22230                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -413,232 +413,232 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                         67417437                       # number of cpu cycles simulated
+system.cpu.numCycles                         67049513                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5107349                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       88247579                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    17213709                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9551886                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      60722717                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1326923                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 4938                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles            27                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles        12869                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  22781060                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 69770                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           66511361                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.678949                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.300919                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles            5112037                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       87027076                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    17055826                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9419716                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      60300614                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1224115                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 5977                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles            37                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles        12656                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  22418203                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 68072                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           66043378                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.665685                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.303820                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 20706181     31.13%     31.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  8267608     12.43%     43.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  9211127     13.85%     57.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 28326445     42.59%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 20904696     31.65%     31.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  8151419     12.34%     44.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  9105743     13.79%     57.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 27881520     42.22%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             66511361                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.255330                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.308973                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                  8663293                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              20135580                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  31585821                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               5633203                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 493464                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              3182521                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                171963                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              101430430                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts               3050546                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 493464                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13424917                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 5969682                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         834240                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  32240480                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              13548578                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               99223336                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts                980873                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3826325                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                  67087                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                4382425                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                5163178                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           103933922                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             457817395                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        115439825                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             66043378                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.254377                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.297952                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                  8568047                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              20331818                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  31035970                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               5662045                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 445498                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              3138719                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                168392                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              100377883                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts               2807284                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 445498                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13201972                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 6021135                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         843957                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  31848304                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              13682512                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               98401933                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts                864722                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3910657                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                  69359                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4461482                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                5194138                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           103316551                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             453881397                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        114363596                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               706                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              93629369                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 10304553                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              18670                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          18666                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12721444                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             24327620                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            22002844                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1418421                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2362163                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   98185716                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               34529                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  94914966                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            694952                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7537638                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     20282691                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            743                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      66511361                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.427049                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.152183                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                  9687182                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              18952                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          18977                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12759909                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             24172969                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            21779154                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1438398                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2287665                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   97467378                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               34812                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  94518121                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            609879                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         6819583                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     18149075                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1026                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      66043378                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.431152                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.152558                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            18195190     27.36%     27.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            17483152     26.29%     53.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            17116175     25.73%     79.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            11668879     17.54%     96.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2046998      3.08%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 967      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            17971444     27.21%     27.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17366377     26.30%     53.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            17018277     25.77%     79.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            11635318     17.62%     96.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2050574      3.10%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                1388      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        66511361                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        66043378                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 6715190     22.43%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                     42      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               11181767     37.35%     59.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              12039186     40.22%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 6745698     22.64%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                     37      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               11091756     37.22%     59.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              11960162     40.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              49504183     52.16%     52.16% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                89872      0.09%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               1      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              8      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24074068     25.36%     77.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            21246803     22.39%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              49324075     52.18%     52.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                86626      0.09%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                  32      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               6      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc             12      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             23968009     25.36%     77.63% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            21139361     22.37%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               94914966                       # Type of FU issued
-system.cpu.iq.rate                           1.407870                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    29936185                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.315400                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          286972221                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         105769455                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     93478190                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 209                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           59                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              124851032                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     119                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1366282                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               94518121                       # Type of FU issued
+system.cpu.iq.rate                           1.409676                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    29797653                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.315259                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          285486823                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         104332871                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     93229184                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 329                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                574                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           84                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              124315586                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     188                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1381077                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1461358                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2098                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        12063                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1447106                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1306707                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2085                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        11900                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1223416                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads       140885                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        185939                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads       147221                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        186554                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 493464                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  630348                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                519071                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            98230120                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                 445498                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  578203                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                566637                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            97517928                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              24327620                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             22002844                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              18609                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1657                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                514382                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          12063                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         303781                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       221600                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               525381                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              93994405                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              23766194                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            920561                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              24172969                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             21779154                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              18892                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1555                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                562180                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          11900                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         250835                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       223196                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               474031                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              93719339                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              23701905                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            798782                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          9875                       # number of nop insts executed
-system.cpu.iew.exec_refs                     44755394                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14253394                       # Number of branches executed
-system.cpu.iew.exec_stores                   20989200                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.394215                       # Inst execution rate
-system.cpu.iew.wb_sent                       93600457                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      93478249                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  44984526                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  76573166                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.386559                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.587471                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts         6555355                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         15738                       # number of nop insts executed
+system.cpu.iew.exec_refs                     44631646                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14212084                       # Number of branches executed
+system.cpu.iew.exec_stores                   20929741                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.397763                       # Inst execution rate
+system.cpu.iew.wb_sent                       93338125                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      93229268                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  44994314                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  76693481                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.390454                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.586677                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts         5957514                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            480151                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     65449475                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.385621                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.157530                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            432296                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     65078464                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.393520                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.163869                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     31837500     48.64%     48.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     16816023     25.69%     74.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4347616      6.64%     80.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      4166544      6.37%     87.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1933514      2.95%     90.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1257718      1.92%     92.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       744905      1.14%     93.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       580044      0.89%     94.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3765611      5.75%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     31565690     48.50%     48.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     16713735     25.68%     74.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4316875      6.63%     80.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      4188712      6.44%     87.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1942227      2.98%     90.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1235606      1.90%     92.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       754913      1.16%     93.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       587526      0.90%     94.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3773180      5.80%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     65449475                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     65078464                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             70913204                       # Number of instructions committed
 system.cpu.commit.committedOps               90688159                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -684,388 +684,386 @@ system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          90688159                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3765611                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    158902079                       # The number of ROB reads
-system.cpu.rob.rob_writes                   195550630                       # The number of ROB writes
-system.cpu.timesIdled                           26501                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          906076                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3773180                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    157925658                       # The number of ROB reads
+system.cpu.rob.rob_writes                   194257744                       # The number of ROB writes
+system.cpu.timesIdled                           27177                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                         1006135                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    70907652                       # Number of Instructions Simulated
 system.cpu.committedOps                      90682607                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.950778                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.950778                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.051770                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.051770                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                102290676                       # number of integer regfile reads
-system.cpu.int_regfile_writes                56801575                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        38                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       22                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 346161860                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 38808202                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                44217642                       # number of misc regfile reads
+system.cpu.cpi                               0.945589                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.945589                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.057542                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.057542                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                102008139                       # number of integer regfile reads
+system.cpu.int_regfile_writes                56630693                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        48                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       42                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 345209533                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 38766867                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                44112766                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements            485010                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           510.749644                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40413326                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs            485522                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             83.236858                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         153371500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   510.749644                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997558                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997558                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            486293                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           510.756058                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40330532                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            486805                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             82.847407                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         150823500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   510.756058                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997570                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997570                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          456                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          84616114                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         84616114                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     21490425                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        21490425                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18831304                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18831304                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data        60283                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total         60283                       # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data        15350                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total        15350                       # number of LoadLockedReq hits
+system.cpu.dcache.tags.tag_accesses          84456645                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         84456645                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     21406566                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21406566                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18832689                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18832689                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data        59994                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total         59994                       # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15306                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15306                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40321729                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40321729                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40382012                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40382012                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       564289                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        564289                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1018597                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1018597                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data        68553                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total        68553                       # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data          576                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total          576                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1582886                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1582886                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1651439                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1651439                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   9271463500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   9271463500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  14268416431                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  14268416431                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5543500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      5543500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  23539879931                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  23539879931                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  23539879931                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  23539879931                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22054714                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22054714                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data      40239255                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40239255                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40299249                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40299249                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       567937                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        567937                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1017212                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1017212                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data        68679                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total        68679                       # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data          618                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total          618                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1585149                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1585149                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1653828                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1653828                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   9485185000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   9485185000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  14264451930                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  14264451930                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5633500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      5633500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  23749636930                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  23749636930                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  23749636930                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  23749636930                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     21974503                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     21974503                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data       128836                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total       128836                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data       128673                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total       128673                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15924                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        15924                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41904615                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41904615                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42033451                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42033451                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025586                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.025586                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051315                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.051315                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532095                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.532095                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036167                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036167                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037774                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037774                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.039289                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.039289                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16430.345975                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 16430.345975                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14007.911304                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 14007.911304                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9624.131944                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9624.131944                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14871.494176                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14871.494176                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14254.162540                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14254.162540                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs           63                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      2905402                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets          131245                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.727273                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    22.137240                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     41824404                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41824404                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41953077                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41953077                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025845                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.025845                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051245                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.051245                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.533748                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.533748                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.038809                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.038809                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037900                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037900                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.039421                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.039421                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9115.695793                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9115.695793                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14982.589605                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14360.403216                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs           48                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      2907482                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 6                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets          131418                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs            8                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    22.123925                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       485010                       # number of writebacks
-system.cpu.dcache.writebacks::total            485010                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       264882                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       264882                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870061                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       870061                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          576                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total          576                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1134943                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1134943                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1134943                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1134943                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299407                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       299407                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148536                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       148536                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37590                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total        37590                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       447943                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       447943                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       485533                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       485533                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3623952500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   3623952500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2306335972                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   2306335972                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1883780500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1883780500                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5930288472                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   5930288472                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7814068972                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7814068972                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013576                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013576                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291766                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291766                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010690                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.010690                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011551                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.011551                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12103.766779                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12103.766779                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15527.117817                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15527.117817                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50113.873371                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50113.873371                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13238.935472                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13238.935472                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16093.795833                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16093.795833                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       486293                       # number of writebacks
+system.cpu.dcache.writebacks::total            486293                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       267392                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       267392                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       868636                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       868636                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          618                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total          618                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1136028                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1136028                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1136028                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1136028                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       300545                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       300545                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148576                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       148576                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37700                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total        37700                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       449121                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       449121                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       486821                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       486821                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3693304500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3693304500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2308719470                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2308719470                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1888982500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1888982500                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6002023970                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6002023970                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7891006470                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7891006470                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013677                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013677                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007485                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007485                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.292991                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.292991                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010738                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.010738                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011604                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.011604                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12288.690546                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12288.690546                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements            322968                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.276903                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22446876                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs            323480                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs             69.391851                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle        1134274500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.276903                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.996635                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.996635                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            325000                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.229072                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22083387                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            325512                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             67.842006                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        1115028500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.229072                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.996541                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.996541                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           88                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2           21                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          338                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           85                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           63                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          320                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45885393                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45885393                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22446876                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22446876                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22446876                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22446876                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22446876                       # number of overall hits
-system.cpu.icache.overall_hits::total        22446876                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       334075                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        334075                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       334075                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         334075                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       334075                       # number of overall misses
-system.cpu.icache.overall_misses::total        334075                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   3448429403                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   3448429403                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   3448429403                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   3448429403                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   3448429403                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   3448429403                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22780951                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22780951                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22780951                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22780951                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22780951                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22780951                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014665                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.014665                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.014665                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.014665                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.014665                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.014665                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10322.321045                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 10322.321045                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 10322.321045                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 10322.321045                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 10322.321045                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 10322.321045                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs       262312                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets           50                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs             16368                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses          45161716                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45161716                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22083387                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22083387                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22083387                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22083387                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22083387                       # number of overall hits
+system.cpu.icache.overall_hits::total        22083387                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       334707                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        334707                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       334707                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         334707                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       334707                       # number of overall misses
+system.cpu.icache.overall_misses::total        334707                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   3526570179                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   3526570179                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   3526570179                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   3526570179                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   3526570179                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   3526570179                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22418094                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22418094                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22418094                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22418094                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22418094                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22418094                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014930                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.014930                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014930                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.014930                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014930                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.014930                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10536.290484                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 10536.290484                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 10536.290484                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 10536.290484                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 10536.290484                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs       264177                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets           49                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs             16495                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    16.025904                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets           25                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    16.015580                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    24.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks       322968                       # number of writebacks
-system.cpu.icache.writebacks::total            322968                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10583                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        10583                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        10583                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        10583                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        10583                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        10583                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323492                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       323492                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       323492                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       323492                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       323492                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       323492                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3173672438                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   3173672438                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3173672438                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   3173672438                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3173672438                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   3173672438                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014200                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.014200                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014200                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.014200                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9810.667460                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9810.667460                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9810.667460                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  9810.667460                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9810.667460                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  9810.667460                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks       325000                       # number of writebacks
+system.cpu.icache.writebacks::total            325000                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         9178                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         9178                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         9178                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         9178                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         9178                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         9178                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       325529                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       325529                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       325529                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       325529                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       325529                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       325529                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3259633220                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   3259633220                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3259633220                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   3259633220                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3259633220                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   3259633220                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014521                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014521                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014521                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.014521                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014521                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.014521                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued       822850                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified       826406                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit         3117                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued       822902                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified       826054                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit         2760                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage        78938                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements           127914                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        15989.309751                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs            1181667                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs           144275                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             8.190379                       # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfSpanPage        78906                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements           128177                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        15989.063291                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1184574                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           144531                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             8.195986                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15893.511070                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    95.798681                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.970063                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.005847                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.975910                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022           28                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        16333                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2            1                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3           12                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4            7                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2736                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12138                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          528                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4          795                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001709                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996887                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses         24987971                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses        24987971                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks       259400                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total       259400                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks       468713                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total       468713                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       137243                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       137243                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       313417                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total       313417                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data       300447                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total       300447                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst       313417                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       437690                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          751107                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst       313417                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       437690                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         751107                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data           10                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total           10                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        11329                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        11329                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10064                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total        10064                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data        36503                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total        36503                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst        10064                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        47832                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         57896                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst        10064                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        47832                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        57896                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1187627500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   1187627500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    761841000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    761841000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2998033500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total   2998033500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    761841000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   4185661000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   4947502000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    761841000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   4185661000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   4947502000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks       259400                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total       259400                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks       468713                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total       468713                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data           11                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total           11                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       148572                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       148572                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       323481                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total       323481                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336950                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total       336950                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst       323481                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       485522                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       809003                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst       323481                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       485522                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       809003                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.909091                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.909091                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076253                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.076253                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.031112                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.031112                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.108334                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.108334                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.031112                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.098517                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.071565                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.031112                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.098517                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.071565                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104830.744108                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104830.744108                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75699.622417                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75699.622417                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82131.153604                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82131.153604                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75699.622417                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87507.547249                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 85454.988255                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75699.622417                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87507.547249                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 85454.988255                       # average overall miss latency
+system.cpu.l2cache.tags.occ_blocks::writebacks 15883.544788                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   105.518503                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.969455                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006440                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.975895                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022           30                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        16324                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1            7                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2            3                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3           14                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4            6                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          124                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2742                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12115                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          553                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4          790                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001831                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.996338                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         25089114                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        25089114                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks       260314                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total       260314                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks       470737                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total       470737                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       137093                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       137093                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       314576                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total       314576                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data       300687                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total       300687                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       314576                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       437780                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          752356                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       314576                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       437780                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         752356                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           16                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           16                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        11519                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        11519                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        10935                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total        10935                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data        37506                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total        37506                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        10935                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        49025                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         59960                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        10935                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        49025                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        59960                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1190791000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1190791000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    838826500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    838826500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   3069049000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total   3069049000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    838826500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4259840000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   5098666500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    838826500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4259840000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   5098666500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks       260314                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total       260314                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks       470737                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total       470737                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       148612                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       148612                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       325511                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total       325511                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       338193                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total       338193                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       325511                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       486805                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       812316                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       325511                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       486805                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       812316                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.077511                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.077511                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.033593                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.033593                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.110901                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.110901                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.033593                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.100708                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.073814                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.033593                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.100708                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.073814                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103376.247938                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103376.247938                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76710.242341                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76710.242341                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81828.214152                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81828.214152                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76710.242341                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86891.177970                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 85034.464643                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76710.242341                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86891.177970                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 85034.464643                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1074,155 +1072,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks        97128                       # number of writebacks
-system.cpu.l2cache.writebacks::total            97128                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3171                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         3171                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           30                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total           30                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.unused_prefetches              424                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks        97140                       # number of writebacks
+system.cpu.l2cache.writebacks::total            97140                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3182                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         3182                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           28                       # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total           28                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          100                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.ReadSharedReq_mshr_hits::total          100                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst           30                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data         3271                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total         3301                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst           30                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data         3271                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total         3301                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112673                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total       112673                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           10                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total           10                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8158                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         8158                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10034                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10034                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        36403                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total        36403                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst        10034                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        44561                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        54595                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst        10034                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        44561                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112673                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       167268                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10413466023                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10413466023                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       149500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       149500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    654073000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    654073000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    699673000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    699673000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2773387500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2773387500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    699673000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3427460500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total   4127133500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    699673000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3427460500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10413466023                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  14540599523                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           28                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data         3282                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total         3310                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           28                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data         3282                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total         3310                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112662                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total       112662                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           16                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           16                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8337                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         8337                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        10907                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total        10907                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        37406                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total        37406                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        10907                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        45743                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        56650                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        10907                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        45743                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112662                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       169312                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10325101509                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10325101509                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       232500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       232500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    662233000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    662233000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    771578500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    771578500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2838075000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2838075000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    771578500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3500308000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   4271886500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    771578500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3500308000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10325101509                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  14596988009                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.909091                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.909091                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.054909                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.054909                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.031019                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.031019                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.108037                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.108037                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.031019                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.091780                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.067484                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.031019                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.091780                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.056099                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.056099                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.033507                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.033507                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.110605                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.110605                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.033507                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.093966                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.069739                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.033507                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.093966                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.206758                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 92422.017901                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14950                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14950                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80175.655798                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80175.655798                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69730.217261                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69730.217261                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76185.685246                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76185.685246                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69730.217261                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76916.148650                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75595.448301                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69730.217261                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76916.148650                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 92422.017901                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86929.953864                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.208431                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests      1617003                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       808019                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        79877                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        65377                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops        56343                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops         9034                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        660441                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty       356528                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean       548578                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        77222                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq       142341                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp           11                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq       148572                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp       148572                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq       323492                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq       336950                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       969940                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1456076                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total           2426016                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41372672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     62114048                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          103486720                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                      316702                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples      1125716                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.137094                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.366537                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests      1623643                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       811337                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        80260                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops        67456                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops        56671                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        10785                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp        663721                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty       357454                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean       550979                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        79349                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq       142185                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq       148612                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp       148612                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq       325529                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq       338193                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       976039                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1459935                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total           2435974                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     41632640                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     62278272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          103910912                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                      318692                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples      1131024                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.140178                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.373630                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             980421     87.09%     87.09% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             136261     12.10%     99.20% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2               9034      0.80%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             983264     86.94%     86.94% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1             136975     12.11%     99.05% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              10785      0.95%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total        1125716                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy     1616479500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total        1131024                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy     1623114500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          4.8                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy     485683604                       # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization          1.4                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     728543988                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy     488687208                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy     730433064                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp             143003                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty        97128                       # Transaction distribution
-system.membus.trans_dist::CleanEvict            27951                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq               10                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              8158                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             8158                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq        143004                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       427412                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                 427412                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15890496                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                15890496                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp             144751                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty        97140                       # Transaction distribution
+system.membus.trans_dist::CleanEvict            28117                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq               16                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              8337                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             8337                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq        144752                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       431450                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                 431450                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     16014592                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                16014592                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples            276251                       # Request fanout histogram
+system.membus.snoop_fanout::samples            278362                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                  276251    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                  278362    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total              276251                       # Request fanout histogram
-system.membus.reqLayer0.occupancy           745073302                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total              278362                       # Request fanout histogram
+system.membus.reqLayer0.occupancy           747889943                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
-system.membus.respLayer1.occupancy          789293648                       # Layer occupancy (ticks)
-system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)
+system.membus.respLayer1.occupancy          799798093                       # Layer occupancy (ticks)
+system.membus.respLayer1.utilization              2.4                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
index 5327d957c..a0ce19406 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,104 +1,104 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.208729                       # Number of seconds simulated
-sim_ticks                                1208728699500                       # Number of ticks simulated
-final_tick                               1208728699500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.208778                       # Number of seconds simulated
+sim_ticks                                1208777694500                       # Number of ticks simulated
+final_tick                               1208777694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 330067                       # Simulator instruction rate (inst/s)
-host_op_rate                                   330067                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              218444071                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300788                       # Number of bytes of host memory used
-host_seconds                                  5533.36                       # Real time elapsed on the host
+host_inst_rate                                 395749                       # Simulator instruction rate (inst/s)
+host_op_rate                                   395749                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              261924296                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 253640                       # Number of bytes of host memory used
+host_seconds                                  4614.99                       # Real time elapsed on the host
 sim_insts                                  1826378509                       # Number of instructions simulated
 sim_ops                                    1826378509                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             61248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         124969728                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125030976                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        61248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           61248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65416576                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65416576                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                957                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1952652                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1953609                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1022134                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1022134                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                50671                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            103389394                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               103440066                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           50671                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              50671                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          54120148                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               54120148                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          54120148                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               50671                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           103389394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              157560214                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1953609                       # Number of read requests accepted
-system.physmem.writeReqs                      1022134                       # Number of write requests accepted
-system.physmem.readBursts                     1953609                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1022134                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                124947712                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     83264                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65415296                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125030976                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65416576                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1301                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             61312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         124970112                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125031424                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        61312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           61312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65416896                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65416896                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                958                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1952658                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1953616                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1022139                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1022139                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                50722                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            103385521                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               103436244                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           50722                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              50722                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          54118219                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               54118219                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          54118219                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               50722                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           103385521                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              157554463                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1953616                       # Number of read requests accepted
+system.physmem.writeReqs                      1022139                       # Number of write requests accepted
+system.physmem.readBursts                     1953616                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1022139                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                124948416                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83008                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65415616                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125031424                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65416896                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1297                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118310                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              113529                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              115745                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118316                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              113525                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              115740                       # Per bank write bursts
 system.physmem.perBankRdBursts::3              117258                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117308                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117123                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119399                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124116                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              126646                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              129571                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128166                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             129914                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             125584                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             124843                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122159                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             122637                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61419                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117310                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117126                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119402                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124113                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              126650                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              129582                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128169                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             129917                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             125580                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             124837                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122150                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             122644                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61421                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               61661                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60723                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61396                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60724                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61398                       # Per bank write bursts
 system.physmem.perBankWrBursts::4               61819                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63308                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63309                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               64356                       # Per bank write bursts
 system.physmem.perBankWrBursts::7               65855                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65578                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66028                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65644                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              65946                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64498                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64533                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              64901                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64449                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65577                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66031                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65643                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              65945                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64508                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64526                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              64900                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64446                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1208728583000                       # Total gap between requests
+system.physmem.totGap                    1208777578000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1953609                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1953616                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1022134                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1829960                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    122331                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1022139                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1830097                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    122205                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -144,30 +144,30 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    30641                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    31976                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    55228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    59652                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    60110                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60200                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    60169                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    60161                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    60210                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    60162                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    60231                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    60228                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    60672                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    61063                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    60669                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    61150                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    59820                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    59627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      111                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                       20                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    30602                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    32045                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55307                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    59695                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    60116                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60223                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60190                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    60196                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    60182                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    60140                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    60199                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    60169                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    60684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    61042                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    60657                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    61101                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    59828                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    59617                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       96                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                       18                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        7                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                        2                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
@@ -193,31 +193,31 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1831742                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.922688                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.125561                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     130.468112                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1453729     79.36%     79.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       261245     14.26%     93.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        48901      2.67%     96.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        20697      1.13%     97.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13090      0.71%     98.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7260      0.40%     98.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5482      0.30%     98.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         4525      0.25%     99.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        16813      0.92%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1831742                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         59619                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.744729                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      150.866534                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           59458     99.73%     99.73% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1831457                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.940817                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.136003                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     130.529919                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1452947     79.33%     79.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       261995     14.31%     93.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        48664      2.66%     96.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        20593      1.12%     97.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13175      0.72%     98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7238      0.40%     98.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5438      0.30%     98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         4580      0.25%     99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        16827      0.92%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1831457                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         59614                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.747643                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      146.947369                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59453     99.73%     99.73% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::512-1023          115      0.19%     99.92% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            8      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            9      0.02%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535            9      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            9      0.02%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2560-3071            3      0.01%     99.97% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-3583            3      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            3      0.01%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4608-5119            2      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
@@ -225,30 +225,30 @@ system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # R
 system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10752-11263            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::12288-12799            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-15871            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           59619                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         59619                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.144098                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.107874                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.119193                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27514     46.15%     46.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1196      2.01%     48.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              26405     44.29%     92.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3955      6.63%     99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                448      0.75%     99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 78      0.13%     99.96% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           59614                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         59614                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.145620                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.109391                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.119268                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27453     46.05%     46.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1268      2.13%     48.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              26337     44.18%     92.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4007      6.72%     99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                455      0.76%     99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 71      0.12%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::22                 15      0.03%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::23                  6      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::33                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           59619                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    36502723500                       # Total ticks spent queuing
-system.physmem.totMemAccLat               73108498500                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9761540000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18697.22                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           59614                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    36537628750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               73143610000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9761595000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18714.99                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37447.22                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  37464.99                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                         103.37                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          54.12                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                      103.44                       # Average system read bandwidth in MiByte/s
@@ -258,71 +258,75 @@ system.physmem.busUtil                           1.23                       # Da
 system.physmem.busUtilRead                       0.81                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.42                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.64                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     723641                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    419030                       # Number of row buffer hits during writes
+system.physmem.avgWrQLen                        24.80                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     723773                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    419204                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   37.07                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.00                       # Row buffer hit rate for writes
-system.physmem.avgGap                       406193.88                       # Average gap between requests
-system.physmem.pageHitRate                      38.42                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6715147320                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3664018875                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7353699600                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3243479760                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            78947837280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           414818688735                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           361357239750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             876100111320                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              724.815145                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   598389652500                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     40361880000                       # Time in different power states
+system.physmem.writeRowHitRate                  41.01                       # Row buffer hit rate for writes
+system.physmem.avgGap                       406208.70                       # Average gap between requests
+system.physmem.pageHitRate                      38.43                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                 6714376200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3663598125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7353738600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3243518640                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            78951397200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           415074736440                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           361165338750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             876166703955                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              724.837554                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   598070170000                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     40363700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    569973346500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    570342873000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7132791960                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3891900375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7873632000                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3379818960                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            78947837280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           426678504030                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           350953893000                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             878858377605                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              727.097114                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   581002634000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     40361880000                       # Time in different power states
+system.physmem_1.actEnergy                 7131423600                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3891153750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7874224800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3379812480                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            78951397200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           426560774805                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           351089866500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             878878653135                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              727.081103                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   581228871000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     40363700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    587357637250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    587184084000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               246098302                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186353272                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15586995                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            167674122                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               165197435                       # Number of BTB hits
+system.cpu.branchPred.lookups               246097965                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186356162                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15588061                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            167640085                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               165196337                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.522916                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                18413853                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect             104375                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.542265                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                18413332                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             104391                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups             297                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits                 67                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses              230                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted           98                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    452860961                       # DTB read hits
-system.cpu.dtb.read_misses                    4979889                       # DTB read misses
+system.cpu.dtb.read_hits                    452860657                       # DTB read hits
+system.cpu.dtb.read_misses                    4979867                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                457840850                       # DTB read accesses
-system.cpu.dtb.write_hits                   161378751                       # DTB write hits
-system.cpu.dtb.write_misses                   1709377                       # DTB write misses
+system.cpu.dtb.read_accesses                457840524                       # DTB read accesses
+system.cpu.dtb.write_hits                   161378231                       # DTB write hits
+system.cpu.dtb.write_misses                   1709431                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               163088128                       # DTB write accesses
-system.cpu.dtb.data_hits                    614239712                       # DTB hits
-system.cpu.dtb.data_misses                    6689266                       # DTB misses
+system.cpu.dtb.write_accesses               163087662                       # DTB write accesses
+system.cpu.dtb.data_hits                    614238888                       # DTB hits
+system.cpu.dtb.data_misses                    6689298                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                620928978                       # DTB accesses
-system.cpu.itb.fetch_hits                   597989879                       # ITB hits
+system.cpu.dtb.data_accesses                620928186                       # DTB accesses
+system.cpu.itb.fetch_hits                   597989612                       # ITB hits
 system.cpu.itb.fetch_misses                        19                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               597989898                       # ITB accesses
+system.cpu.itb.fetch_accesses               597989631                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -336,82 +340,117 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       2417457399                       # number of cpu cycles simulated
+system.cpu.numCycles                       2417555389                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1826378509                       # Number of instructions committed
 system.cpu.committedOps                    1826378509                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      51810559                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      51811935                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.323634                       # CPI: cycles per instruction
-system.cpu.ipc                               0.755496                       # IPC: instructions per cycle
-system.cpu.tickCycles                      2075240271                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       342217128                       # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements           9121937                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4080.725777                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           601539424                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9126033                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             65.914667                       # Average number of references to valid blocks.
+system.cpu.cpi                               1.323688                       # CPI: cycles per instruction
+system.cpu.ipc                               0.755465                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass            83736345      4.58%      4.58% # Class of committed instruction
+system.cpu.op_class_0::IntAlu              1129914150     61.87%     66.45% # Class of committed instruction
+system.cpu.op_class_0::IntMult                     75      0.00%     66.45% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     66.45% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                805244      0.04%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                    13      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                   100      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                   11      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                    24      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     66.50% # Class of committed instruction
+system.cpu.op_class_0::MemRead              449492741     24.61%     91.11% # Class of committed instruction
+system.cpu.op_class_0::MemWrite             162429806      8.89%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total               1826378509                       # Class of committed instruction
+system.cpu.tickCycles                      2075251932                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       342303457                       # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements           9121974                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4080.726355                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           601538856                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9126070                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             65.914337                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle       16821281500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4080.725777                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4080.726355                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.996271                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.996271                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1547                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2         2403                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1562                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2         2407                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           71                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1231276891                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1231276891                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    443057425                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       443057425                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    158481999                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      158481999                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     601539424                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        601539424                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    601539424                       # number of overall hits
-system.cpu.dcache.overall_hits::total       601539424                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      7289502                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       7289502                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2246503                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2246503                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      9536005                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9536005                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9536005                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9536005                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 185435901500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 185435901500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 108411798000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 108411798000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 293847699500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 293847699500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 293847699500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 293847699500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    450346927                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    450346927                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.tag_accesses        1231275880                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1231275880                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    443056865                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       443056865                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    158481991                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      158481991                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     601538856                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        601538856                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    601538856                       # number of overall hits
+system.cpu.dcache.overall_hits::total       601538856                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7289538                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7289538                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2246511                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2246511                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      9536049                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9536049                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9536049                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9536049                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 185480529000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 185480529000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 108417025500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 108417025500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 293897554500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 293897554500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 293897554500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 293897554500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    450346403                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    450346403                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    611075429                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    611075429                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    611075429                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    611075429                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016186                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.016186                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    611074905                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    611074905                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    611074905                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    611074905                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016187                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.016187                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013977                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.013977                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.015605                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.015605                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015605                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015605                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25438.761317                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25438.761317                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48258.025028                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48258.025028                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30814.549646                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30814.549646                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30814.549646                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30814.549646                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25444.757816                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25444.757816                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48260.180119                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48260.180119                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30819.635522                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30819.635522                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30819.635522                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30819.635522                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -420,32 +459,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3686592                       # number of writebacks
-system.cpu.dcache.writebacks::total           3686592                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50797                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        50797                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359175                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       359175                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       409972                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       409972                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       409972                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       409972                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238705                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7238705                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887328                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1887328                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9126033                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9126033                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9126033                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9126033                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176973816500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 176973816500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83260117500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  83260117500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260233934000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 260233934000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260233934000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 260233934000                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks      3686603                       # number of writebacks
+system.cpu.dcache.writebacks::total           3686603                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        50808                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        50808                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       359171                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       359171                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       409979                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       409979                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       409979                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       409979                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7238730                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7238730                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1887340                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1887340                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9126070                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9126070                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9126070                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9126070                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 177011068000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 177011068000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  83258719000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  83258719000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260269787000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 260269787000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260269787000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 260269787000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016074                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.016074                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011742                       # mshr miss rate for WriteReq accesses
@@ -454,66 +493,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014934
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014934                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014934                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014934                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.270305                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.270305                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44115.340577                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44115.340577                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28515.559170                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28515.559170                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28515.559170                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28515.559170                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24453.332007                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24453.332007                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44114.319095                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44114.319095                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.372194                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.372194                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.372194                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.372194                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 3                       # number of replacements
-system.cpu.icache.tags.tagsinuse           749.290154                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           597988922                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               957                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          624857.807732                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           750.173547                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           597988654                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               958                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          624205.275574                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   749.290154                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.365864                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.365864                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          954                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           80                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   750.173547                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.366296                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.366296                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          955                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          874                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.465820                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1195980715                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1195980715                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    597988922                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       597988922                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     597988922                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        597988922                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    597988922                       # number of overall hits
-system.cpu.icache.overall_hits::total       597988922                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          957                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           957                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            957                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          957                       # number of overall misses
-system.cpu.icache.overall_misses::total           957                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     76621000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     76621000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     76621000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     76621000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     76621000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     76621000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    597989879                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    597989879                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    597989879                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    597989879                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    597989879                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    597989879                       # number of overall (read+write) accesses
+system.cpu.icache.tags.occ_task_id_percent::1024     0.466309                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses        1195980182                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1195980182                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    597988654                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       597988654                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     597988654                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        597988654                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    597988654                       # number of overall hits
+system.cpu.icache.overall_hits::total       597988654                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          958                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           958                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            958                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          958                       # number of overall misses
+system.cpu.icache.overall_misses::total           958                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     76338000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     76338000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     76338000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     76338000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     76338000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     76338000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    597989612                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    597989612                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    597989612                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    597989612                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    597989612                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    597989612                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80063.740857                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 80063.740857                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 80063.740857                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 80063.740857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 80063.740857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 80063.740857                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79684.759916                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 79684.759916                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 79684.759916                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 79684.759916                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 79684.759916                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 79684.759916                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -524,107 +563,107 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            3                       # number of writebacks
 system.cpu.icache.writebacks::total                 3                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          957                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          957                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          957                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          957                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75664000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     75664000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75664000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     75664000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75664000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     75664000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          958                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          958                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          958                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          958                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     75380000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     75380000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     75380000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     75380000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     75380000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     75380000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79063.740857                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79063.740857                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79063.740857                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 79063.740857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79063.740857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 79063.740857                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78684.759916                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 78684.759916                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78684.759916                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 78684.759916                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1920885                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30765.167230                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14409636                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1950689                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.386947                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1920891                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        30765.315888                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14409692                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1950696                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.386949                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      89219766000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14798.522218                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.781155                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 15923.863857                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.451615                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001306                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.485958                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.938878                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29804                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          169                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1218                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12864                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 14798.392410                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    42.817395                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 15924.106083                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.451611                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.001307                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.485965                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.938883                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29805                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           36                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1217                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12865                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15532                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909546                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        149829457                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       149829457                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3686592                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3686592                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909576                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        149830076                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       149830076                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3686603                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3686603                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            3                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            3                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1106819                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1106819                       # number of ReadExReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6066562                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6066562                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7173381                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7173381                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7173381                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7173381                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       780509                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       780509                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          957                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          957                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1172143                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1172143                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          957                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1952652                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1953609                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          957                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1952652                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1953609                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68736259500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  68736259500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     74227500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     74227500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102389221500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 102389221500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     74227500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 171125481000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 171199708500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     74227500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 171125481000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 171199708500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3686592                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      3686592                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1106830                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1106830                       # number of ReadExReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6066582                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6066582                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7173412                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7173412                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7173412                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7173412                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       780510                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       780510                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          958                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          958                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1172148                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1172148                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          958                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1952658                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1953616                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          958                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1952658                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1953616                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  68734828000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  68734828000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     73941000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     73941000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 102426227000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 102426227000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     73941000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 171161055000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 171234996000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     73941000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 171161055000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 171234996000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3686603                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3686603                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks            3                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            3                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887328                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1887328                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          957                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          957                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238705                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7238705                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          957                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9126033                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9126990                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          957                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9126033                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9126990                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413552                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.413552                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1887340                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1887340                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          958                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          958                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7238730                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7238730                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          958                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9126070                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9127028                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          958                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9126070                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9127028                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.413550                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.413550                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.161927                       # miss rate for ReadSharedReq accesses
@@ -635,18 +674,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.214047                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.213965                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.214047                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88065.940944                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88065.940944                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77562.695925                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77562.695925                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87352.158824                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87352.158824                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77562.695925                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87637.469964                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87632.534709                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77562.695925                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87637.469964                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87632.534709                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88063.994055                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88063.994055                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77182.672234                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77182.672234                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87383.356880                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87383.356880                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77182.672234                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87655.418921                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87650.283372                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77182.672234                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87655.418921                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87650.283372                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -655,38 +694,38 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1022134                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1022134                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1022139                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1022139                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          242                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          242                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780509                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       780509                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          957                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          957                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1172143                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1172143                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          957                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1952652                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1953609                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          957                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1952652                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1953609                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60931169500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60931169500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64657500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64657500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90667791500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90667791500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64657500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151598961000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 151663618500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64657500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151598961000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 151663618500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       780510                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       780510                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          958                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          958                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1172148                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1172148                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          958                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1952658                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1953616                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          958                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1952658                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1953616                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  60929728000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  60929728000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     64361000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     64361000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  90704747000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  90704747000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     64361000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151634475000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 151698836000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     64361000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151634475000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 151698836000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413552                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413552                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.413550                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.413550                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.161927                       # mshr miss rate for ReadSharedReq accesses
@@ -697,81 +736,81 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.214047
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.213965                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.214047                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78065.940944                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78065.940944                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67562.695925                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67562.695925                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77352.158824                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77352.158824                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67562.695925                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77637.469964                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77632.534709                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67562.695925                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77637.469964                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77632.534709                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78063.994055                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78063.994055                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67182.672234                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77383.356880                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77383.356880                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77655.418921                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77650.283372                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67182.672234                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77655.418921                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77650.283372                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     18248930                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121940                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     18249005                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9121977                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops         1268                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1268                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7239662                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4708726                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7239688                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4708742                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            3                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6334096                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1887328                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1887328                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          957                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238705                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1917                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374003                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27375920                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820008000                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          820069440                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1920885                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     11047875                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::CleanEvict      6334123                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1887340                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1887340                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          958                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7238730                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1919                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27374114                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27376033                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61504                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    820011072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          820072576                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1920891                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11047919                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000115                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev       0.010713                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           11046607     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11046651     99.99%     99.99% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1               1268      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       11047875                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12811060000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11047919                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12811108500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1435500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1437000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13689049500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13689105000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1173100                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1022134                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           897725                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            780509                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           780509                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1173100                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827077                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5827077                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190447552                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               190447552                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1173106                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1022139                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           897726                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            780510                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           780510                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1173106                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5827097                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5827097                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    190448320                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               190448320                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3873468                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3873481                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3873468    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3873481    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3873468                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8428126500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3873481                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8428417500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.7                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10685578000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        10685410500                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.9                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
index f994e016c..f0b14c5aa 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,107 +1,107 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.669525                       # Number of seconds simulated
-sim_ticks                                669525393000                       # Number of ticks simulated
-final_tick                               669525393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.669588                       # Number of seconds simulated
+sim_ticks                                669587683000                       # Number of ticks simulated
+final_tick                               669587683000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 161577                       # Simulator instruction rate (inst/s)
-host_op_rate                                   161577                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               62314021                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 300544                       # Number of bytes of host memory used
-host_seconds                                 10744.38                       # Real time elapsed on the host
+host_inst_rate                                 206275                       # Simulator instruction rate (inst/s)
+host_op_rate                                   206275                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               79559671                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 254664                       # Number of bytes of host memory used
+host_seconds                                  8416.17                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
 sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             60992                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         125490432                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            125551424                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        60992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           60992                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     65555904                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          65555904                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                953                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            1960788                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               1961741                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1024311                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1024311                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                91097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            187431923                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               187523021                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           91097                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              91097                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          97913992                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               97913992                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          97913992                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               91097                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           187431923                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              285437013                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       1961741                       # Number of read requests accepted
-system.physmem.writeReqs                      1024311                       # Number of write requests accepted
-system.physmem.readBursts                     1961741                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1024311                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                125468352                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     83072                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                  65554688                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 125551424                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys               65555904                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1298                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst             60736                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         125489536                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            125550272                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        60736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           60736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     65555456                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          65555456                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                949                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            1960774                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               1961723                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1024304                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1024304                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                90707                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            187413149                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               187503855                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           90707                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              90707                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          97904214                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               97904214                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          97904214                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               90707                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           187413149                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              285408070                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       1961723                       # Number of read requests accepted
+system.physmem.writeReqs                      1024304                       # Number of write requests accepted
+system.physmem.readBursts                     1961723                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1024304                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                125465280                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     84992                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                  65553920                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 125550272                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys               65555456                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     1328                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              118677                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              113900                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              116118                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              117645                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              117762                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              117513                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              119856                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              124646                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              127338                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              130111                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             128791                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             130502                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             126296                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             125424                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             122633                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             123231                       # Per bank write bursts
-system.physmem.perBankWrBursts::0               61509                       # Per bank write bursts
-system.physmem.perBankWrBursts::1               61765                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               60825                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               61513                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               61969                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               63433                       # Per bank write bursts
-system.physmem.perBankWrBursts::6               64481                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65997                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               65770                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               66158                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              65809                       # Per bank write bursts
-system.physmem.perBankWrBursts::11              66082                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              64703                       # Per bank write bursts
-system.physmem.perBankWrBursts::13              64664                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              65021                       # Per bank write bursts
-system.physmem.perBankWrBursts::15              64593                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              118674                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              113905                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              116110                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              117640                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              117758                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              117504                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              119855                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              124644                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              127350                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              130115                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             128783                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             130505                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             126282                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             125429                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             122618                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             123223                       # Per bank write bursts
+system.physmem.perBankWrBursts::0               61508                       # Per bank write bursts
+system.physmem.perBankWrBursts::1               61766                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               60822                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               61512                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               61965                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               63432                       # Per bank write bursts
+system.physmem.perBankWrBursts::6               64483                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65996                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               65772                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               66160                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              65806                       # Per bank write bursts
+system.physmem.perBankWrBursts::11              66084                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              64700                       # Per bank write bursts
+system.physmem.perBankWrBursts::13              64663                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              65022                       # Per bank write bursts
+system.physmem.perBankWrBursts::15              64589                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    669525297500                       # Total gap between requests
+system.physmem.totGap                    669587587500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 1961741                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 1961723                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1024311                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1618506                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    241044                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                     69880                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                     30998                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        14                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1024304                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   1618543                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    241060                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                     69851                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                     30927                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        13                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    26356                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    27917                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    49392                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    56811                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    59370                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    60627                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    60983                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61171                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61281                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61428                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61383                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61603                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62346                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    63632                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    65011                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62797                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61721                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    60222                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                      183                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    26257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    27847                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    49475                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    56829                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    59490                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    60645                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    60944                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61173                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61265                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61375                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61421                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61570                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62336                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    63644                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    65120                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62738                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61667                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    60239                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                      191                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::34                       38                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                       19                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                       14                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                        7                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
@@ -193,55 +193,58 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1769975                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      107.923423                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      82.935475                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     137.553027                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1375598     77.72%     77.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       270762     15.30%     93.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        53515      3.02%     96.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21283      1.20%     97.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        12968      0.73%     97.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         6460      0.36%     98.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         4828      0.27%     98.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         3885      0.22%     98.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        20676      1.17%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1769975                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         60095                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        32.621932                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      151.728866                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511           59931     99.73%     99.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023          120      0.20%     99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1535           12      0.02%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-2047            4      0.01%     99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559            5      0.01%     99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-3071            5      0.01%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3583            4      0.01%     99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-4095            2      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1769781                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      107.933083                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      82.950192                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     137.486388                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1375005     77.69%     77.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       271238     15.33%     93.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        53445      3.02%     96.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21262      1.20%     97.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        12891      0.73%     97.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         6578      0.37%     98.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         4909      0.28%     98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         3869      0.22%     98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        20584      1.16%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1769781                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         60104                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        32.614784                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      150.080179                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511           59932     99.71%     99.71% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023          127      0.21%     99.93% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1535           10      0.02%     99.94% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-2047            7      0.01%     99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-2559            8      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-3071            4      0.01%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-3583            3      0.00%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3584-4095            1      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-4607            2      0.00%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4608-5119            3      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::6656-7167            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::9216-9727            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::8704-9215            1      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::9216-9727            1      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::11776-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::14848-15359            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-15871            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           60095                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         60095                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.044546                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.002519                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.231700                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              31758     52.85%     52.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1379      2.29%     55.14% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              21272     35.40%     90.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               4591      7.64%     98.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                816      1.36%     99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                185      0.31%     99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                 43      0.07%     99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                 20      0.03%     99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  5      0.01%     99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                  5      0.01%     99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::14848-15359            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total           60104                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         60104                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.041794                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.999820                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.231211                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              31815     52.93%     52.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1444      2.40%     55.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              21085     35.08%     90.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               4727      7.86%     98.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                762      1.27%     99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                188      0.31%     99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                 35      0.06%     99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                 13      0.02%     99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                  6      0.01%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                  1      0.00%     99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                  5      0.01%     99.96% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::27                  2      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28                  1      0.00%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30                  1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::31                  1      0.00%     99.97% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::32                  3      0.00%     99.98% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::33                  2      0.00%     99.98% # Writes before turning the bus around for reads
@@ -254,87 +257,91 @@ system.physmem.wrPerTurnAround::39                  1      0.00%    100.00% # Wr
 system.physmem.wrPerTurnAround::40                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::41                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::42                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           60095                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    40550197000                       # Total ticks spent queuing
-system.physmem.totMemAccLat               77308503250                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                   9802215000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       20684.20                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           60104                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    40549512750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               77306919000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                   9801975000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       20684.36                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  39434.20                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         187.40                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                          97.91                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      187.52                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                       97.91                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  39434.36                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         187.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                          97.90                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      187.50                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                       97.90                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           2.23                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       1.46                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.76                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.10                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.94                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     792754                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    422001                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   40.44                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  41.20                       # Row buffer hit rate for writes
-system.physmem.avgGap                       224217.56                       # Average gap between requests
+system.physmem.avgWrQLen                        24.98                       # Average write queue length when enqueuing
+system.physmem.readRowHits                     792652                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    422237                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   40.43                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  41.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                       224240.30                       # Average gap between requests
 system.physmem.pageHitRate                      40.70                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 6484552200                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3538198125                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7379689200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3249668160                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            43730057280                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           304192019700                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           134879490000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             503453674665                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              751.957257                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   222404009750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     22356880000                       # Time in different power states
+system.physmem_0.actEnergy                 6484506840                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3538173375                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7379478600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3249616320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            43734125760                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           304395031755                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           134738783250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             503519715900                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              751.985934                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   222173701250                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     22358960000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    424763715750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    425054234250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 6896443680                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 3762940500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                7911594600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3387744000                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            43730057280                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           311181502770                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           128748364500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             505618647330                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              755.190855                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   212167441250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     22356880000                       # Time in different power states
+system.physmem_1.actEnergy                 6895022400                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 3762165000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                7911430800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3387718080                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            43734125760                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           311120339490                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           128839390500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             505650192030                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              755.167712                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   212315780250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     22358960000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    435000017500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    434911888500                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               409350195                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         318164532                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          15963584                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            282308187                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               278578841                       # Number of BTB hits
+system.cpu.branchPred.lookups               409349783                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         318159413                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          15962959                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            282310323                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               278567233                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             98.678981                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                26172152                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 19                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             98.674122                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                26172089                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 47                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           12632                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits               1004                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            11628                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted           76                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                    644938332                       # DTB read hits
-system.cpu.dtb.read_misses                   12159455                       # DTB read misses
+system.cpu.dtb.read_hits                    644930756                       # DTB read hits
+system.cpu.dtb.read_misses                   12159240                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                657097787                       # DTB read accesses
-system.cpu.dtb.write_hits                   218091822                       # DTB write hits
-system.cpu.dtb.write_misses                   7511788                       # DTB write misses
+system.cpu.dtb.read_accesses                657089996                       # DTB read accesses
+system.cpu.dtb.write_hits                   218090963                       # DTB write hits
+system.cpu.dtb.write_misses                   7511655                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses               225603610                       # DTB write accesses
-system.cpu.dtb.data_hits                    863030154                       # DTB hits
-system.cpu.dtb.data_misses                   19671243                       # DTB misses
+system.cpu.dtb.write_accesses               225602618                       # DTB write accesses
+system.cpu.dtb.data_hits                    863021719                       # DTB hits
+system.cpu.dtb.data_misses                   19670895                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                882701397                       # DTB accesses
-system.cpu.itb.fetch_hits                   420624983                       # ITB hits
+system.cpu.dtb.data_accesses                882692614                       # DTB accesses
+system.cpu.itb.fetch_hits                   420612911                       # ITB hits
 system.cpu.itb.fetch_misses                        37                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses               420625020                       # ITB accesses
+system.cpu.itb.fetch_accesses               420612948                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -348,138 +355,138 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   29                       # Number of system calls
-system.cpu.numCycles                       1339050787                       # number of cpu cycles simulated
+system.cpu.numCycles                       1339175367                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles          431760433                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     3409990757                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   409350195                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          304750993                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     884524854                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                45382362                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles          431750962                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     3410040939                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   409349783                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          304740326                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     884658040                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                45380368                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles          1660                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles           14                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 420624983                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8290664                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1338978167                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.546711                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.150697                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles            9                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 420612911                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8286314                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1339100880                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.546515                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.150664                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                713970324     53.32%     53.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 47658259      3.56%     56.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 24222568      1.81%     58.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 45103345      3.37%     62.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                142790906     10.66%     72.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 65943786      4.92%     77.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 43594409      3.26%     80.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 29428241      2.20%     83.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                226266329     16.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                714090223     53.33%     53.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 47658538      3.56%     56.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 24213511      1.81%     58.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 45104764      3.37%     62.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                142790793     10.66%     72.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 65948937      4.92%     77.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 43596223      3.26%     80.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 29427236      2.20%     83.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                226270655     16.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1338978167                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.305702                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.546573                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                353776569                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             403484138                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 524228681                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              34798314                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               22690465                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             62024721                       # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total           1339100880                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.305673                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.546374                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                353769972                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             403619551                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 524217734                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              34804152                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               22689471                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             62026814                       # Number of times decode resolved a branch
 system.cpu.decode.BranchMispred                   760                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             3256106209                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                  2093                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               22690465                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                372012141                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               212467548                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           7342                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 537162613                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             194638058                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             3173768927                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents               1816422                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               20455726                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents              148599653                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               30860374                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          2371827952                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            4117690277                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       4117553850                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            136426                       # Number of floating rename lookups
+system.cpu.decode.DecodedInsts             3256105292                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                  2070                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               22689471                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                372006695                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               212568628                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           7422                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 537155412                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             194673252                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             3173749438                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents               1811256                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               20472342                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents              148588016                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               30888023                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          2371822708                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            4117670877                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       4117534302                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            136574                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1376202963                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                995624989                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                146                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            145                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  99592668                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            717246268                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           272455740                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          90411000                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         58626283                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2884178650                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 125                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                2620049271                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1544769                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined      1148134993                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    502709027                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             96                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1338978167                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.956753                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.148253                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                995619745                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                151                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            149                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  99632674                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            717246724                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           272457234                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          90451892                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         58631522                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2884174304                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 130                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                2620036143                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1544818                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined      1148130652                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    502718906                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            101                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1339100880                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.956564                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.148176                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           535496202     39.99%     39.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           169647302     12.67%     52.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           157966093     11.80%     64.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           149142376     11.14%     75.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4           126023638      9.41%     85.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            84181895      6.29%     91.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            68010869      5.08%     96.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7            34104922      2.55%     98.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8            14404870      1.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           535608565     40.00%     40.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           169639715     12.67%     52.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           157955882     11.80%     64.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           149207498     11.14%     75.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4           126008488      9.41%     85.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            84159132      6.28%     91.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            68020206      5.08%     96.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7            34099830      2.55%     98.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8            14401564      1.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1338978167                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1339100880                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                13158801     35.84%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               18966749     51.66%     87.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               4591786     12.51%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                13158046     35.85%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               18960543     51.65%     87.50% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               4589272     12.50%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1716928227     65.53%     65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                  113      0.00%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1716921702     65.53%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                  112      0.00%     65.53% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd              896664      0.03%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                  19      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd              896133      0.03%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                  22      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                 165      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                 30      0.00%     65.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                 32      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatDiv                  26      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     65.56% # Type of FU issued
@@ -502,82 +509,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     65.56% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     65.56% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     65.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            671542182     25.63%     91.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           230681845      8.80%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            671538399     25.63%     91.20% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           230679552      8.80%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             2620049271                       # Type of FU issued
-system.cpu.iq.rate                           1.956647                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    36717336                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.014014                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         6615397697                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        4031207578                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   2518612422                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             1941117                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            1249905                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       887144                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2655798760                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  967847                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         69398293                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             2620036143                       # Type of FU issued
+system.cpu.iq.rate                           1.956455                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    36707861                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.014010                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         6615486651                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        4031199558                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   2518604332                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             1939194                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            1248781                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       886609                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2655777108                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  966896                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         69396468                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    272650605                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       374228                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       146038                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores    111727238                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    272651061                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       372885                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       145563                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores    111728732                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads          239                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       6310160                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads          286                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       6308614                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               22690465                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles               149836338                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles              21229362                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          3035183152                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           6595413                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             717246268                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            272455740                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                125                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 801803                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents              20684202                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         146038                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10633994                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8701055                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             19335049                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            2574897906                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             657097795                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          45151365                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               22689471                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles               149827283                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles              21278630                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          3035173177                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           6594541                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             717246724                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            272457234                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                130                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 801857                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents              20733670                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         145563                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10633550                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8701156                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             19334706                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            2574881369                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             657090005                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          45154774                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                     151004377                       # number of nop insts executed
-system.cpu.iew.exec_refs                    882701473                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                315482828                       # Number of branches executed
-system.cpu.iew.exec_stores                  225603678                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.922928                       # Inst execution rate
-system.cpu.iew.wb_sent                     2549323154                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    2519499566                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1487497634                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1918379503                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.881556                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.775393                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       998640819                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                     150998743                       # number of nop insts executed
+system.cpu.iew.exec_refs                    882692691                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                315484112                       # Number of branches executed
+system.cpu.iew.exec_stores                  225602686                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.922737                       # Inst execution rate
+system.cpu.iew.wb_sent                     2549313271                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    2519490941                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1487485532                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1918368513                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.881375                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.775391                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       998632615                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          15962868                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1200994355                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.515228                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.548533                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          15962246                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1201120469                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.515069                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.548329                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    712309125     59.31%     59.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    159609736     13.29%     72.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     79494019      6.62%     79.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     52028691      4.33%     83.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     28473987      2.37%     85.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     19488340      1.62%     87.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     19957354      1.66%     89.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     23050317      1.92%     91.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8    106582786      8.87%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    712379439     59.31%     59.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    159650119     13.29%     72.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     79517213      6.62%     79.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     52024602      4.33%     83.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     28479101      2.37%     85.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     19489140      1.62%     87.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     19970906      1.66%     89.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     23045357      1.92%     91.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8    106564592      8.87%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1200994355                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1201120469                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
 system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -623,265 +630,265 @@ system.cpu.commit.op_class_0::MemWrite      160728502      8.83%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1819780126                       # Class of committed instruction
-system.cpu.commit.bw_lim_events             106582786                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3827053314                       # The number of ROB reads
-system.cpu.rob.rob_writes                  5774960362                       # The number of ROB writes
-system.cpu.timesIdled                             711                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           72620                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events             106564592                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3827189418                       # The number of ROB reads
+system.cpu.rob.rob_writes                  5774940551                       # The number of ROB writes
+system.cpu.timesIdled                             705                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           74487                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
 system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.771323                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.771323                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.296473                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.296473                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               3463595596                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2019348323                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                     39740                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      588                       # number of floating regfile writes
+system.cpu.cpi                               0.771395                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.771395                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.296353                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.296353                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               3463571137                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2019338951                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                     39668                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      612                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                      25                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements           9207181                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.441061                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           712353360                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs           9211277                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             77.334919                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements           9207202                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          4087.451175                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           712346624                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           9211298                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             77.334011                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        5127954500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.441061                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.997910                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.997910                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.451175                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.997913                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.997913                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          698                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         2969                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          699                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         2968                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2          425                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3            4                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1470163219                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1470163219                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    556855010                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       556855010                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    155498347                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      155498347                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data     712353357                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        712353357                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    712353357                       # number of overall hits
-system.cpu.dcache.overall_hits::total       712353357                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     12892455                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      12892455                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      5230155                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      5230155                       # number of WriteReq misses
+system.cpu.dcache.tags.tag_accesses        1470154674                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1470154674                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    556848448                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       556848448                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155498172                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155498172                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            4                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            4                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     712346620                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        712346620                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    712346620                       # number of overall hits
+system.cpu.dcache.overall_hits::total       712346620                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     12894733                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      12894733                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5230330                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5230330                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     18122610                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       18122610                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     18122610                       # number of overall misses
-system.cpu.dcache.overall_misses::total      18122610                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 411787652500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 411787652500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 315044398573                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 315044398573                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        72500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total        72500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 726832051073                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 726832051073                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 726832051073                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 726832051073                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    569747465                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    569747465                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data     18125063                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       18125063                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     18125063                       # number of overall misses
+system.cpu.dcache.overall_misses::total      18125063                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 412093066500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 412093066500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 315139193599                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 315139193599                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        85500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        85500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 727232260099                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 727232260099                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 727232260099                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 727232260099                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    569743181                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    569743181                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total            4                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    730475967                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    730475967                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    730475967                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    730475967                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022628                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.022628                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032540                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.032540                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.250000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.250000                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.024809                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.024809                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.024809                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.024809                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31940.204755                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 31940.204755                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60236.149516                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 60236.149516                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        72500                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        72500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 40106.367188                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 40106.367188                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 40106.367188                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 40106.367188                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     15689743                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      9578184                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs           1104687                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           68028                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.202886                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets   140.797672                       # average number of cycles each access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            5                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            5                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    730471683                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    730471683                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    730471683                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    730471683                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.022633                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.022633                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.032541                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.032541                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.200000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.200000                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.024813                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.024813                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.024813                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.024813                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31958.247332                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 31958.247332                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60252.258194                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60252.258194                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85500                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40123.019716                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40123.019716                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40123.019716                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40123.019716                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     15672953                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      9573691                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs           1104455                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           68040                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    14.190667                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets   140.706805                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3727717                       # number of writebacks
-system.cpu.dcache.writebacks::total           3727717                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5560371                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      5560371                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3350963                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      3350963                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      8911334                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      8911334                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      8911334                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      8911334                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7332084                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      7332084                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879192                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      1879192                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks      3727750                       # number of writebacks
+system.cpu.dcache.writebacks::total           3727750                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      5562625                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      5562625                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3351141                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3351141                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      8913766                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      8913766                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      8913766                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      8913766                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7332108                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7332108                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1879189                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1879189                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      9211276                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      9211276                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      9211276                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      9211276                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182956640000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 182956640000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84332021587                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84332021587                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        71500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        71500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267288661587                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 267288661587                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267288661587                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 267288661587                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data      9211297                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9211297                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9211297                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9211297                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182971511500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 182971511500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84313777567                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84313777567                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        84500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        84500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267285289067                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 267285289067                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267285289067                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 267285289067                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.012869                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.012869                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011692                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.011692                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.200000                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.200000                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.012610                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012610                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.012610                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24952.883791                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24952.883791                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.745743                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.745743                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        71500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        71500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.549967                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.549967                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.549967                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.549967                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.830384                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.830384                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44867.108932                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44867.108932                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        84500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        84500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.117684                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.117684                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.117684                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.117684                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                 1                       # number of replacements
-system.cpu.icache.tags.tagsinuse           755.122971                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           420623501                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               953                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          441367.786988                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           753.790798                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           420611422                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               949                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          443215.407798                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   755.122971                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.368712                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.368712                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          952                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   753.790798                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.368062                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.368062                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          948                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1            2                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          886                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.464844                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         841250919                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        841250919                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    420623501                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       420623501                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     420623501                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        420623501                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    420623501                       # number of overall hits
-system.cpu.icache.overall_hits::total       420623501                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1482                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1482                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1482                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1482                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1482                       # number of overall misses
-system.cpu.icache.overall_misses::total          1482                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    113433000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    113433000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    113433000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    113433000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    113433000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    113433000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    420624983                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    420624983                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    420624983                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    420624983                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    420624983                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    420624983                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          882                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.462891                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         841226771                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        841226771                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    420611422                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       420611422                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     420611422                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        420611422                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    420611422                       # number of overall hits
+system.cpu.icache.overall_hits::total       420611422                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1489                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1489                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1489                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1489                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1489                       # number of overall misses
+system.cpu.icache.overall_misses::total          1489                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    114620499                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    114620499                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    114620499                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    114620499                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    114620499                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    114620499                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    420612911                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    420612911                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    420612911                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    420612911                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    420612911                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    420612911                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000004                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76540.485830                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76540.485830                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76540.485830                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76540.485830                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76540.485830                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76540.485830                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          290                       # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76978.172599                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76978.172599                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76978.172599                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76978.172599                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76978.172599                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76978.172599                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          274                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                 5                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           58                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    68.500000                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
 system.cpu.icache.writebacks::total                 1                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          529                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          529                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          529                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          529                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          529                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          529                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          953                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          953                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          953                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          953                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          953                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          953                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     79168000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     79168000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     79168000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     79168000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     79168000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     79168000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          540                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          540                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          540                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          540                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          540                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          540                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          949                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          949                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          949                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          949                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          949                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          949                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     79774499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     79774499                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     79774499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     79774499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     79774499                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     79774499                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83072.402938                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83072.402938                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83072.402938                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 83072.402938                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83072.402938                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 83072.402938                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84061.642782                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84061.642782                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84061.642782                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 84061.642782                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84061.642782                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 84061.642782                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          1929037                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31408.501295                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14580101                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          1958824                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.443293                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          1929018                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31408.626842                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14580161                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1958805                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.443396                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      28140218000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14352.871617                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.846080                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 17029.783598                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.438015                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000789                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.519708                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.958511                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 14352.619403                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    25.692409                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 17030.315030                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.438007                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000784                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.519724                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.958515                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        29787                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0          157                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1          977                       # Occupied blocks per task id
@@ -889,84 +896,84 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2          615
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        17550                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        10488                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.909027                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        151193328                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       151193328                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3727717                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3727717                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.tag_accesses        151193610                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       151193610                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3727750                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3727750                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks            1                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total            1                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1106791                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1106791                       # number of ReadExReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6143698                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6143698                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.data      7250489                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         7250489                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.data      7250489                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        7250489                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data       772417                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       772417                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          953                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          953                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1188371                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1188371                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          953                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      1960788                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       1961741                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          953                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      1960788                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      1961741                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  69331694500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  69331694500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     77733500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     77733500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106499450500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 106499450500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     77733500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 175831145000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 175908878500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     77733500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 175831145000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 175908878500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3727717                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      3727717                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1106786                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1106786                       # number of ReadExReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6143738                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6143738                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.data      7250524                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         7250524                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      7250524                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        7250524                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data       772419                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       772419                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          949                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          949                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1188355                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1188355                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          949                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1960774                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1961723                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          949                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1960774                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1961723                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  69313632000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  69313632000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     78342500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     78342500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 106514273500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 106514273500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     78342500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 175827905500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 175906248000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     78342500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 175827905500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 175906248000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3727750                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3727750                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks            1                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total            1                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      1879208                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      1879208                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          953                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          953                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7332069                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total      7332069                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          953                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      9211277                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9212230                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          953                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      9211277                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9212230                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411033                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.411033                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1879205                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1879205                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          949                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          949                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7332093                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total      7332093                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          949                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9211298                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9212247                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          949                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9211298                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9212247                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.411035                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.411035                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst            1                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_miss_rate::total            1                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162079                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162079                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.162076                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.162076                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.212868                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.212950                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.212866                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.212947                       # miss rate for demand accesses
 system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.212868                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.212950                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89759.410396                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89759.410396                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81567.156348                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81567.156348                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89618.015334                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89618.015334                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81567.156348                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89673.715363                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89669.777254                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81567.156348                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89673.715363                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89669.777254                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.212866                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.212947                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89735.793656                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89735.793656                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82552.687039                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82552.687039                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89631.695495                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89631.695495                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82552.687039                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89672.703483                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 89669.259116                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82552.687039                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89672.703483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89669.259116                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -975,123 +982,123 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1024311                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1024311                       # number of writebacks
+system.cpu.l2cache.writebacks::writebacks      1024304                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1024304                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          240                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          240                       # number of CleanEvict MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       772417                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       772417                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          953                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          953                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1188371                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1188371                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          953                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      1960788                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      1961741                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          953                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      1960788                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      1961741                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61607524500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61607524500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68203500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68203500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94615740500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94615740500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68203500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156223265000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 156291468500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68203500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156223265000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 156291468500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       772419                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       772419                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          949                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          949                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1188355                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1188355                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          949                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1960774                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1961723                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          949                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1960774                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1961723                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  61589442000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  61589442000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     68852500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     68852500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  94630723500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  94630723500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     68852500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156220165500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 156289018000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     68852500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156220165500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 156289018000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411033                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411033                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.411035                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.411035                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162079                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162079                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.162076                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.162076                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212868                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.212950                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.212866                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.212947                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212868                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.212950                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79759.410396                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79759.410396                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71567.156348                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71567.156348                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79618.015334                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79618.015334                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71567.156348                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79673.715363                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.777254                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71567.156348                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79673.715363                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.777254                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.212866                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.212947                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79735.793656                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79735.793656                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72552.687039                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72552.687039                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79631.695495                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79631.695495                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72552.687039                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79672.703483                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79669.259116                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72552.687039                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79672.703483                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79669.259116                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     18419412                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests      9207182                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests     18419450                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests      9207203                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1280                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1280                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1275                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1275                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7333022                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4752028                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7333042                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4752054                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean            1                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6384190                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      1879208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      1879208                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          953                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq      7332069                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1907                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27629735                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27631642                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        61056                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828095616                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total          828156672                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     1929037                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     11141267                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.000115                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.010718                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::CleanEvict      6384166                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      1879205                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      1879205                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          949                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq      7332093                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1899                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27629798                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27631697                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        60800                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    828099072                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total          828159872                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     1929018                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11141265                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.000114                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.010697                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           11139987     99.99%     99.99% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               1280      0.01%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11139990     99.99%     99.99% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1275      0.01%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       11141267                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12937424000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11141265                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12937476000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.9                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1429500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1423999                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13816915500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13816947000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          2.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1189324                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1024311                       # Transaction distribution
-system.membus.trans_dist::CleanEvict           903686                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            772417                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           772417                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1189324                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851479                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                5851479                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191107328                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               191107328                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            1189304                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1024304                       # Transaction distribution
+system.membus.trans_dist::CleanEvict           903679                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            772419                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           772419                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       1189304                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      5851429                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                5851429                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    191105728                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               191105728                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           3889738                       # Request fanout histogram
+system.membus.snoop_fanout::samples           3889706                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 3889738    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 3889706    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             3889738                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8475624000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             3889706                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8475680000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               1.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        10684646000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        10684396000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.6                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
index 0ee27457c..0b0903e3c 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
@@ -1,68 +1,68 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.116861                       # Number of seconds simulated
-sim_ticks                                1116860578500                       # Number of ticks simulated
-final_tick                               1116860578500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.116866                       # Number of seconds simulated
+sim_ticks                                1116865668500                       # Number of ticks simulated
+final_tick                               1116865668500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 228405                       # Simulator instruction rate (inst/s)
-host_op_rate                                   246072                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              165157932                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 318996                       # Number of bytes of host memory used
-host_seconds                                  6762.38                       # Real time elapsed on the host
+host_inst_rate                                 315195                       # Simulator instruction rate (inst/s)
+host_op_rate                                   339575                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              227915704                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 272300                       # Number of bytes of host memory used
+host_seconds                                  4900.35                       # Real time elapsed on the host
 sim_insts                                  1544563088                       # Number of instructions simulated
 sim_ops                                    1664032481                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             50176                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst             50112                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         130931712                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            130981888                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        50176                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           50176                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total            130981824                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        50112                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           50112                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks     67207872                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          67207872                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                784                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst                783                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data            2045808                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               2046592                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               2046591                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks         1050123                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total              1050123                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                44926                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            117231922                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               117276848                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           44926                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              44926                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          60175704                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               60175704                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          60175704                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               44926                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           117231922                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              177452552                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       2046592                       # Number of read requests accepted
+system.physmem.bw_read::cpu.inst                44868                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            117231388                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               117276256                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           44868                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              44868                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          60175430                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               60175430                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          60175430                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               44868                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           117231388                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              177451686                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       2046591                       # Number of read requests accepted
 system.physmem.writeReqs                      1050123                       # Number of write requests accepted
-system.physmem.readBursts                     2046592                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                     2046591                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                    1050123                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                130898112                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                     83776                       # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM                130898176                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                     83648                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                  67206400                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 130981888                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                 130981824                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys               67207872                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     1309                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ                     1307                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0              127279                       # Per bank write bursts
 system.physmem.perBankRdBursts::1              124661                       # Per bank write bursts
 system.physmem.perBankRdBursts::2              121601                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              123659                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              123656                       # Per bank write bursts
 system.physmem.perBankRdBursts::4              122620                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              122678                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              122679                       # Per bank write bursts
 system.physmem.perBankRdBursts::6              123247                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              123768                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              131395                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              123770                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              131396                       # Per bank write bursts
 system.physmem.perBankRdBursts::9              133511                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             132082                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             133309                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             132081                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             133308                       # Per bank write bursts
 system.physmem.perBankRdBursts::12             133249                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             133361                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             129308                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             133362                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             129309                       # Per bank write bursts
 system.physmem.perBankRdBursts::15             129555                       # Per bank write bursts
 system.physmem.perBankWrBursts::0               66136                       # Per bank write bursts
 system.physmem.perBankWrBursts::1               64410                       # Per bank write bursts
@@ -71,25 +71,25 @@ system.physmem.perBankWrBursts::3               63006                       # Pe
 system.physmem.perBankWrBursts::4               63000                       # Per bank write bursts
 system.physmem.perBankWrBursts::5               63100                       # Per bank write bursts
 system.physmem.perBankWrBursts::6               64443                       # Per bank write bursts
-system.physmem.perBankWrBursts::7               65435                       # Per bank write bursts
-system.physmem.perBankWrBursts::8               67311                       # Per bank write bursts
-system.physmem.perBankWrBursts::9               67795                       # Per bank write bursts
-system.physmem.perBankWrBursts::10              67548                       # Per bank write bursts
+system.physmem.perBankWrBursts::7               65436                       # Per bank write bursts
+system.physmem.perBankWrBursts::8               67310                       # Per bank write bursts
+system.physmem.perBankWrBursts::9               67797                       # Per bank write bursts
+system.physmem.perBankWrBursts::10              67549                       # Per bank write bursts
 system.physmem.perBankWrBursts::11              67882                       # Per bank write bursts
-system.physmem.perBankWrBursts::12              67328                       # Per bank write bursts
+system.physmem.perBankWrBursts::12              67326                       # Per bank write bursts
 system.physmem.perBankWrBursts::13              67793                       # Per bank write bursts
-system.physmem.perBankWrBursts::14              66483                       # Per bank write bursts
+system.physmem.perBankWrBursts::14              66482                       # Per bank write bursts
 system.physmem.perBankWrBursts::15              65854                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    1116860484000                       # Total gap between requests
+system.physmem.totGap                    1116865574000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 2046592                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 2046591                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -97,9 +97,9 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                1050123                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   1916633                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                    128632                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                        18                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                   1916619                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                    128648                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                        17                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
@@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    32728                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    33960                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    56927                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    32746                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    33984                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    56911                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::18                    61204                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    61631                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    61691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    61599                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                    61668                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                    61654                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                    61696                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                    61750                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                    61691                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                    62166                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                    62564                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                    62074                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                    62571                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                    61298                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                    61140                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                       86                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    61629                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    61690                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                    61591                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                    61663                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                    61651                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                    61697                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                    61747                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                    61696                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                    62170                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                    62557                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                    62067                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                    62573                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                    61301                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                    61138                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                       84                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::35                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::36                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::37                        1                       # What write queue length does an incoming req see
@@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      1910141                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      103.711749                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      81.835384                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     125.555895                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        1485377     77.76%     77.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       305179     15.98%     93.74% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        52494      2.75%     96.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        21040      1.10%     97.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        13364      0.70%     98.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767         7561      0.40%     98.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         5492      0.29%     98.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5154      0.27%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        14480      0.76%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        1910141                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         61138                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        33.410579                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      159.595244                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023          61092     99.92%     99.92% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      1910138                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      103.711175                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      81.836423                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     125.540224                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        1485349     77.76%     77.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       305158     15.98%     93.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        52532      2.75%     96.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        21047      1.10%     97.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        13374      0.70%     98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767         7565      0.40%     98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         5491      0.29%     98.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5162      0.27%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        14460      0.76%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        1910138                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         61136                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        33.411672                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      159.590236                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023          61090     99.92%     99.92% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1024-2047           21      0.03%     99.96% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-3071           10      0.02%     99.98% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::3072-4095            7      0.01%     99.99% # Reads before turning the bus around for writes
@@ -219,27 +219,27 @@ system.physmem.rdPerTurnAround::9216-10239            2      0.00%    100.00% #
 system.physmem.rdPerTurnAround::13312-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::15360-16383            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::22528-23551            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           61138                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         61138                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        17.175897                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       17.140866                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.098115                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              27038     44.22%     44.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               1118      1.83%     46.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              28658     46.87%     92.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               3907      6.39%     99.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20                362      0.59%     99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                 47      0.08%     99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           61136                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         61136                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        17.176459                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       17.141461                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.097536                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              27008     44.18%     44.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1128      1.85%     46.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              28688     46.92%     92.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               3895      6.37%     99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20                363      0.59%     99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                 46      0.08%     99.99% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::22                  6      0.01%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                  1      0.00%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::26                  1      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           61138                       # Writes before turning the bus around for reads
-system.physmem.totQLat                    38118822750                       # Total ticks spent queuing
-system.physmem.totMemAccLat               76467879000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  10226415000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       18637.43                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total           61136                       # Writes before turning the bus around for reads
+system.physmem.totQLat                    38124700750                       # Total ticks spent queuing
+system.physmem.totMemAccLat               76473775750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  10226420000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       18640.30                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  37387.43                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  37390.30                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                         117.20                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                          60.17                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                      117.28                       # Average system read bandwidth in MiByte/s
@@ -250,49 +250,53 @@ system.physmem.busUtilRead                       0.92                       # Da
 system.physmem.busUtilWrite                      0.47                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.02                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                        24.32                       # Average write queue length when enqueuing
-system.physmem.readRowHits                     773327                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    411912                       # Number of row buffer hits during writes
+system.physmem.readRowHits                     773341                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    411895                       # Number of row buffer hits during writes
 system.physmem.readRowHitRate                   37.81                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  39.23                       # Row buffer hit rate for writes
-system.physmem.avgGap                       360659.76                       # Average gap between requests
+system.physmem.writeRowHitRate                  39.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                       360661.52                       # Average gap between requests
 system.physmem.pageHitRate                      38.29                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                 7038745560                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 3840585375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                7718170200                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               3318446880                       # Energy for write commands per rank (pJ)
+system.physmem_0.actEnergy                 7039078200                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 3840766875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                7717881600                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               3318453360                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy            72947846400                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           420695682570                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy           301084680000                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             816644156985                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              731.196552                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   498171573500                       # Time in different power states
+system.physmem_0.actBackEnergy           420697412235                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy           301083150000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             816644588670                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              731.196952                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   498171344000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF     37294400000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    581394006750                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    581396539000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                 7401920400                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 4038746250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                8234982600                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               3486201120                       # Energy for write commands per rank (pJ)
+system.physmem_1.actEnergy                 7401549960                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 4038544125                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                8234959200                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               3486194640                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy            72947846400                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           429157184085                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           293662305750                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             818929186605                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              733.242498                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   485776924250                       # Time in different power states
+system.physmem_1.actBackEnergy           429293377035                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           293542830000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             818945301360                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              733.256935                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   485580062750                       # Time in different power states
 system.physmem_1.memoryStateTime::REF     37294400000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    593789084750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    593987729250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               239639085                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         186342301                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14526140                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            130646105                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               122079391                       # Number of BTB hits
+system.cpu.branchPred.lookups               239639355                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         186342486                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14526193                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            130646338                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               122079091                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             93.442809                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                15657029                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             93.442413                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                15657057                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                 15                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups             537                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits                230                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses              307                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          164                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -411,68 +415,103 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       2233721157                       # number of cpu cycles simulated
+system.cpu.numCycles                       2233731337                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                  1544563088                       # Number of instructions committed
 system.cpu.committedOps                    1664032481                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      41470128                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      41470388                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.446183                       # CPI: cycles per instruction
-system.cpu.ipc                               0.691475                       # IPC: instructions per cycle
-system.cpu.tickCycles                      1834122800                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                       399598357                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.446190                       # CPI: cycles per instruction
+system.cpu.ipc                               0.691472                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu              1030178776     61.91%     61.91% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 700322      0.04%     61.95% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                3      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     61.95% # Class of committed instruction
+system.cpu.op_class_0::MemRead              458306334     27.54%     89.49% # Class of committed instruction
+system.cpu.op_class_0::MemWrite             174847046     10.51%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total               1664032481                       # Class of committed instruction
+system.cpu.tickCycles                      1834123667                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                       399607670                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements           9221041                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4085.616187                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           624218895                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          4085.616095                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           624218928                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs           9225137                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             67.665000                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             67.665004                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle        9804990500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4085.616187                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data  4085.616095                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997465                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997465                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          245                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1         1237                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          251                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1         1231                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2         2553                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3           61                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1276841907                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1276841907                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    453887715                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       453887715                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    170331057                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      170331057                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1276841941                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1276841941                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    453887732                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       453887732                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170331073                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170331073                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data            1                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total             1                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     624218772                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        624218772                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    624218773                       # number of overall hits
-system.cpu.dcache.overall_hits::total       624218773                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     624218805                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        624218805                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    624218806                       # number of overall hits
+system.cpu.dcache.overall_hits::total       624218806                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      7334498                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       7334498                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2254990                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2254990                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2254974                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2254974                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data      9589488                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        9589488                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      9589490                       # number of overall misses
-system.cpu.dcache.overall_misses::total       9589490                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 190927662500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 190927662500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 109073789000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 109073789000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 300001451500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 300001451500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 300001451500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 300001451500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    461222213                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    461222213                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      9589472                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9589472                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9589474                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9589474                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 190926660000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 190926660000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 109083916000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 109083916000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 300010576000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 300010576000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 300010576000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 300010576000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    461222230                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    461222230                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            3                       # number of SoftPFReq accesses(hits+misses)
@@ -481,10 +520,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    633808260                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    633808260                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    633808263                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    633808263                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    633808277                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    633808277                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    633808280                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    633808280                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.015902                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.015902                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.013066                       # miss rate for WriteReq accesses
@@ -495,14 +534,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.015130
 system.cpu.dcache.demand_miss_rate::total     0.015130                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.015130                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.015130                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.456072                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.456072                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48369.965720                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48369.965720                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.407624                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31284.407624                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.401100                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31284.401100                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26031.319390                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26031.319390                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48374.799887                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48374.799887                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.411334                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 31285.411334                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 31285.404809                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -511,16 +550,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      3684566                       # number of writebacks
-system.cpu.dcache.writebacks::total           3684566                       # number of writebacks
+system.cpu.dcache.writebacks::writebacks      3684567                       # number of writebacks
+system.cpu.dcache.writebacks::total           3684567                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data          215                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          215                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364137                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total       364137                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       364352                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       364352                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       364352                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       364352                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       364121                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       364121                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       364336                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       364336                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       364336                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       364336                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7334283                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total      7334283                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1890853                       # number of WriteReq MSHR misses
@@ -531,16 +570,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data      9225136
 system.cpu.dcache.demand_mshr_misses::total      9225136                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data      9225137                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total      9225137                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183587623500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 183587623500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84772423500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  84772423500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183586477500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 183586477500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  84779361000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  84779361000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        74000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        74000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268360047000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 268360047000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268360121000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 268360121000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268365838500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 268365838500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268365912500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 268365912500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015902                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.015902                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010956                       # mshr miss rate for WriteReq accesses
@@ -551,69 +590,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014555
 system.cpu.dcache.demand_mshr_miss_rate::total     0.014555                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014555                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.014555                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.434361                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.434361                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44832.900019                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44832.900019                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25031.278109                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25031.278109                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        74000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        74000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.091138                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.091138                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.096006                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.096006                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements                29                       # number of replacements
-system.cpu.icache.tags.tagsinuse           661.384835                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           465281420                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs               820                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          567416.365854                       # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse           660.385482                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           465281510                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs               819                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          568109.291819                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   661.384835                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.322942                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.322942                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024          791                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst   660.385482                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.322454                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.322454                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          790                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           32                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2            5                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          754                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.386230                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         930565300                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        930565300                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    465281420                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       465281420                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     465281420                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        465281420                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    465281420                       # number of overall hits
-system.cpu.icache.overall_hits::total       465281420                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          820                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           820                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          820                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            820                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          820                       # number of overall misses
-system.cpu.icache.overall_misses::total           820                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62291000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62291000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62291000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62291000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62291000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62291000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    465282240                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    465282240                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    465282240                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    465282240                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    465282240                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    465282240                       # number of overall (read+write) accesses
+system.cpu.icache.tags.age_task_id_blocks_1024::4          753                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.385742                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses         930565477                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        930565477                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    465281510                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       465281510                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     465281510                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        465281510                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    465281510                       # number of overall hits
+system.cpu.icache.overall_hits::total       465281510                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          819                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           819                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          819                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            819                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          819                       # number of overall misses
+system.cpu.icache.overall_misses::total           819                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     62402500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     62402500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     62402500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     62402500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     62402500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     62402500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    465282329                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    465282329                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    465282329                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    465282329                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    465282329                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    465282329                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75964.634146                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75964.634146                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75964.634146                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75964.634146                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75964.634146                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75964.634146                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76193.528694                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 76193.528694                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 76193.528694                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 76193.528694                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 76193.528694                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -624,133 +663,133 @@ system.cpu.icache.fast_writes                       0                       # nu
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks           29                       # number of writebacks
 system.cpu.icache.writebacks::total                29                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          820                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          820                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          820                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          820                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          820                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          820                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61471000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     61471000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61471000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     61471000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61471000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     61471000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          819                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          819                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          819                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          819                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          819                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          819                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     61583500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     61583500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     61583500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     61583500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     61583500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     61583500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74964.634146                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74964.634146                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74964.634146                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 74964.634146                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74964.634146                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 74964.634146                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements          2013920                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        31258.306174                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           14509192                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.replacements          2013919                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        31258.258362                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           14509191                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs          2043695                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.099490                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.099489                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle      59769702000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14832.753669                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.505297                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.047209                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.452660                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000809                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.500459                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.953928                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        29775                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           91                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst    26.456768                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 16398.892088                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.452664                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.000807                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.500454                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.953926                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        29776                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1251                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         1250                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3        12849                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::4        15553                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908661                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        151498012                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       151498012                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      3684566                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      3684566                       # number of WritebackDirty hits
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.908691                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        151498004                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       151498004                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      3684567                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      3684567                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks           29                       # number of WritebackClean hits
 system.cpu.l2cache.WritebackClean_hits::total           29                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data      1089694                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total      1089694                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           35                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           35                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6089631                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total      6089631                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           35                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      7179325                       # number of demand (read+write) hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           36                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           36                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6089630                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total      6089630                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           36                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      7179324                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total         7179360                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           35                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      7179325                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst           36                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      7179324                       # number of overall hits
 system.cpu.l2cache.overall_hits::total        7179360                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data       801159                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total       801159                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          785                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total          785                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1244653                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      1244653                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          785                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      2045812                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       2046597                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          785                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      2045812                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      2046597                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  70434494500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  70434494500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     59842000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     59842000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108638363500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 108638363500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     59842000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 179072858000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 179132700000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     59842000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 179072858000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 179132700000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      3684566                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      3684566                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst          783                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total          783                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      1244654                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      1244654                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          783                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2045813                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2046596                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          783                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2045813                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2046596                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  70441435500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  70441435500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     59945000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     59945000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108637226500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 108637226500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     59945000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 179078662000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 179138607000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     59945000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 179078662000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 179138607000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      3684567                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      3684567                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks           29                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::total           29                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data      1890853                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total      1890853                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          820                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total          820                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst          819                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total          819                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      7334284                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total      7334284                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          820                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          819                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data      9225137                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      9225957                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          820                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9225956                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          819                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data      9225137                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      9225957                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9225956                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.423702                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.423702                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.957317                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.957317                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.169703                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.169703                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.957317                       # miss rate for demand accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.956044                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.956044                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.169704                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.169704                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.956044                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.221765                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.221830                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.957317                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.956044                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.221765                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.221830                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87915.750182                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87915.750182                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76231.847134                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76231.847134                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87284.057083                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87284.057083                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76231.847134                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87531.433973                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 87527.099864                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76231.847134                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87531.433973                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 87527.099864                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87924.413880                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87924.413880                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76558.109834                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76558.109834                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87283.073449                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87283.073449                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76558.109834                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87534.228202                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 87530.028887                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76558.109834                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -761,131 +800,127 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks      1050123                       # number of writebacks
 system.cpu.l2cache.writebacks::total          1050123                       # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            4                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total            4                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            5                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            5                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            4                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            5                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          214                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.CleanEvict_mshr_misses::total          214                       # number of CleanEvict MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       801159                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       801159                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          784                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total          784                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst          783                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total          783                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      1244649                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total      1244649                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          784                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          783                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data      2045808                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      2046592                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          784                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2046591                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          783                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data      2045808                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      2046592                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  62422904500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  62422904500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     51986500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     51986500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  96191610000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  96191610000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     51986500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158614514500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 158666501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     51986500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158614514500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 158666501000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total      2046591                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  62429845500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  62429845500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     52115000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     52115000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  96190393500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  96190393500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     52115000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158620239000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 158672354000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     52115000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158620239000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 158672354000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.423702                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.423702                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.956098                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.956098                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.956044                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.956044                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.169703                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.169703                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.956098                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.956044                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.221765                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.221830                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.956098                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.956044                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.221765                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.221830                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77915.750182                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77915.750182                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66309.311224                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66309.311224                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77284.125886                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77284.125886                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66309.311224                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77531.476316                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77527.177376                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66309.311224                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77531.476316                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77527.177376                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77924.413880                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77924.413880                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66558.109834                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66558.109834                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77283.148502                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77283.148502                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66558.109834                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77534.274477                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     18447027                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests     18447026                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests      9221082                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1594                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops         1287                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1281                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         1286                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1280                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            6                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp       7335104                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      4734689                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp       7335103                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      4734690                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean           29                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      6500272                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      6500270                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq      1890853                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp      1890853                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq          820                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq          819                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq      7334284                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1669                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         1667                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     27671315                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          27672984                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54336                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826220992                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          27672982                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        54272                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    826221056                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size::total          826275328                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     2013920                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     11239877                       # Request fanout histogram
+system.cpu.toL2Bus.snoops                     2013919                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     11239875                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean        0.000258                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.016091                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.016088                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           11236984     99.97%     99.97% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1               2887      0.03%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           11236983     99.97%     99.97% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               2886      0.03%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  6      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       11239877                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    12908108500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       11239875                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    12908109000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1230499                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1228500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   13837707496                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   13837707995                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          1.2                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            1245433                       # Transaction distribution
+system.membus.trans_dist::ReadResp            1245432                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty      1050123                       # Transaction distribution
 system.membus.trans_dist::CleanEvict           962724                       # Transaction distribution
 system.membus.trans_dist::ReadExReq            801159                       # Transaction distribution
 system.membus.trans_dist::ReadExResp           801159                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       1245433                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6106031                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                6106031                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198189760                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               198189760                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq       1245432                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      6106029                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                6106029                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    198189696                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               198189696                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           4059439                       # Request fanout histogram
+system.membus.snoop_fanout::samples           4059438                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 4059439    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 4059438    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             4059439                       # Request fanout histogram
-system.membus.reqLayer0.occupancy          8663213500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             4059438                       # Request fanout histogram
+system.membus.reqLayer0.occupancy          8663216000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.8                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        11191513500                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        11191487250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              1.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 659d2c639..ad14d9d64 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,122 +1,122 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.767851                       # Number of seconds simulated
-sim_ticks                                767851412000                       # Number of ticks simulated
-final_tick                               767851412000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.767804                       # Number of seconds simulated
+sim_ticks                                767803843500                       # Number of ticks simulated
+final_tick                               767803843500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  96147                       # Simulator instruction rate (inst/s)
-host_op_rate                                   103584                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               47797800                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 342312                       # Number of bytes of host memory used
-host_seconds                                 16064.58                       # Real time elapsed on the host
+host_inst_rate                                 188017                       # Simulator instruction rate (inst/s)
+host_op_rate                                   202560                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               93463451                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 313392                       # Number of bytes of host memory used
+host_seconds                                  8215.02                       # Real time elapsed on the host
 sim_insts                                  1544563024                       # Number of instructions simulated
 sim_ops                                    1664032416                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst             64960                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         235334976                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher     63685504                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            299085440                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        64960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           64960                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks    104625984                       # Number of bytes written to this memory
-system.physmem.bytes_written::total         104625984                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1015                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data            3677109                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher       995086                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               4673210                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks         1634781                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              1634781                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                84600                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            306485047                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher     82939880                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               389509527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           84600                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              84600                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks         136258112                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              136258112                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks         136258112                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               84600                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           306485047                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher     82939880                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              525767639                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                       4673210                       # Number of read requests accepted
-system.physmem.writeReqs                      1634781                       # Number of write requests accepted
-system.physmem.readBursts                     4673210                       # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts                    1634781                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                298595648                       # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ                    489792                       # Total number of bytes read from write queue
-system.physmem.bytesWritten                 104623680                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                 299085440                       # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys              104625984                       # Total written bytes from the system interface side
-system.physmem.servicedByWrQ                     7653                       # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts                      16                       # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst             65216                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         235320384                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher     63711040                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            299096640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        65216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           65216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks    104697344                       # Number of bytes written to this memory
+system.physmem.bytes_written::total         104697344                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1019                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data            3676881                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher       995485                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               4673385                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks         1635896                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total              1635896                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                84938                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            306485030                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher     82978277                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               389548245                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           84938                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              84938                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks         136359495                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              136359495                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks         136359495                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               84938                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           306485030                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher     82978277                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              525907740                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                       4673385                       # Number of read requests accepted
+system.physmem.writeReqs                      1635896                       # Number of write requests accepted
+system.physmem.readBursts                     4673385                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts                    1635896                       # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM                298598336                       # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ                    498304                       # Total number of bytes read from write queue
+system.physmem.bytesWritten                 104693696                       # Total number of bytes written to DRAM
+system.physmem.bytesReadSys                 299096640                       # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys              104697344                       # Total written bytes from the system interface side
+system.physmem.servicedByWrQ                     7786                       # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts                      26                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0              301092                       # Per bank write bursts
-system.physmem.perBankRdBursts::1              298585                       # Per bank write bursts
-system.physmem.perBankRdBursts::2              284412                       # Per bank write bursts
-system.physmem.perBankRdBursts::3              287553                       # Per bank write bursts
-system.physmem.perBankRdBursts::4              288019                       # Per bank write bursts
-system.physmem.perBankRdBursts::5              285340                       # Per bank write bursts
-system.physmem.perBankRdBursts::6              281024                       # Per bank write bursts
-system.physmem.perBankRdBursts::7              277791                       # Per bank write bursts
-system.physmem.perBankRdBursts::8              293545                       # Per bank write bursts
-system.physmem.perBankRdBursts::9              299289                       # Per bank write bursts
-system.physmem.perBankRdBursts::10             291195                       # Per bank write bursts
-system.physmem.perBankRdBursts::11             297241                       # Per bank write bursts
-system.physmem.perBankRdBursts::12             298946                       # Per bank write bursts
-system.physmem.perBankRdBursts::13             298565                       # Per bank write bursts
-system.physmem.perBankRdBursts::14             293948                       # Per bank write bursts
-system.physmem.perBankRdBursts::15             289012                       # Per bank write bursts
-system.physmem.perBankWrBursts::0              103815                       # Per bank write bursts
-system.physmem.perBankWrBursts::1              101663                       # Per bank write bursts
-system.physmem.perBankWrBursts::2               99081                       # Per bank write bursts
-system.physmem.perBankWrBursts::3               99729                       # Per bank write bursts
-system.physmem.perBankWrBursts::4               98947                       # Per bank write bursts
-system.physmem.perBankWrBursts::5               98825                       # Per bank write bursts
-system.physmem.perBankWrBursts::6              102537                       # Per bank write bursts
-system.physmem.perBankWrBursts::7              104314                       # Per bank write bursts
-system.physmem.perBankWrBursts::8              105187                       # Per bank write bursts
-system.physmem.perBankWrBursts::9              104412                       # Per bank write bursts
-system.physmem.perBankWrBursts::10             101681                       # Per bank write bursts
-system.physmem.perBankWrBursts::11             102588                       # Per bank write bursts
-system.physmem.perBankWrBursts::12             102740                       # Per bank write bursts
-system.physmem.perBankWrBursts::13             102708                       # Per bank write bursts
-system.physmem.perBankWrBursts::14             104126                       # Per bank write bursts
-system.physmem.perBankWrBursts::15             102392                       # Per bank write bursts
+system.physmem.perBankRdBursts::0              301126                       # Per bank write bursts
+system.physmem.perBankRdBursts::1              298685                       # Per bank write bursts
+system.physmem.perBankRdBursts::2              284250                       # Per bank write bursts
+system.physmem.perBankRdBursts::3              287696                       # Per bank write bursts
+system.physmem.perBankRdBursts::4              287908                       # Per bank write bursts
+system.physmem.perBankRdBursts::5              285921                       # Per bank write bursts
+system.physmem.perBankRdBursts::6              280645                       # Per bank write bursts
+system.physmem.perBankRdBursts::7              277366                       # Per bank write bursts
+system.physmem.perBankRdBursts::8              293768                       # Per bank write bursts
+system.physmem.perBankRdBursts::9              299240                       # Per bank write bursts
+system.physmem.perBankRdBursts::10             292091                       # Per bank write bursts
+system.physmem.perBankRdBursts::11             297828                       # Per bank write bursts
+system.physmem.perBankRdBursts::12             299005                       # Per bank write bursts
+system.physmem.perBankRdBursts::13             298032                       # Per bank write bursts
+system.physmem.perBankRdBursts::14             293386                       # Per bank write bursts
+system.physmem.perBankRdBursts::15             288652                       # Per bank write bursts
+system.physmem.perBankWrBursts::0              103980                       # Per bank write bursts
+system.physmem.perBankWrBursts::1              101811                       # Per bank write bursts
+system.physmem.perBankWrBursts::2               99205                       # Per bank write bursts
+system.physmem.perBankWrBursts::3               99712                       # Per bank write bursts
+system.physmem.perBankWrBursts::4               99000                       # Per bank write bursts
+system.physmem.perBankWrBursts::5               99026                       # Per bank write bursts
+system.physmem.perBankWrBursts::6              102693                       # Per bank write bursts
+system.physmem.perBankWrBursts::7              104157                       # Per bank write bursts
+system.physmem.perBankWrBursts::8              105172                       # Per bank write bursts
+system.physmem.perBankWrBursts::9              104159                       # Per bank write bursts
+system.physmem.perBankWrBursts::10             102137                       # Per bank write bursts
+system.physmem.perBankWrBursts::11             102620                       # Per bank write bursts
+system.physmem.perBankWrBursts::12             102863                       # Per bank write bursts
+system.physmem.perBankWrBursts::13             102594                       # Per bank write bursts
+system.physmem.perBankWrBursts::14             104213                       # Per bank write bursts
+system.physmem.perBankWrBursts::15             102497                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    767851370500                       # Total gap between requests
+system.physmem.totGap                    767803802500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                 4673210                       # Read request sizes (log2)
+system.physmem.readPktSize::6                 4673385                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
-system.physmem.writePktSize::6                1634781                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                   2763298                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                   1028318                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                    325143                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                    231238                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                    149204                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                     81551                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                     37590                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                     23700                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                     18069                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9                      4228                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10                     1700                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11                      825                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12                      454                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13                      226                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14                       11                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15                        2                       # What read queue length does an incoming req see
+system.physmem.writePktSize::6                1635896                       # Write request sizes (log2)
+system.physmem.rdQLenPdf::0                   2761676                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                   1029435                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                    325938                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                    231496                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                    148985                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                     81565                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                     37573                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                     23615                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                     17937                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9                      4209                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10                     1691                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11                      802                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12                      456                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13                      219                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14                        2                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
@@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11                        1                       # Wh
 system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15                    25895                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16                    28601                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17                    56060                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18                    73237                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19                    85035                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20                    93837                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21                    99991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22                   103634                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23                   105624                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24                   106179                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25                   107211                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26                   108036                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27                   109230                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28                   110922                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29                   111311                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30                   103575                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31                   100806                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32                   100214                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33                     2991                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34                     1245                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35                      586                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36                      276                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37                      138                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38                       66                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39                       27                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40                       12                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41                        6                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15                    25842                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16                    28487                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17                    55926                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18                    73202                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19                    85102                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20                    93551                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21                   100017                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22                   103625                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23                   105684                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24                   106315                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25                   107141                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26                   108142                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27                   109489                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28                   111392                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29                   111204                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30                   103853                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31                   101152                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32                   100444                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33                     3026                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34                     1226                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35                      559                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36                      257                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37                      119                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38                       52                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39                       23                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40                       15                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41                        5                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::42                        3                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43                        2                       # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
@@ -197,116 +197,120 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples      4241219                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean       95.071143                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      78.963204                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     102.762534                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127        3377855     79.64%     79.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255       665363     15.69%     95.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383        95455      2.25%     97.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511        35191      0.83%     98.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639        22820      0.54%     98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767        12430      0.29%     99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895         7284      0.17%     99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023         5212      0.12%     99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151        19609      0.46%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total        4241219                       # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples         97672                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean        47.767497                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev      100.584321                       # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255           95276     97.55%     97.55% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511          1151      1.18%     98.73% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767           710      0.73%     99.45% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023          401      0.41%     99.86% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1279          104      0.11%     99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1535           19      0.02%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1791            2      0.00%     99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples      4243508                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean       95.037234                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      78.939445                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     102.771916                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127        3380789     79.67%     79.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255       664864     15.67%     95.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383        95298      2.25%     97.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511        35170      0.83%     98.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639        22966      0.54%     98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767        12163      0.29%     99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895         7344      0.17%     99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023         5345      0.13%     99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151        19569      0.46%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total        4243508                       # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples         97753                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean        47.727814                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev      100.001834                       # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255           95363     97.56%     97.56% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511          1154      1.18%     98.74% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-767           681      0.70%     99.43% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-1023          412      0.42%     99.85% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-1279          112      0.11%     99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1280-1535           14      0.01%     99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-1791            8      0.01%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::1792-2047            2      0.00%     99.99% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::2048-2303            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2304-2559            1      0.00%     99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2816-3071            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2560-2815            2      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2816-3071            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3328-3583            1      0.00%    100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3840-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
 system.physmem.rdPerTurnAround::4096-4351            1      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4608-4863            2      0.00%    100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total           97672                       # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples         97672                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean        16.737089                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean       16.693249                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev        1.262570                       # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16              68211     69.84%     69.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17               2039      2.09%     71.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18              18248     18.68%     90.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19               5781      5.92%     96.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20               2040      2.09%     98.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21                736      0.75%     99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22                303      0.31%     99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23                177      0.18%     99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24                 71      0.07%     99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25                 35      0.04%     99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26                 22      0.02%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27                  3      0.00%     99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28                  2      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total           97753                       # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples         97753                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean        16.734412                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean       16.690766                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev        1.259650                       # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16              68350     69.92%     69.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17               1981      2.03%     71.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18              18352     18.77%     90.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19               5702      5.83%     96.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20               2016      2.06%     98.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21                741      0.76%     99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22                311      0.32%     99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23                155      0.16%     99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24                 75      0.08%     99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25                 43      0.04%     99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26                 16      0.02%     99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27                  8      0.01%    100.00% # Writes before turning the bus around for reads
 system.physmem.wrPerTurnAround::29                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32                  2      0.00%    100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total           97672                       # Writes before turning the bus around for reads
-system.physmem.totQLat                   128403949042                       # Total ticks spent queuing
-system.physmem.totMemAccLat              215883142792                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                  23327785000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       27521.68                       # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::35                  1      0.00%    100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total           97753                       # Writes before turning the bus around for reads
+system.physmem.totQLat                   128478496877                       # Total ticks spent queuing
+system.physmem.totMemAccLat              215958478127                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                  23327995000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       27537.41                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  46271.68                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                         388.87                       # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW                         136.26                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                      389.51                       # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys                      136.26                       # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  46287.41                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                         388.90                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW                         136.35                       # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys                      389.55                       # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys                      136.36                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           4.10                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       3.04                       # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite                      1.06                       # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite                      1.07                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.42                       # Average read queue length when enqueuing
-system.physmem.avgWrQLen                        24.90                       # Average write queue length when enqueuing
-system.physmem.readRowHits                    1711348                       # Number of row buffer hits during reads
-system.physmem.writeRowHits                    347723                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   36.68                       # Row buffer hit rate for reads
-system.physmem.writeRowHitRate                  21.27                       # Row buffer hit rate for writes
-system.physmem.avgGap                       121726.77                       # Average gap between requests
-system.physmem.pageHitRate                      32.68                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                15936283440                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                 8695392750                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy               17969468400                       # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy               5241691440                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy            50152152960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy           414929915685                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            96735845250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy             609660749925                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              793.985115                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   158402074288                       # Time in different power states
-system.physmem_0.memoryStateTime::REF     25640160000                       # Time in different power states
+system.physmem.avgWrQLen                        24.85                       # Average write queue length when enqueuing
+system.physmem.readRowHits                    1710736                       # Number of row buffer hits during reads
+system.physmem.writeRowHits                    347188                       # Number of row buffer hits during writes
+system.physmem.readRowHitRate                   36.67                       # Row buffer hit rate for reads
+system.physmem.writeRowHitRate                  21.22                       # Row buffer hit rate for writes
+system.physmem.avgGap                       121694.34                       # Average gap between requests
+system.physmem.pageHitRate                      32.66                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                15941658600                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                 8698325625                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy               17967846000                       # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy               5246104320                       # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy            50149101600                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy           414557114310                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            97034832000                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy             609594982455                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              793.947771                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   158900831773                       # Time in different power states
+system.physmem_0.memoryStateTime::REF     25638600000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT    583806871462                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT    583262954477                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                16127249040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                 8799590250                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy               18421525200                       # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy               5351352480                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy            50152152960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy           410152468095                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy           100926587250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy             609930925275                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              794.336977                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   165409997970                       # Time in different power states
-system.physmem_1.memoryStateTime::REF     25640160000                       # Time in different power states
+system.physmem_1.actEnergy                16139254320                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                 8806140750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy               18423607800                       # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy               5354132400                       # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy            50149101600                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy           410075734410                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy           100965867000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy             609913838280                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              794.363055                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   165472936005                       # Time in different power states
+system.physmem_1.memoryStateTime::REF     25638600000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT    576799157530                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT    576690946995                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups               286283871                       # Number of BP lookups
-system.cpu.branchPred.condPredicted         223409198                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect          14630000                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups            157660833                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits               150354422                       # Number of BTB hits
+system.cpu.branchPred.lookups               286292198                       # Number of BP lookups
+system.cpu.branchPred.condPredicted         223415085                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect          14631198                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups            158639381                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits               150355883                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.365741                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                16641462                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                 64                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             94.778410                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                16642674                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                 61                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups            3027                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits               1888                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             1139                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          136                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -425,128 +429,128 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       1535702825                       # number of cpu cycles simulated
+system.cpu.numCycles                       1535607688                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           13928194                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     2067545272                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   286283871                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          166995884                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                    1507053814                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                29284843                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                  194                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles          878                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                 656961352                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   924                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1535625501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.442414                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.228162                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           13928755                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     2067573004                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   286292198                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          167000445                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                    1506957925                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                29287239                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                  183                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles          992                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                 656968436                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   958                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1535531474                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.442524                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.228151                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                453179554     29.51%     29.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                465452437     30.31%     59.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                101425758      6.60%     66.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                515567752     33.57%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                453078112     29.51%     29.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                465445913     30.31%     59.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                101427094      6.61%     66.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                515580355     33.58%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1535625501                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.186419                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.346319                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 74705832                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             538167437                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 849914387                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              58196125                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               14641720                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             42203366                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   738                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts             2037249572                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              52491206                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               14641720                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                139798655                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               457197163                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          14177                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 837846796                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              86126990                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1976444651                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              26741715                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents              45304447                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 126733                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1592000                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents               25068959                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands          1985917884                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            9128448478                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2432959376                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               137                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total           1535531474                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.186436                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.346420                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 74706893                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             538056624                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 849925630                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              58199384                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               14642943                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             42203258                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   730                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts             2037275151                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              52500118                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles               14642943                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                139803593                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               457092273                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          13624                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 837854747                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              86124294                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1976468269                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              26746953                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents              45300136                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 126625                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1588286                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents               25069373                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands          1985943496                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            9128568325                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2432995559                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               145                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps            1674898945                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                311018939                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                156                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            147                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 111499439                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            542575800                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           199311764                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          26984794                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         29485637                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1948029914                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 213                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1857440521                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued          13485383                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       283997711                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    647527066                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             43                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1535625501                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.209566                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.150575                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                311044551                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                174                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            175                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 111502635                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            542585286                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           199312070                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          26927303                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         29234152                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1948047142                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 231                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1857492479                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued          13497229                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       284014957                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    647584155                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             61                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1535531474                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.209674                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.150607                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           582643896     37.94%     37.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           326148429     21.24%     59.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           378192784     24.63%     83.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           219661214     14.30%     98.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            28973008      1.89%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                6170      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           582548107     37.94%     37.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           326134076     21.24%     59.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           378190631     24.63%     83.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           219663672     14.31%     98.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            28988815      1.89%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                6173      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1535625501                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1535531474                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu               166041601     41.02%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                   1966      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     41.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead              191453028     47.29%     88.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite              47322574     11.69%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu               166038532     40.99%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                   1976      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     40.99% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead              191466165     47.27%     88.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite              47567904     11.74%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1138257310     61.28%     61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               800951      0.04%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1138257084     61.28%     61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               800920      0.04%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.32% # Type of FU issued
@@ -568,88 +572,88 @@ system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.32% # Ty
 system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt              30      0.00%     61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt              31      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMisc             22      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.32% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            532072663     28.65%     89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           186309545     10.03%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            532121986     28.65%     89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           186312436     10.03%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1857440521                       # Type of FU issued
-system.cpu.iq.rate                           1.209505                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                   404819169                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.217945                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         5668810855                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2232040657                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1805715757                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total             1857492479                       # Type of FU issued
+system.cpu.iq.rate                           1.209614                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                   405074577                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.218076                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         5669087998                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2232075127                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1805719723                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                 240                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                240                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           70                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             2262259556                       # Number of integer alu accesses
+system.cpu.iq.fp_inst_queue_writes                252                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           72                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             2262566922                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                     134                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         17798811                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads         17809734                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     84269466                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        66606                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        13290                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     24464719                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     84278952                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        66732                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        13280                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     24465025                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      4470256                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       4868274                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      4505677                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       4870984                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               14641720                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                25371637                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1306573                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1948030205                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles               14642943                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                25375759                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1295309                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1948047519                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             542575800                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            199311764                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                151                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 159252                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents               1145955                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          13290                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        7700252                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      8704527                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             16404779                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1827784428                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             516894749                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          29656093                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts             542585286                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            199312070                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                169                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 159534                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents               1134383                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          13280                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        7701154                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      8705181                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             16406335                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1827826675                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             516940315                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          29665804                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                            78                       # number of nop insts executed
-system.cpu.iew.exec_refs                    698647521                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                229543891                       # Number of branches executed
-system.cpu.iew.exec_stores                  181752772                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.190194                       # Inst execution rate
-system.cpu.iew.wb_sent                     1808752237                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1805715827                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1169206310                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1689633446                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.175824                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.691988                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts       258099424                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                           146                       # number of nop insts executed
+system.cpu.iew.exec_refs                    698692225                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                229542687                       # Number of branches executed
+system.cpu.iew.exec_stores                  181751910                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.190295                       # Inst execution rate
+system.cpu.iew.wb_sent                     1808754463                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1805719795                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1169207800                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1689618799                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.175899                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.691995                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       258113026                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             170                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14629299                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1496131949                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.112223                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.027889                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14630522                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1496036001                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.112294                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.028030                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    915820639     61.21%     61.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    250646763     16.75%     77.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2    110056209      7.36%     85.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     55261288      3.69%     89.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     29350080      1.96%     90.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     34099698      2.28%     93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     24719772      1.65%     94.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     18148053      1.21%     96.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     58029447      3.88%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    915722932     61.21%     61.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    250663462     16.76%     77.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2    110062832      7.36%     85.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     55282207      3.70%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29306686      1.96%     90.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     34079757      2.28%     93.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     24721963      1.65%     94.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     18129916      1.21%     96.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     58066246      3.88%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1496131949                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total   1496036001                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts           1544563042                       # Number of instructions committed
 system.cpu.commit.committedOps             1664032434                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -695,76 +699,76 @@ system.cpu.commit.op_class_0::MemWrite      174847045     10.51%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total        1664032434                       # Class of committed instruction
-system.cpu.commit.bw_lim_events              58029447                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                   3360233761                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3883762364                       # The number of ROB writes
-system.cpu.timesIdled                             834                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           77324                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events              58066246                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                   3360114616                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3883791528                       # The number of ROB writes
+system.cpu.timesIdled                             840                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           76214                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1544563024                       # Number of Instructions Simulated
 system.cpu.committedOps                    1664032416                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.994264                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.994264                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.005769                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.005769                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2175773439                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1261589366                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        40                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                       52                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                6965635020                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                551858996                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               675848866                       # number of misc regfile reads
+system.cpu.cpi                               0.994202                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.994202                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.005832                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.005832                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2175815840                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1261595611                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        42                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                       54                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                6965778765                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                551854660                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               675853701                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    124                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements          17003597                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.964807                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs           638080633                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs          17004109                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             37.525085                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle          77932500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.964807                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.replacements          17003710                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.964650                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs           638076364                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs          17004222                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.524584                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          78426500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.964650                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999931                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999931                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0          408                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          104                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          395                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses        1335734207                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses       1335734207                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data    469362265                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       469362265                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    168718228                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      168718228                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses        1335728390                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses       1335728390                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data    469357603                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       469357603                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    168718615                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      168718615                       # number of WriteReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data           57                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total           57                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     638080493                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        638080493                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    638080493                       # number of overall hits
-system.cpu.dcache.overall_hits::total       638080493                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data     17416613                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total      17416613                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      3867819                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      3867819                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     638076218                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        638076218                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    638076218                       # number of overall hits
+system.cpu.dcache.overall_hits::total       638076218                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     17418310                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      17418310                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      3867432                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      3867432                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            2                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            2                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            4                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            4                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data     21284432                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total       21284432                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data     21284434                       # number of overall misses
-system.cpu.dcache.overall_misses::total      21284434                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 412110560500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 412110560500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 148910053049                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 148910053049                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data     21285742                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       21285742                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     21285744                       # number of overall misses
+system.cpu.dcache.overall_misses::total      21285744                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 411945425500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 148954509432                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       196500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total       196500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 561020613549                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 561020613549                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 561020613549                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 561020613549                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    486778878                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    486778878                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 560899934932                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 560899934932                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 560899934932                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 560899934932                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    486775913                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    486775913                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data            2                       # number of SoftPFReq accesses(hits+misses)
@@ -773,72 +777,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61
 system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    659364925                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    659364925                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    659364927                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    659364927                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035779                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.035779                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022411                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.022411                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    659361960                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    659361960                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    659361962                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    659361962                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.035783                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.035783                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022409                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.022409                       # miss rate for WriteReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::cpu.data            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.SoftPFReq_miss_rate::total            1                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.065574                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.065574                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.032280                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.032280                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.032280                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.032280                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23661.923274                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23661.923274                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38499.747028                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38499.747028                       # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.032282                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.032282                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.032282                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.032282                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        49125                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        49125                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26358.260984                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26358.260984                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26358.258507                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26358.258507                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     20478587                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      3417945                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs            942442                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets           67202                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.729281                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    50.860763                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26350.969345                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26350.966869                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     20530392                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      3397643                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs            943594                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets           67194                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    21.757654                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    50.564678                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks     17003597                       # number of writebacks
-system.cpu.dcache.writebacks::total          17003597                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3150032                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      3150032                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1130287                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1130287                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks     17003710                       # number of writebacks
+system.cpu.dcache.writebacks::total          17003710                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3151672                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3151672                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1129843                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1129843                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            4                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total            4                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      4280319                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      4280319                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      4280319                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      4280319                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14266581                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total     14266581                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737532                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total      2737532                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data      4281515                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      4281515                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      4281515                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      4281515                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data     14266638                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total     14266638                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2737589                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      2737589                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data     17004113                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total     17004113                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data     17004114                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total     17004114                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331850986000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 331850986000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115586978404                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 115586978404                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data     17004227                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total     17004227                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data     17004228                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total     17004228                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        68000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        68000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447437964404                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 447437964404                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447438032404                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 447438032404                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 447484732765                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 447484800765                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.029308                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.029308                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015862                       # mshr miss rate for WriteReq accesses
@@ -849,393 +853,394 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025789
 system.cpu.dcache.demand_mshr_miss_rate::total     0.025789                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025789                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.025789                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23260.722804                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23260.722804                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42223.060189                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42223.060189                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        68000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        68000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26313.513937                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26313.513937                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26313.516388                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26313.516388                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements               586                       # number of replacements
-system.cpu.icache.tags.tagsinuse           444.620453                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs           656959766                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              1072                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          612835.602612                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements               589                       # number of replacements
+system.cpu.icache.tags.tagsinuse           444.836642                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs           656966815                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              1075                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          611131.920930                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   444.620453                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.868399                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.868399                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst   444.836642                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.868822                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.868822                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          486                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1           13                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          442                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1           14                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          441                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.949219                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses        1313923770                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses       1313923770                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst    656959766                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       656959766                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     656959766                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        656959766                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    656959766                       # number of overall hits
-system.cpu.icache.overall_hits::total       656959766                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1583                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1583                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1583                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1583                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1583                       # number of overall misses
-system.cpu.icache.overall_misses::total          1583                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    101448987                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    101448987                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    101448987                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    101448987                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    101448987                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    101448987                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    656961349                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    656961349                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    656961349                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    656961349                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    656961349                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    656961349                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses        1313937945                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses       1313937945                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst    656966815                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       656966815                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     656966815                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        656966815                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    656966815                       # number of overall hits
+system.cpu.icache.overall_hits::total       656966815                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1620                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1620                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1620                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1620                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1620                       # number of overall misses
+system.cpu.icache.overall_misses::total          1620                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     98788987                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     98788987                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     98788987                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     98788987                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     98788987                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     98788987                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    656968435                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    656968435                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    656968435                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    656968435                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    656968435                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    656968435                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000002                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000002                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000002                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000002                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000002                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64086.536323                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 64086.536323                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 64086.536323                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 64086.536323                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 64086.536323                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 64086.536323                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        16918                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets          173                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               189                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               5                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    89.513228                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets    34.600000                       # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 60980.856173                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 60980.856173                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        17260                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          439                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               183                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               8                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    94.316940                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets    54.875000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks          586                       # number of writebacks
-system.cpu.icache.writebacks::total               586                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          509                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          509                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          509                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          509                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          509                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          509                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1074                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1074                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1074                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1074                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1074                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1074                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     74582990                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     74582990                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     74582990                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     74582990                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     74582990                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     74582990                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks          589                       # number of writebacks
+system.cpu.icache.writebacks::total               589                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          544                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          544                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          544                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          544                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          544                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          544                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1076                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1076                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1076                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1076                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1076                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1076                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     73759491                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     73759491                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     73759491                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     73759491                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     73759491                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     73759491                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000002                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000002                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69444.124767                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69444.124767                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69444.124767                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69444.124767                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69444.124767                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69444.124767                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued     11607728                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified     11635838                       # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit        19050                       # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued     11611376                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified     11640224                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit        19566                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull            5                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage      4655842                       # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements          4705864                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        16099.842459                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs           22826032                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs          4721788                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             4.834192                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle      54104143500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 13102.285184                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data     2.119304                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  2995.437971                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.799700                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.000129                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.182827                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.982656                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022          773                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024        15151                       # Occupied blocks per task id
+system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
+system.cpu.l2cache.prefetcher.pfSpanPage      4656640                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements          4706089                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        16099.754607                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs           22829126                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          4722015                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             4.834615                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle      54111720000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data     2.290302                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher  2999.119162                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.799460                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.000140                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.183052                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.982651                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022          829                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        15097                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1          599                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3          172                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0          469                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2950                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4343                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5551                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1838                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022     0.047180                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.924744                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses        552240776                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses       552240776                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks      4834377                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total      4834377                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks     12148517                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total     12148517                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data      1758217                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total      1758217                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           57                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total           57                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11520794                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total     11520794                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst           57                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data     13279011                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total        13279068                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst           57                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data     13279011                       # number of overall hits
-system.cpu.l2cache.overall_hits::total       13279068                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            5                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            5                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       979355                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       979355                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1017                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         1017                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2745743                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total      2745743                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1017                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data      3725098                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total       3726115                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1017                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data      3725098                       # number of overall misses
-system.cpu.l2cache.overall_misses::total      3726115                       # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       100500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total       100500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  98934121000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total  98934121000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     73094500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total     73094500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234186702000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 234186702000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     73094500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 333120823000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 333193917500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     73094500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 333120823000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 333193917500                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks      4834377                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total      4834377                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks     12148517                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total     12148517                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            5                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            5                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737572                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total      2737572                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1074                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         1074                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14266537                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total     14266537                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1074                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data     17004109                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total     17005183                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1074                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data     17004109                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total     17005183                       # number of overall (read+write) accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1          636                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3          191                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0          453                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2943                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         4353                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5523                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1825                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022     0.050598                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.921448                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses        552242422                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses       552242422                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks      4833112                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total      4833112                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks     12149903                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total     12149903                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1757087                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1757087                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst           56                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total           56                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data     11522367                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total     11522367                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           56                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data     13279454                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total        13279510                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           56                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data     13279454                       # number of overall hits
+system.cpu.l2cache.overall_hits::total       13279510                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       980546                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       980546                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         1020                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         1020                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data      2744222                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total      2744222                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1020                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      3724768                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       3725788                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1020                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      3724768                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      3725788                       # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       121000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       121000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  99083213500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  99083213500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst     72272000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total     72272000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     72272000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 333235195500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     72272000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 333235195500                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks      4833112                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total      4833112                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks     12149903                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total     12149903                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            6                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            6                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      2737633                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      2737633                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         1076                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         1076                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data     14266589                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total     14266589                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1076                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data     17004222                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total     17005298                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1076                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data     17004222                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total     17005298                       # number of overall (read+write) accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.357746                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.357746                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.946927                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.946927                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.192460                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.192460                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.946927                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.219070                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.219116                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.946927                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.219070                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.219116                       # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data        20100                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total        20100                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101019.672131                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101019.672131                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71872.664700                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71872.664700                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85290.830934                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85290.830934                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71872.664700                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.056174                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89421.265178                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71872.664700                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89426.056174                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89421.265178                       # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs          398                       # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358173                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.358173                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.947955                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.947955                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.192353                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.192353                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.947955                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.219050                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.219096                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.947955                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.219050                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.219096                       # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383                       # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs           53                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                4                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs                1                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs    99.500000                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs           53                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks      1634781                       # number of writebacks
-system.cpu.l2cache.writebacks::total          1634781                       # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3953                       # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total         3953                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.unused_prefetches            56900                       # number of HardPF blocks evicted w/o reference
+system.cpu.l2cache.writebacks::writebacks      1635896                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1635896                       # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3915                       # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total         3915                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            1                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            1                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45302                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45302                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data        45253                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total        45253                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data        49255                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total        49256                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data        49168                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total        49169                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data        49255                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total        49256                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1144188                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total      1144188                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            5                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       975402                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       975402                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1016                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1016                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2700441                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2700441                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1016                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data      3675843                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total      3676859                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1016                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data      3675843                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1144188                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total      4821047                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  72422793987                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  72422793987                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        70500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        70500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  92707545500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  92707545500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     66931500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     66931500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215168959000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215168959000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     66931500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307876504500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 307943436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     66931500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307876504500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  72422793987                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 380366229987                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data        49168                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total        49169                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher      1145204                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total      1145204                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       976631                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       976631                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         1019                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         1019                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data      2698969                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total      2698969                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1019                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      3675600                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      3676619                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1019                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      3675600                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher      1145204                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      4821823                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  72434619378                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  72434619378                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        85000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        85000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  92854351000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  92854351000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     66085000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     66085000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     66085000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     66085000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  72434619378                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356302                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356302                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.945996                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.945996                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189285                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189285                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.945996                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216174                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.216220                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.945996                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216174                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.356743                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.356743                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.947026                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.947026                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.189181                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.189181                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.947026                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.216158                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.216204                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.947026                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.216158                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.283505                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63296.236271                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        14100                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        14100                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95045.474071                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95045.474071                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65877.460630                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65877.460630                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79679.192769                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79679.192769                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65877.460630                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83756.706829                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83751.766385                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65877.460630                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83756.706829                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78897.017595                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.283548                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests     34009371                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests     17004197                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21289                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops      2918881                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops      2900097                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        18784                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp      14267609                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty      6469158                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean     12169806                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict      5772538                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq      1435459                       # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests     34009604                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests     17004315                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        21284                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops      2918086                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops      2899299                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops        18787                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp      14267664                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty      6469008                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean     12171187                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict      5770180                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq      1436414                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::HardPFResp            9                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp            5                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq      2737572                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp      2737572                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         1074                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq     14266537                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2732                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     51011834                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total          51014566                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       106112                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2176493760                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total         2176599872                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                     8842787                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples     25847966                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.114476                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.320662                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq            6                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp            6                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq      2737633                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp      2737633                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         1076                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq     14266589                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side         2740                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     51012175                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total          51014915                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       106496                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   2176508224                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total         2176614720                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                     8842499                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples     25847794                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.114446                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.320627                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0           22907787     88.63%     88.63% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1            2921395     11.30%     99.93% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              18784      0.07%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0           22908415     88.63%     88.63% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1            2920592     11.30%     99.93% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2              18787      0.07%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total       25847966                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy    34008868522                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total       25847794                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy    34009101529                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          4.4                       # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy        13530                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy        13538                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       1609497                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       1613498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy   25506170491                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy   25506339992                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          3.3                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp            3697667                       # Transaction distribution
-system.membus.trans_dist::WritebackDirty      1634781                       # Transaction distribution
-system.membus.trans_dist::CleanEvict          3002759                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq                5                       # Transaction distribution
-system.membus.trans_dist::ReadExReq            975542                       # Transaction distribution
-system.membus.trans_dist::ReadExResp           975542                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq       3697668                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     13983964                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total               13983964                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    403711360                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total               403711360                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp            3696594                       # Transaction distribution
+system.membus.trans_dist::WritebackDirty      1635896                       # Transaction distribution
+system.membus.trans_dist::CleanEvict          3001813                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
+system.membus.trans_dist::ReadExReq            976790                       # Transaction distribution
+system.membus.trans_dist::ReadExResp           976790                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq       3696595                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port     13984484                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total               13984484                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    403793920                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total               403793920                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples           9310755                       # Request fanout histogram
+system.membus.snoop_fanout::samples           9311100                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                 9310755    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                 9311100    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total             9310755                       # Request fanout histogram
-system.membus.reqLayer0.occupancy         17653458992                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total             9311100                       # Request fanout histogram
+system.membus.reqLayer0.occupancy         17657610874                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
-system.membus.respLayer1.occupancy        25411663187                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy        25413256779                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              3.3                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
index 8b18f9604..6eb6b8f50 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,42 +1,42 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.051911                       # Number of seconds simulated
-sim_ticks                                 51910606500                       # Number of ticks simulated
-final_tick                                51910606500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.051906                       # Number of seconds simulated
+sim_ticks                                 51905634500                       # Number of ticks simulated
+final_tick                                51905634500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 362776                       # Simulator instruction rate (inst/s)
-host_op_rate                                   362776                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              204910533                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303308                       # Number of bytes of host memory used
-host_seconds                                   253.33                       # Real time elapsed on the host
+host_inst_rate                                 327219                       # Simulator instruction rate (inst/s)
+host_op_rate                                   327219                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              184808729                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257300                       # Number of bytes of host memory used
+host_seconds                                   280.86                       # Real time elapsed on the host
 sim_insts                                    91903089                       # Number of instructions simulated
 sim_ops                                      91903089                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            202752                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            202816                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            137664                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               340416                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       202752                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          202752                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3168                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total               340480                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       202816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          202816                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3169                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               2151                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5319                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              3905791                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2651944                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 6557735                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         3905791                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            3905791                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3905791                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2651944                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                6557735                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5319                       # Number of read requests accepted
+system.physmem.num_reads::total                  5320                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              3907399                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2652198                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 6559596                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         3907399                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            3907399                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             3907399                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2652198                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                6559596                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5320                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5319                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5320                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   340416                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   340480                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    340416                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    340480                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
@@ -49,7 +49,7 @@ system.physmem.perBankRdBursts::4                 224                       # Pe
 system.physmem.perBankRdBursts::5                 238                       # Per bank write bursts
 system.physmem.perBankRdBursts::6                 222                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 289                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 251                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 252                       # Per bank write bursts
 system.physmem.perBankRdBursts::9                 282                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                254                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                261                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     51910519000                       # Total gap between requests
+system.physmem.totGap                     51905547000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5319                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5320                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4921                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       379                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4923                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       378                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        19                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          979                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      346.541369                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     213.036393                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     328.369108                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            309     31.56%     31.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          207     21.14%     52.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          105     10.73%     63.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           89      9.09%     72.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           71      7.25%     79.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           31      3.17%     82.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           27      2.76%     85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           27      2.76%     88.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          113     11.54%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            979                       # Bytes accessed per row activation
-system.physmem.totQLat                       35329750                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 135061000                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26595000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        6642.18                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          982                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      346.395112                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     212.989816                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     328.326928                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            308     31.36%     31.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          213     21.69%     53.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          101     10.29%     63.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           90      9.16%     72.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           71      7.23%     79.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           37      3.77%     83.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           21      2.14%     85.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           29      2.95%     88.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          112     11.41%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            982                       # Bytes accessed per row activation
+system.physmem.totQLat                       32661000                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 132411000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26600000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        6139.29                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25392.18                       # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat                  24889.29                       # Average memory access latency per DRAM burst
 system.physmem.avgRdBW                           6.56                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
 system.physmem.avgRdBWSys                        6.56                       # Average system read bandwidth in MiByte/s
@@ -216,70 +216,74 @@ system.physmem.busUtilRead                       0.05                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4332                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4334                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   81.44                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   81.47                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      9759450.84                       # Average gap between requests
-system.physmem.pageHitRate                      81.44                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3507840                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1914000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19835400                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      9756681.77                       # Average gap between requests
+system.physmem.pageHitRate                      81.47                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3515400                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1918125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19983600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_0.refreshEnergy             3390060960                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             1735573905                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            29619608250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              34770500355                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.907919                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    49271583750                       # Time in different power states
+system.physmem_0.actBackEnergy             1736098875                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            29619147750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              34770724710                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.912241                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    49270880000                       # Time in different power states
 system.physmem_0.memoryStateTime::REF      1733160000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       898672500                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       899376250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3848040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2099625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  21216000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3885840                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2120250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  21309600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
 system.physmem_1.refreshEnergy             3390060960                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             1825260840                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            29540935500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              34783420965                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.156855                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    49142724000                       # Time in different power states
+system.physmem_1.actBackEnergy             1812535875                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            29552097750                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              34782010275                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.129676                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    49159142250                       # Time in different power states
 system.physmem_1.memoryStateTime::REF      1733160000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1030067000                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1011440250                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                11441088                       # Number of BP lookups
-system.cpu.branchPred.condPredicted           8207826                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            765853                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              6077536                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 5340604                       # Number of BTB hits
+system.cpu.branchPred.lookups                11440185                       # Number of BP lookups
+system.cpu.branchPred.condPredicted           8207191                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            765027                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              6076858                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 5316207                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.874494                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1173808                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             87.482824                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1173724                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                216                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           26312                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              24255                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             2057                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          983                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     20417089                       # DTB read hits
-system.cpu.dtb.read_misses                      43350                       # DTB read misses
+system.cpu.dtb.read_hits                     20416195                       # DTB read hits
+system.cpu.dtb.read_misses                      43360                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                 20460439                       # DTB read accesses
-system.cpu.dtb.write_hits                     6579898                       # DTB write hits
+system.cpu.dtb.read_accesses                 20459555                       # DTB read accesses
+system.cpu.dtb.write_hits                     6579893                       # DTB write hits
 system.cpu.dtb.write_misses                       278                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 6580176                       # DTB write accesses
-system.cpu.dtb.data_hits                     26996987                       # DTB hits
-system.cpu.dtb.data_misses                      43628                       # DTB misses
+system.cpu.dtb.write_accesses                 6580171                       # DTB write accesses
+system.cpu.dtb.data_hits                     26996088                       # DTB hits
+system.cpu.dtb.data_misses                      43638                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                 27040615                       # DTB accesses
-system.cpu.itb.fetch_hits                    22953519                       # ITB hits
+system.cpu.dtb.data_accesses                 27039726                       # DTB accesses
+system.cpu.itb.fetch_hits                    22951506                       # ITB hits
 system.cpu.itb.fetch_misses                        90                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                22953609                       # ITB accesses
+system.cpu.itb.fetch_accesses                22951596                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,26 +297,61 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                        103821213                       # number of cpu cycles simulated
+system.cpu.numCycles                        103811269                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                    91903089                       # Number of instructions committed
 system.cpu.committedOps                      91903089                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                       2183676                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                       2181586                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.129681                       # CPI: cycles per instruction
-system.cpu.ipc                               0.885205                       # IPC: instructions per cycle
-system.cpu.tickCycles                       102104321                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         1716892                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.129573                       # CPI: cycles per instruction
+system.cpu.ipc                               0.885290                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass             7723353      8.40%      8.40% # Class of committed instruction
+system.cpu.op_class_0::IntAlu                51001454     55.49%     63.90% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 458252      0.50%     64.40% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     64.40% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd               2732553      2.97%     67.37% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                104605      0.11%     67.48% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt               2333953      2.54%     70.02% # Class of committed instruction
+system.cpu.op_class_0::FloatMult               296445      0.32%     70.35% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                754822      0.82%     71.17% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                  318      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc                0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult                0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     71.17% # Class of committed instruction
+system.cpu.op_class_0::MemRead               19996208     21.76%     92.93% # Class of committed instruction
+system.cpu.op_class_0::MemWrite               6501126      7.07%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                 91903089                       # Class of committed instruction
+system.cpu.tickCycles                       102098443                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         1712826                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements               157                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1447.424803                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            26573200                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1447.414267                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            26572424                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              2230                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          11916.233184                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          11915.885202                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1447.424803                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.353375                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.353375                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1447.414267                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.353373                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.353373                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         2073                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           19                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           43                       # Occupied blocks per task id
@@ -320,56 +359,56 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2          227
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          405                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1379                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.506104                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          53155492                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         53155492                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     20075007                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        20075007                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6498193                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6498193                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      26573200                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         26573200                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     26573200                       # number of overall hits
-system.cpu.dcache.overall_hits::total        26573200                       # number of overall hits
+system.cpu.dcache.tags.tag_accesses          53153936                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         53153936                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     20074229                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20074229                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6498195                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6498195                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      26572424                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26572424                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26572424                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26572424                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          521                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           521                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         2910                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         2910                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         3431                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           3431                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         3431                       # number of overall misses
-system.cpu.dcache.overall_misses::total          3431                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     40212500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     40212500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    214034000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    214034000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    254246500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    254246500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    254246500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    254246500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     20075528                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     20075528                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data         2908                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2908                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         3429                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3429                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         3429                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3429                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     40464500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     40464500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    214055500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    214055500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    254520000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    254520000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    254520000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    254520000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20074750                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20074750                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     26576631                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     26576631                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     26576631                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     26576631                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     26575853                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26575853                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     26575853                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26575853                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000026                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000026                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000448                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000448                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000447                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000447                       # miss rate for WriteReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000129                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000129                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000129                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000129                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.202749                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.202749                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 74102.739726                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 74102.739726                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 74102.739726                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 74102.739726                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77666.986564                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 77666.986564                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73609.181568                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73609.181568                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 74225.721785                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 74225.721785                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 74225.721785                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 74225.721785                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -382,12 +421,12 @@ system.cpu.dcache.writebacks::writebacks          107                       # nu
 system.cpu.dcache.writebacks::total               107                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           36                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           36                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1165                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         1165                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         1201                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         1201                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         1201                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         1201                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         1163                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         1163                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         1199                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         1199                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         1199                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         1199                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          485                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          485                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1745                       # number of WriteReq MSHR misses
@@ -396,14 +435,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         2230
 system.cpu.dcache.demand_mshr_misses::total         2230                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         2230                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         2230                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     37107000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     37107000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131706500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    131706500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    168813500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    168813500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    168813500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    168813500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36953000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     36953000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    131397000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    131397000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    168350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    168350000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    168350000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    168350000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000024                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000268                       # mshr miss rate for WriteReq accesses
@@ -412,69 +451,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000084                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75476.504298                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75476.504298                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.121076                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.121076                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.121076                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.121076                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76191.752577                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76191.752577                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75299.140401                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75299.140401                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75493.273543                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75493.273543                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75493.273543                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75493.273543                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             13850                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1640.456655                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            22937703                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             15815                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1450.376415                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements             13853                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1642.330146                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            22935687                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             15818                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1449.973891                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1640.456655                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.801004                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.801004                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1642.330146                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.801919                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.801919                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1965                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          144                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          671                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          672                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3          150                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          946                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.959473                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          45922853                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         45922853                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     22937703                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        22937703                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      22937703                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         22937703                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     22937703                       # number of overall hits
-system.cpu.icache.overall_hits::total        22937703                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        15816                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         15816                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        15816                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          15816                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        15816                       # number of overall misses
-system.cpu.icache.overall_misses::total         15816                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    408931500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    408931500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    408931500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    408931500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    408931500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    408931500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     22953519                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     22953519                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     22953519                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     22953519                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     22953519                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     22953519                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses          45918830                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         45918830                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     22935687                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        22935687                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      22935687                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         22935687                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     22935687                       # number of overall hits
+system.cpu.icache.overall_hits::total        22935687                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        15819                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         15819                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        15819                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          15819                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        15819                       # number of overall misses
+system.cpu.icache.overall_misses::total         15819                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    406827000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    406827000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    406827000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    406827000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    406827000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    406827000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     22951506                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     22951506                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     22951506                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     22951506                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     22951506                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     22951506                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000689                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000689                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000689                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000689                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000689                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000689                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25855.557663                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 25855.557663                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 25855.557663                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 25855.557663                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 25855.557663                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 25855.557663                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25717.618054                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 25717.618054                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25717.618054                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 25717.618054                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25717.618054                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 25717.618054                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -483,135 +522,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        13850                       # number of writebacks
-system.cpu.icache.writebacks::total             13850                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15816                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        15816                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        15816                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        15816                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        15816                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        15816                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    393116500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    393116500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    393116500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    393116500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    393116500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    393116500                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks        13853                       # number of writebacks
+system.cpu.icache.writebacks::total             13853                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15819                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15819                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15819                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15819                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15819                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15819                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    391009000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    391009000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    391009000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    391009000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    391009000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    391009000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000689                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000689                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000689                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000689                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24855.620890                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24855.620890                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24855.620890                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 24855.620890                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24855.620890                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 24855.620890                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24717.681269                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24717.681269                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24717.681269                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 24717.681269                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24717.681269                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 24717.681269                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2477.794192                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              26614                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3666                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             7.259684                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2479.710860                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              26619                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3667                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             7.259067                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.781001                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2100.046719                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   359.966473                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.780381                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2101.965355                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   359.965124                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064088                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.064147                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.010985                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.075616                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3666                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::total     0.075675                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3667                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           65                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          143                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          142                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::2          770                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::3          183                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2505                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111877                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           261827                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          261827                       # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2507                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.111908                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           261876                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          261876                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks          107                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          107                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        13850                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        13850                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        13853                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        13853                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12647                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        12647                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        12649                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        12649                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data           53                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total           53                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        12647                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst        12649                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           79                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total           12726                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        12647                       # number of overall hits
+system.cpu.l2cache.demand_hits::total           12728                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        12649                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           79                       # number of overall hits
-system.cpu.l2cache.overall_hits::total          12726                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          12728                       # number of overall hits
 system.cpu.l2cache.ReadExReq_misses::cpu.data         1719                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total         1719                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3168                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3168                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3169                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3169                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadSharedReq_misses::cpu.data          432                       # number of ReadSharedReq misses
 system.cpu.l2cache.ReadSharedReq_misses::total          432                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3168                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst         3169                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         2151                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5319                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3168                       # number of overall misses
+system.cpu.l2cache.demand_misses::total          5320                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3169                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         2151                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5319                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    128816000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    128816000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    236598500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    236598500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     35817000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     35817000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    236598500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    164633000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    401231500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    236598500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    164633000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    401231500                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total         5320                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    128506000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    128506000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    234465500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    234465500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     35663000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     35663000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    234465500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    164169000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    398634500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    234465500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    164169000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    398634500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks          107                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total          107                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        13850                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        13850                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        13853                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        13853                       # number of WritebackClean accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data         1745                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total         1745                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15815                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        15815                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        15818                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        15818                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          485                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          485                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        15815                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst        15818                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data         2230                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        18045                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        15815                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        18048                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        15818                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data         2230                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        18045                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        18048                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985100                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.985100                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.200316                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.200316                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.200341                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.200341                       # miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.890722                       # miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.890722                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200316                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.200341                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data     0.964574                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.294763                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200316                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.294770                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.200341                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.964574                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.294763                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74936.591041                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74936.591041                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74683.869949                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74683.869949                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82909.722222                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82909.722222                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74683.869949                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76537.889354                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75433.634142                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74683.869949                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76537.889354                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75433.634142                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.294770                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74756.253636                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74756.253636                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73987.219943                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73987.219943                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82553.240741                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82553.240741                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73987.219943                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76322.175732                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 74931.296992                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73987.219943                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76322.175732                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 74931.296992                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -622,113 +661,113 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1719                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total         1719                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3168                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3168                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3169                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3169                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          432                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.ReadSharedReq_mshr_misses::total          432                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3168                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3169                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         2151                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5319                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3168                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5320                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3169                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         2151                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5319                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    111626000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    111626000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    204918500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    204918500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31497000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31497000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    204918500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    143123000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    348041500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    204918500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    143123000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    348041500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total         5320                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    111316000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    111316000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    202775500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    202775500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31343000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31343000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    202775500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    142659000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    345434500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    202775500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    142659000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    345434500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985100                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985100                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.200316                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.200341                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.200341                       # mshr miss rate for ReadCleanReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.890722                       # mshr miss rate for ReadSharedReq accesses
 system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.890722                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.200341                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964574                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.294763                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200316                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.294770                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.200341                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964574                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.294763                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64936.591041                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64936.591041                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64683.869949                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64683.869949                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64683.869949                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66537.889354                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65433.634142                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64683.869949                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66537.889354                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65433.634142                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.294770                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64756.253636                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64756.253636                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63987.219943                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63987.219943                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72553.240741                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72553.240741                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63987.219943                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66322.175732                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64931.296992                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63987.219943                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66322.175732                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64931.296992                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        32052                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests        14007                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        32058                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests        14010                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         16300                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         16303                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          107                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        13850                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        13853                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict           50                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExReq         1745                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadExResp         1745                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        15815                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        15818                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          485                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45480                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        45489                       # Packet count per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4617                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             50097                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1898560                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             50106                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1898944                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       149568                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            2048128                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            2048512                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        18045                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        18048                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              18045    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              18048    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          18045                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       29983000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          18048                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       29989000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      23722500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      23727000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       3345000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3600                       # Transaction distribution
+system.membus.trans_dist::ReadResp               3601                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1719                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1719                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3600                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10638                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10638                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340416                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  340416                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq          3601                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10640                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10640                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       340480                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  340480                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5319                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5320                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5319    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5320    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5319                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6412500                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5320                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6419000                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           28165250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           28167750                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
index 5f230123f..5ce51dae8 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,48 +1,48 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.021917                       # Number of seconds simulated
-sim_ticks                                 21916940500                       # Number of ticks simulated
-final_tick                                21916940500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.021909                       # Number of seconds simulated
+sim_ticks                                 21909208500                       # Number of ticks simulated
+final_tick                                21909208500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 209109                       # Simulator instruction rate (inst/s)
-host_op_rate                                   209109                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               54443336                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303052                       # Number of bytes of host memory used
-host_seconds                                   402.56                       # Real time elapsed on the host
+host_inst_rate                                 236201                       # Simulator instruction rate (inst/s)
+host_op_rate                                   236201                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               61475451                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258056                       # Number of bytes of host memory used
+host_seconds                                   356.39                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
 sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            195712                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            138496                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               334208                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       195712                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          195712                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3058                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5222                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              8929714                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              6319130                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15248844                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         8929714                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            8929714                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             8929714                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             6319130                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               15248844                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5222                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            195968                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            138560                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               334528                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       195968                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          195968                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3062                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2165                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5227                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              8944550                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              6324281                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15268831                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         8944550                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            8944550                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             8944550                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             6324281                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               15268831                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5227                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5222                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5227                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   334208                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   334528                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    334208                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    334528                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
 system.physmem.perBankRdBursts::0                 470                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 290                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 291                       # Per bank write bursts
 system.physmem.perBankRdBursts::2                 302                       # Per bank write bursts
 system.physmem.perBankRdBursts::3                 523                       # Per bank write bursts
 system.physmem.perBankRdBursts::4                 220                       # Per bank write bursts
@@ -50,12 +50,12 @@ system.physmem.perBankRdBursts::5                 223                       # Pe
 system.physmem.perBankRdBursts::6                 218                       # Per bank write bursts
 system.physmem.perBankRdBursts::7                 288                       # Per bank write bursts
 system.physmem.perBankRdBursts::8                 239                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 277                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 278                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                249                       # Per bank write bursts
 system.physmem.perBankRdBursts::11                251                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                396                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                338                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                489                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                395                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                339                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                492                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                449                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     21916845500                       # Total gap between requests
+system.physmem.totGap                     21909113500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5222                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5227                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,12 +90,12 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3268                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                      1190                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       509                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                       237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3269                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                      1202                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       507                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                       232                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                        15                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                         3                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                         2                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          859                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      386.235157                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     231.364931                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     358.000658                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            253     29.45%     29.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          187     21.77%     51.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           82      9.55%     60.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           62      7.22%     67.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           35      4.07%     72.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           38      4.42%     76.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           35      4.07%     80.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           43      5.01%     85.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          124     14.44%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            859                       # Bytes accessed per row activation
-system.physmem.totQLat                       43137250                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 141049750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     26110000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        8260.68                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples          857                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      387.435239                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     233.348968                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     357.138574                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            246     28.70%     28.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          186     21.70%     50.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           85      9.92%     60.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           65      7.58%     67.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           37      4.32%     72.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           35      4.08%     76.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           34      3.97%     80.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           49      5.72%     86.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          120     14.00%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            857                       # Bytes accessed per row activation
+system.physmem.totQLat                       42496500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 140502750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     26135000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        8130.19                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  27010.68                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                          15.25                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26880.19                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                          15.27                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                       15.25                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                       15.27                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.12                       # Data bus utilization in percentage
@@ -216,70 +216,74 @@ system.physmem.busUtilRead                       0.12                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.03                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4353                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4359                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   83.36                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   83.39                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      4197021.35                       # Average gap between requests
-system.physmem.pageHitRate                      83.36                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3122280                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1703625                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  19461000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      4191527.36                       # Average gap between requests
+system.physmem.pageHitRate                      83.39                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3076920                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1678875                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  19468800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             1431087840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy              912284145                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            12346211250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              14713870140                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              671.536045                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    20536521000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF       731640000                       # Time in different power states
+system.physmem_0.refreshEnergy             1430579280                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy              930163050                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            12325856250                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              14710823175                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              671.635656                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    20502630500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF       731380000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT       642620250                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT       668984500                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3311280                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1806750                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  20748000                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3341520                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    1823250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  20771400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             1431087840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy              917766405                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            12341402250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              14716122525                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              671.638843                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    20529652250                       # Time in different power states
-system.physmem_1.memoryStateTime::REF       731640000                       # Time in different power states
+system.physmem_1.refreshEnergy             1430579280                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy              904676355                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            12348213000                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              14709404805                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              671.570899                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    20540502500                       # Time in different power states
+system.physmem_1.memoryStateTime::REF       731380000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       650829750                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT       632027000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                16111441                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          11701383                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect            926235                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups              8627871                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                 7529688                       # Number of BTB hits
+system.cpu.branchPred.lookups                16102191                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          11688099                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect            930994                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups              8963309                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                 7508263                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             87.271680                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1595490                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect                408                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             83.766642                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1594548                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect                465                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups           29370                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits              25724                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             3646                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted          560                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                     24061115                       # DTB read hits
-system.cpu.dtb.read_misses                     205797                       # DTB read misses
-system.cpu.dtb.read_acv                             2                       # DTB read access violations
-system.cpu.dtb.read_accesses                 24266912                       # DTB read accesses
-system.cpu.dtb.write_hits                     7162299                       # DTB write hits
-system.cpu.dtb.write_misses                      1202                       # DTB write misses
+system.cpu.dtb.read_hits                     24064579                       # DTB read hits
+system.cpu.dtb.read_misses                     206327                       # DTB read misses
+system.cpu.dtb.read_acv                             4                       # DTB read access violations
+system.cpu.dtb.read_accesses                 24270906                       # DTB read accesses
+system.cpu.dtb.write_hits                     7168860                       # DTB write hits
+system.cpu.dtb.write_misses                      1193                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                 7163501                       # DTB write accesses
-system.cpu.dtb.data_hits                     31223414                       # DTB hits
-system.cpu.dtb.data_misses                     206999                       # DTB misses
-system.cpu.dtb.data_acv                             2                       # DTB access violations
-system.cpu.dtb.data_accesses                 31430413                       # DTB accesses
-system.cpu.itb.fetch_hits                    15924997                       # ITB hits
-system.cpu.itb.fetch_misses                        77                       # ITB misses
+system.cpu.dtb.write_accesses                 7170053                       # DTB write accesses
+system.cpu.dtb.data_hits                     31233439                       # DTB hits
+system.cpu.dtb.data_misses                     207520                       # DTB misses
+system.cpu.dtb.data_acv                             4                       # DTB access violations
+system.cpu.dtb.data_accesses                 31440959                       # DTB accesses
+system.cpu.itb.fetch_hits                    15932703                       # ITB hits
+system.cpu.itb.fetch_misses                        79                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                15925074                       # ITB accesses
+system.cpu.itb.fetch_accesses                15932782                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -293,236 +297,236 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                  389                       # Number of system calls
-system.cpu.numCycles                         43833882                       # number of cpu cycles simulated
+system.cpu.numCycles                         43818418                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           16631894                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      137948476                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    16111441                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9125178                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      25988337                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 1931044                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles           16643559                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      137979359                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    16102191                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9128535                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      25956071                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 1939868                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                  165                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2266                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles          2614                       # Number of stall cycles due to pending traps
 system.cpu.fetch.IcacheWaitRetryStallCycles            8                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  15924997                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                365277                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           43588192                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              3.164813                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.433150                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                  15932703                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                367699                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           43572351                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.166672                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.433625                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 19406935     44.52%     44.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2620914      6.01%     50.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1337526      3.07%     53.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  1925752      4.42%     58.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3007087      6.90%     64.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1288201      2.96%     67.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1362015      3.12%     71.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   884285      2.03%     73.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 11755477     26.97%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 19392056     44.51%     44.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2618542      6.01%     50.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1330036      3.05%     53.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  1934112      4.44%     58.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3001913      6.89%     64.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1292242      2.97%     67.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1355704      3.11%     70.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   886645      2.03%     73.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 11761101     26.99%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             43588192                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.367557                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        3.147074                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 12849243                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles               8247037                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  19437084                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               2100878                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                 953950                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2651003                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 11975                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              132120831                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                 49966                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                 953950                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 13971462                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 4650933                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          10896                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  20300187                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               3700764                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              128743195                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 69669                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                2038779                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                1385854                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  54667                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands            94545107                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             167268798                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        159787749                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           7481048                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total             43572351                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.367475                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        3.148890                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 12867028                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles               8206518                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  19434084                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               2106116                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                 958605                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2654233                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 11853                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              132149690                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                 49712                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                 958605                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 13986113                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 4641138                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          10397                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  20305818                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               3670280                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              128777120                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 70822                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                2026790                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                1359443                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  54939                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands            94599417                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             167333836                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        159779688                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           7554147                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps              68427361                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 26117746                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps                 26172056                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                950                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            948                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                   8310352                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             26910154                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             8709135                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           3511293                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1618997                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  111850389                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                1284                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  99739394                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            116060                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        27671963                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     21101257                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            895                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      43588192                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.288220                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.099837                       # Number of insts issued each cycle
+system.cpu.rename.tempSerializingInsts            946                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                   8271760                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             26904379                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             8704430                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           3459754                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1614105                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  111855372                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                1919                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  99762873                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            119457                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        27677581                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     21095041                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1530                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      43572351                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.289591                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.099378                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            11252596     25.82%     25.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1             7641941     17.53%     43.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7479961     17.16%     60.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             5717065     13.12%     73.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             4459781     10.23%     83.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2974994      6.83%     90.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2026656      4.65%     95.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1169278      2.68%     98.01% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              865920      1.99%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            11226739     25.77%     25.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1             7658694     17.58%     43.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7470474     17.14%     60.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             5702469     13.09%     73.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             4463101     10.24%     83.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2983064      6.85%     90.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2041659      4.69%     95.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1171062      2.69%     98.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              855089      1.96%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        43588192                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        43572351                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  482625     20.24%     20.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     20.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.24% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                   536      0.02%     20.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                 34267      1.44%     21.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                12315      0.52%     22.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv               1010469     42.37%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 686537     28.79%     93.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                158059      6.63%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  483998     20.16%     20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     20.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                   538      0.02%     20.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     20.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                 34928      1.45%     21.64% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                12187      0.51%     22.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv               1012495     42.17%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     64.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 694978     28.95%     93.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                161680      6.73%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 7      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              60676588     60.84%     60.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               490565      0.49%     61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2839004      2.85%     64.17% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp              115354      0.12%     64.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt             2438838      2.45%     66.73% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult             313701      0.31%     67.05% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv              766055      0.77%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.82% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             24836317     24.90%     92.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             7262646      7.28%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60663003     60.81%     60.81% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               489936      0.49%     61.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.30% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2847512      2.85%     64.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp              115351      0.12%     64.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt             2443315      2.45%     66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult             314199      0.31%     67.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv              765838      0.77%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                319      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             24854808     24.91%     92.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             7268585      7.29%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               99739394                       # Type of FU issued
-system.cpu.iq.rate                           2.275395                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2384808                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.023910                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          229942315                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         130052988                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     89783673                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            15625533                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9511643                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      7169331                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               93775141                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 8349054                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1917494                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               99762873                       # Type of FU issued
+system.cpu.iq.rate                           2.276734                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2400804                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.024065                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          229929463                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         129921880                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     89757813                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            15688895                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9653551                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      7189472                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               93781732                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 8381938                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1923340                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6913956                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11070                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        41356                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2208032                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6908181                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11335                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        40937                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2203327                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        42783                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          1512                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        42874                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          1494                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                 953950                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 3617044                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                465078                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           122781228                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            240022                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              26910154                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              8709135                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1284                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  38486                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                420890                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          41356                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         525280                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       502970                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1028250                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              98428862                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24267391                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1310532                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                 958605                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 3611196                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                465334                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           122779718                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            241439                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              26904379                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              8704430                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1919                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  38387                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                421097                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          40937                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         531949                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       502390                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1034339                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              98437326                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              24271451                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1325547                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      10929555                       # number of nop insts executed
-system.cpu.iew.exec_refs                     31430926                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 12487406                       # Number of branches executed
-system.cpu.iew.exec_stores                    7163535                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.245497                       # Inst execution rate
-system.cpu.iew.wb_sent                       97642114                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      96953004                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  66984387                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  95000699                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       2.211828                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.705094                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        30880053                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                      10922427                       # number of nop insts executed
+system.cpu.iew.exec_refs                     31441543                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 12471856                       # Number of branches executed
+system.cpu.iew.exec_stores                    7170092                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.246483                       # Inst execution rate
+system.cpu.iew.wb_sent                       97646069                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      96947285                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  66976790                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  94960923                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       2.212478                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.705309                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        30878414                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            914663                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     39095166                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.350752                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.921213                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts            919665                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     39078577                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.351750                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.919984                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     14698751     37.60%     37.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8546224     21.86%     59.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3864207      9.88%     69.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      1928510      4.93%     74.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1372257      3.51%     77.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1004424      2.57%     80.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       690640      1.77%     82.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       733325      1.88%     84.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6256828     16.00%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     14680368     37.57%     37.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8532696     21.83%     59.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3879932      9.93%     69.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      1909819      4.89%     74.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1376650      3.52%     77.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1035169      2.65%     80.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       692226      1.77%     82.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       728499      1.86%     84.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6243218     15.98%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     39095166                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total     39078577                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
 system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -568,356 +572,356 @@ system.cpu.commit.op_class_0::MemWrite        6501103      7.07%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total          91903055                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               6256828                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    155620406                       # The number of ROB reads
-system.cpu.rob.rob_writes                   250114778                       # The number of ROB writes
-system.cpu.timesIdled                            4635                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          245690                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6243218                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    155615788                       # The number of ROB reads
+system.cpu.rob.rob_writes                   250112160                       # The number of ROB writes
+system.cpu.timesIdled                            4756                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          246067                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
 system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.520718                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.520718                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.920426                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.920426                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                132978272                       # number of integer regfile reads
-system.cpu.int_regfile_writes                72916434                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   6252591                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  6155476                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                  719142                       # number of misc regfile reads
+system.cpu.cpi                               0.520534                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.520534                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.921103                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.921103                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                133011224                       # number of integer regfile reads
+system.cpu.int_regfile_writes                72905073                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   6263399                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  6178143                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                  719113                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.dcache.tags.replacements               158                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1457.328310                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            28591208                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              2244                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          12741.180036                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1457.375474                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            28588753                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2245                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          12734.411136                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1457.328310                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.355793                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.355793                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         2086                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1457.375474                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.355805                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.355805                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2087                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           25                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          542                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          137                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          536                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4         1389                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.509277                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          57203742                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         57203742                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     22098137                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        22098137                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      6492614                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        6492614                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data          457                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total          457                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits::cpu.data      28590751                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         28590751                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     28590751                       # number of overall hits
-system.cpu.dcache.overall_hits::total        28590751                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data         1051                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total          1051                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         8489                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         8489                       # number of WriteReq misses
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.509521                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          57198843                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         57198843                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     22095651                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        22095651                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6492632                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6492632                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data          470                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total          470                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      28588283                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28588283                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28588283                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28588283                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1074                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1074                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8471                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8471                       # number of WriteReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data         9540                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           9540                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         9540                       # number of overall misses
-system.cpu.dcache.overall_misses::total          9540                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     72374000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     72374000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    544060252                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    544060252                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data         9545                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9545                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9545                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9545                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     71413000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     71413000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    546757246                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    546757246                       # number of WriteReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        85000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total        85000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    616434252                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    616434252                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    616434252                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    616434252                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     22099188                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     22099188                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data    618170246                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    618170246                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    618170246                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    618170246                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22096725                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22096725                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data          458                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total          458                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     28600291                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     28600291                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     28600291                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     28600291                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000048                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000048                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001306                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001306                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002183                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002183                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data          471                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total          471                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     28597828                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     28597828                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     28597828                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     28597828                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000049                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000049                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001303                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001303                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002123                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002123                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_miss_rate::cpu.data     0.000334                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.000334                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000334                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000334                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68862.036156                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 68862.036156                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64090.028507                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 64090.028507                       # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66492.551210                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66492.551210                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64544.592846                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64544.592846                       # average WriteReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        85000                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        85000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 64615.749686                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 64615.749686                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 64615.749686                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 64615.749686                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs        32998                       # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 64763.776427                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 64763.776427                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64763.776427                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64763.776427                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs        32543                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets          127                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs               378                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs               392                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    87.296296                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    83.017857                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets    63.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
 system.cpu.dcache.writebacks::total               108                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          544                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          544                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6753                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         6753                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         7297                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         7297                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         7297                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         7297                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          507                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          507                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1736                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1736                       # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          559                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          559                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6742                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6742                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7301                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7301                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7301                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7301                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          515                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          515                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1729                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1729                       # number of WriteReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2243                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2243                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2243                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2243                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     40562000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     40562000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    135653495                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    135653495                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         2244                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2244                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2244                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2244                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39779500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     39779500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    135885995                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    135885995                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        84000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        84000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    176215495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    176215495                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    176215495                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    176215495                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    175665495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    175665495                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    175665495                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    175665495                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000267                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002183                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002183                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.002123                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.002123                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000078                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000078                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000078                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80003.944773                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80003.944773                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78141.414171                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78141.414171                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77241.747573                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77241.747573                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78592.246964                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78592.246964                       # average WriteReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        84000                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        84000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78562.414177                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78562.414177                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78562.414177                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78562.414177                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78282.306150                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78282.306150                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78282.306150                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              9476                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1601.325936                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            15910465                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             11413                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1394.065101                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              9515                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1600.928709                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            15918297                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             11453                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1389.880119                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1601.325936                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.781897                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.781897                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1937                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_blocks::cpu.inst  1600.928709                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.781703                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.781703                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1938                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1          180                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          752                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4          944                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.945801                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          31861405                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         31861405                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     15910465                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        15910465                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      15910465                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         15910465                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     15910465                       # number of overall hits
-system.cpu.icache.overall_hits::total        15910465                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        14531                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         14531                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        14531                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          14531                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        14531                       # number of overall misses
-system.cpu.icache.overall_misses::total         14531                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    444593500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    444593500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    444593500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    444593500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    444593500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    444593500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     15924996                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     15924996                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     15924996                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     15924996                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     15924996                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     15924996                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000912                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000912                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000912                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000912                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000912                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000912                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30596.208107                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 30596.208107                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 30596.208107                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 30596.208107                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 30596.208107                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 30596.208107                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          865                       # number of cycles access was blocked
+system.cpu.icache.tags.occ_task_id_percent::1024     0.946289                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          31876857                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         31876857                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     15918297                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        15918297                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      15918297                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         15918297                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     15918297                       # number of overall hits
+system.cpu.icache.overall_hits::total        15918297                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        14405                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         14405                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        14405                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          14405                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        14405                       # number of overall misses
+system.cpu.icache.overall_misses::total         14405                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    446574000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    446574000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    446574000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    446574000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    446574000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    446574000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     15932702                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     15932702                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     15932702                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     15932702                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     15932702                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     15932702                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000904                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000904                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000904                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000904                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000904                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000904                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31001.318986                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 31001.318986                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 31001.318986                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 31001.318986                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 31001.318986                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 31001.318986                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs          636                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 4                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs   216.250000                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs          159                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         9476                       # number of writebacks
-system.cpu.icache.writebacks::total              9476                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3118                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3118                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3118                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3118                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3118                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3118                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11413                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        11413                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        11413                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        11413                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        11413                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        11413                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    335979500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    335979500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    335979500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    335979500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    335979500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    335979500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000717                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000717                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000717                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000717                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29438.315955                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29438.315955                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29438.315955                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 29438.315955                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29438.315955                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 29438.315955                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         9515                       # number of writebacks
+system.cpu.icache.writebacks::total              9515                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2951                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2951                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2951                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2951                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2951                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2951                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11454                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        11454                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        11454                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        11454                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        11454                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        11454                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    336702000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    336702000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    336702000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    336702000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    336702000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    336702000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000719                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000719                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000719                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000719                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29396.018858                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29396.018858                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29396.018858                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 29396.018858                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29396.018858                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 29396.018858                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2397.525400                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs              17950                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3578                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             5.016769                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2407.364249                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              18027                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3589                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             5.022848                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks    17.688826                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2004.597838                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   375.238736                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000540                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061175                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.011451                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.073167                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3578                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           71                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          177                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          907                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2421                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109192                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           191642                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          191642                       # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::writebacks    17.652891                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2008.506649                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   381.204708                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000539                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.061295                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.011633                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.073467                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3589                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           72                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          176                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          909                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2431                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.109528                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           192294                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          192294                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks          108                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total          108                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         9476                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         9476                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         9515                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         9515                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8355                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         8355                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         8392                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         8392                       # number of ReadCleanReq hits
 system.cpu.l2cache.ReadSharedReq_hits::cpu.data           54                       # number of ReadSharedReq hits
 system.cpu.l2cache.ReadSharedReq_hits::total           54                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         8355                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst         8392                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.data           80                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            8435                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         8355                       # number of overall hits
+system.cpu.l2cache.demand_hits::total            8472                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8392                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.data           80                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           8435                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1710                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1710                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3058                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3058                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          454                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          454                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3058                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         2164                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5222                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3058                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         2164                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5222                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    132634500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    132634500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    230850500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    230850500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     39300500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     39300500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    230850500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    171935000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    402785500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    230850500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    171935000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    402785500                       # number of overall miss cycles
+system.cpu.l2cache.overall_hits::total           8472                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1703                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1703                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3062                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3062                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          462                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          462                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3062                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2165                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5227                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3062                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2165                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5227                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    132876500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    132876500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    231097000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    231097000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     38506000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     38506000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    231097000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    171382500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    402479500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    231097000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    171382500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    402479500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks          108                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total          108                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         9476                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         9476                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1736                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1736                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11413                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        11413                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          508                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          508                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        11413                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         2244                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total        13657                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        11413                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         2244                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total        13657                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985023                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.985023                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.267940                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.267940                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.893701                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.893701                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.267940                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.964349                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.382368                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.267940                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.964349                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.382368                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77564.035088                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77564.035088                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75490.680183                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75490.680183                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86564.977974                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86564.977974                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75490.680183                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79452.402957                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77132.420529                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75490.680183                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79452.402957                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77132.420529                       # average overall miss latency
+system.cpu.l2cache.WritebackClean_accesses::writebacks         9515                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         9515                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1729                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1729                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        11454                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        11454                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          516                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          516                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        11454                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2245                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        13699                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        11454                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2245                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        13699                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.984962                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.984962                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.267330                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.267330                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.895349                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.895349                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.267330                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.964365                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.381561                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.267330                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.964365                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.381561                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78024.955960                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78024.955960                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75472.566950                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75472.566950                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83346.320346                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83346.320346                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75472.566950                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79160.508083                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77000.095657                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75472.566950                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79160.508083                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77000.095657                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -926,115 +930,115 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1710                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1710                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3058                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3058                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          454                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          454                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3058                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         2164                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5222                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3058                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         2164                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5222                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115534500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115534500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    200270500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    200270500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     34760500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     34760500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    200270500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    150295000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    350565500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    200270500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    150295000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    350565500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985023                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.985023                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.267940                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.267940                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.893701                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.893701                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.267940                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.382368                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.267940                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964349                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.382368                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67564.035088                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67564.035088                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65490.680183                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65490.680183                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76564.977974                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76564.977974                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65490.680183                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69452.402957                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67132.420529                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65490.680183                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69452.402957                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67132.420529                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1703                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1703                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3062                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3062                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          462                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          462                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3062                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2165                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5227                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3062                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2165                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5227                       # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    115846500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    115846500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    200477000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    200477000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     33886000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     33886000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    200477000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    149732500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    350209500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    200477000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    149732500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    350209500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.984962                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.984962                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.267330                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.895349                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.895349                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964365                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.381561                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.267330                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964365                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.381561                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68024.955960                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68024.955960                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65472.566950                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65472.566950                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73346.320346                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73346.320346                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65472.566950                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69160.508083                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67000.095657                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65472.566950                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69160.508083                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67000.095657                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        23291                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         9634                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        23372                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         9673                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp         11921                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp         11969                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty          108                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         9476                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         9515                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict           50                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1736                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1736                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        11413                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          508                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32302                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4646                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             36948                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1336896                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150528                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total            1487424                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq         1729                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1729                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        11454                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          516                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        32422                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4648                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             37070                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1341952                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       150592                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1492544                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples        13657                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples        13699                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::mean               0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::stdev              0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0              13657    100.00%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              13699    100.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            0                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total          13657                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       21229500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          13699                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       21309000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      17119500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      17179500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3366000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3367500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3512                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1710                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1710                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3512                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10444                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  10444                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334208                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  334208                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               3524                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1703                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1703                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          3524                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        10454                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  10454                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       334528                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  334528                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5222                       # Request fanout histogram
+system.membus.snoop_fanout::samples              5227                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5222    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    5227    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5222                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6271000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                5227                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             6276500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           27427000                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           27456000                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
index fae4160aa..21492b1f0 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.130773                       # Number of seconds simulated
-sim_ticks                                130772642500                       # Number of ticks simulated
-final_tick                               130772642500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.130383                       # Number of seconds simulated
+sim_ticks                                130382890500                       # Number of ticks simulated
+final_tick                               130382890500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 239563                       # Simulator instruction rate (inst/s)
-host_op_rate                                   252538                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              181805529                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 322304                       # Number of bytes of host memory used
-host_seconds                                   719.30                       # Real time elapsed on the host
+host_inst_rate                                 248644                       # Simulator instruction rate (inst/s)
+host_op_rate                                   262111                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              188134778                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 275596                       # Number of bytes of host memory used
+host_seconds                                   693.03                       # Real time elapsed on the host
 sim_insts                                   172317810                       # Number of instructions simulated
 sim_ops                                     181650743                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total          138112                       # Nu
 system.physmem.num_reads::cpu.inst               2158                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1708                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3866                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1056123                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               835893                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 1892017                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1056123                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1056123                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1056123                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              835893                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                1892017                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              1059280                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               838392                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 1897672                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         1059280                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            1059280                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             1059280                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              838392                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                1897672                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                          3866                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
 system.physmem.readBursts                        3866                       # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                    130772548000                       # Total gap between requests
+system.physmem.totGap                    130382796000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      3617                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       237                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      3618                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       236                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                        12                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
@@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples          905                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      271.628729                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     179.806384                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     277.022098                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            259     28.62%     28.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          352     38.90%     67.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383           86      9.50%     77.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           59      6.52%     83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           34      3.76%     87.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           21      2.32%     89.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           17      1.88%     91.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           17      1.88%     93.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           60      6.63%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total            905                       # Bytes accessed per row activation
-system.physmem.totQLat                       27654500                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 100142000                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples          915                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      268.939891                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     176.781102                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     276.529935                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            273     29.84%     29.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          347     37.92%     67.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383           83      9.07%     76.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           59      6.45%     83.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           35      3.83%     87.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           24      2.62%     89.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           16      1.75%     91.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           20      2.19%     93.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           58      6.34%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total            915                       # Bytes accessed per row activation
+system.physmem.totQLat                       27071500                       # Total ticks spent queuing
+system.physmem.totMemAccLat                  99559000                       # Total ticks spent from burst creation until serviced by the DRAM
 system.physmem.totBusLat                     19330000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7153.26                       # Average queueing delay per DRAM burst
+system.physmem.avgQLat                        7002.46                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  25903.26                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           1.89                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  25752.46                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           1.90                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        1.89                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        1.90                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.01                       # Data bus utilization in percentage
@@ -216,49 +216,53 @@ system.physmem.busUtilRead                       0.01                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       2957                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       2948                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   76.49                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   76.25                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     33826318.68                       # Average gap between requests
-system.physmem.pageHitRate                      76.49                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    3099600                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    1691250                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  16161600                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     33725503.36                       # Average gap between requests
+system.physmem.pageHitRate                      76.25                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    3144960                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    1716000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  16192800                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             8541265200                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             3568631490                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            75331810500                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              87462659640                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              668.826558                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE   125319167750                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      4366700000                       # Time in different power states
+system.physmem_0.refreshEnergy             8515837200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3562127505                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            75103936500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              87202954965                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              668.831686                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE   124939990750                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      4353700000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1084461000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1087339250                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3727080                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    2033625                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  13782600                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3764880                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2054250                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  13790400                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             8541265200                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3564306900                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            75335612250                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              87460727655                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              668.811714                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE   125325942500                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      4366700000                       # Time in different power states
+system.physmem_1.refreshEnergy             8515837200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3544157970                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            75119701500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              87199306200                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              668.803682                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE   124966482000                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      4353700000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      1077991500                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1060850750                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                49732170                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          39495980                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           5592247                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             24154061                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                23128262                       # Number of BTB hits
+system.cpu.branchPred.lookups                49622074                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          39447439                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5514206                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             24092073                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                22843202                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             95.753099                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1888632                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct             94.816258                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 1888965                       # Number of times the RAS was used to get a target.
 system.cpu.branchPred.RASInCorrect                142                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          213748                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             207973                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses             5775                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        40452                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -377,69 +381,104 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        261545285                       # number of cpu cycles simulated
+system.cpu.numCycles                        260765781                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   172317810                       # Number of instructions committed
 system.cpu.committedOps                     181650743                       # Number of ops (including micro ops) committed
-system.cpu.discardedOps                      11660914                       # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps                      11583006                       # Number of ops (including micro ops) which were discarded before commit
 system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
-system.cpu.cpi                               1.517808                       # CPI: cycles per instruction
-system.cpu.ipc                               0.658845                       # IPC: instructions per cycle
-system.cpu.tickCycles                       255252020                       # Number of cycles that the object actually ticked
-system.cpu.idleCycles                         6293265                       # Total number of cycles that the object has spent stopped
+system.cpu.cpi                               1.513284                       # CPI: cycles per instruction
+system.cpu.ipc                               0.660815                       # IPC: instructions per cycle
+system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
+system.cpu.op_class_0::IntAlu               138988213     76.51%     76.51% # Class of committed instruction
+system.cpu.op_class_0::IntMult                 908940      0.50%     77.01% # Class of committed instruction
+system.cpu.op_class_0::IntDiv                       0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatAdd                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatCmp                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatCvt                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatMult                    0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatDiv                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::FloatSqrt                    0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdAdd                      0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdAddAcc                   0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdAlu                      0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdCmp                      0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdCvt                      0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdMisc                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdMult                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdMultAcc                  0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdShift                    0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdSqrt                     0      0.00%     77.01% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAdd             32754      0.02%     77.03% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     77.03% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCmp            154829      0.09%     77.12% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatCvt            238880      0.13%     77.25% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatDiv             76016      0.04%     77.29% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMisc           437591      0.24%     77.53% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMult           200806      0.11%     77.64% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatMultAcc         71617      0.04%     77.68% # Class of committed instruction
+system.cpu.op_class_0::SimdFloatSqrt              318      0.00%     77.68% # Class of committed instruction
+system.cpu.op_class_0::MemRead               27896144     15.36%     93.04% # Class of committed instruction
+system.cpu.op_class_0::MemWrite              12644635      6.96%    100.00% # Class of committed instruction
+system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
+system.cpu.op_class_0::total                181650743                       # Class of committed instruction
+system.cpu.tickCycles                       254551967                       # Number of cycles that the object actually ticked
+system.cpu.idleCycles                         6213814                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements                42                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1377.707606                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            40756382                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1810                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          22517.338122                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse          1378.689350                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            40754473                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              1811                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          22503.850359                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1377.707606                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.336354                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.336354                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1768                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1378.689350                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.336594                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.336594                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         1769                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           18                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           38                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           83                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::3          271                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1358                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.431641                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          81519460                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         81519460                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28348467                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28348467                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12362639                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12362639                       # number of WriteReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1359                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.431885                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses          81515639                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         81515639                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28346557                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28346557                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12362640                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12362640                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data          462                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total           462                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      40711106                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         40711106                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     40711568                       # number of overall hits
-system.cpu.dcache.overall_hits::total        40711568                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          794                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           794                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1648                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1648                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data      40709197                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40709197                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40709659                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40709659                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          793                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           793                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1647                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1647                       # number of WriteReq misses
 system.cpu.dcache.SoftPFReq_misses::cpu.data            1                       # number of SoftPFReq misses
 system.cpu.dcache.SoftPFReq_misses::total            1                       # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data         2442                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2442                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2443                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2443                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     58082000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     58082000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    126294500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    126294500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    184376500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    184376500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    184376500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    184376500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28349261                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28349261                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         2440                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2440                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2441                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2441                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     59629000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     59629000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    126003000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    126003000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    185632000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    185632000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    185632000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    185632000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28347350                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28347350                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data          463                       # number of SoftPFReq accesses(hits+misses)
@@ -448,10 +487,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     40713548                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     40713548                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     40714011                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     40714011                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     40711637                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     40711637                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     40712100                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     40712100                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000028                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000133                       # miss rate for WriteReq accesses
@@ -462,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000060
 system.cpu.dcache.demand_miss_rate::total     0.000060                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000060                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000060                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73151.133501                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73151.133501                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76635.012136                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76635.012136                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 75502.252252                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 75502.252252                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 75471.346705                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 75471.346705                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75194.199243                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75194.199243                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76504.553734                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 76504.553734                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76078.688525                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76078.688525                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76047.521508                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76047.521508                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -480,34 +519,34 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
 system.cpu.dcache.writebacks::total                16                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           83                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           83                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          550                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          550                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          633                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          633                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          633                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          633                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           82                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           82                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          548                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          548                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          630                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          630                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          630                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          630                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data          711                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          711                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1098                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1098                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1099                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1099                       # number of WriteReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data            1                       # number of SoftPFReq MSHR misses
 system.cpu.dcache.SoftPFReq_mshr_misses::total            1                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         1809                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         1809                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         1810                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         1810                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     51822500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     51822500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85060000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     85060000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data         1810                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1810                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1811                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1811                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     52555500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     52555500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85213000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85213000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        70000                       # number of SoftPFReq MSHR miss cycles
 system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        70000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    136882500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    136882500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    136952500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    136952500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    137768500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    137768500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    137838500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    137838500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
@@ -518,71 +557,71 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000044
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000044                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000044                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72886.779184                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72886.779184                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77468.123862                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77468.123862                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73917.721519                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73917.721519                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77536.851683                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77536.851683                       # average WriteReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        70000                       # average SoftPFReq mshr miss latency
 system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        70000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75667.495854                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 75667.495854                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75664.364641                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 75664.364641                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.193370                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.193370                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76111.816676                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76111.816676                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              2888                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1423.991712                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            71011798                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              4684                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs          15160.503416                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              2881                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1423.942746                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            70779397                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              4677                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs          15133.503742                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1423.991712                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.695308                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.695308                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1423.942746                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.695285                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.695285                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1796                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           51                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          495                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3          123                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          496                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          122                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::4         1068                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024     0.876953                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         142037650                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        142037650                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     71011798                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        71011798                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      71011798                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         71011798                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     71011798                       # number of overall hits
-system.cpu.icache.overall_hits::total        71011798                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         4685                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          4685                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         4685                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           4685                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         4685                       # number of overall misses
-system.cpu.icache.overall_misses::total          4685                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    199916500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    199916500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    199916500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    199916500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    199916500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    199916500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     71016483                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     71016483                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     71016483                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     71016483                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     71016483                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     71016483                       # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses         141572827                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        141572827                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     70779397                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        70779397                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      70779397                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         70779397                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     70779397                       # number of overall hits
+system.cpu.icache.overall_hits::total        70779397                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4678                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4678                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4678                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4678                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4678                       # number of overall misses
+system.cpu.icache.overall_misses::total          4678                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    198432500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    198432500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    198432500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    198432500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    198432500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    198432500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     70784075                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     70784075                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     70784075                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     70784075                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     70784075                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     70784075                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000066                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000066                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000066                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000066                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000066                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42671.611526                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 42671.611526                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 42671.611526                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 42671.611526                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 42671.611526                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 42671.611526                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42418.234288                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 42418.234288                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 42418.234288                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 42418.234288                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 42418.234288                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 42418.234288                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -591,135 +630,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         2888                       # number of writebacks
-system.cpu.icache.writebacks::total              2888                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4685                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         4685                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         4685                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         4685                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         4685                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         4685                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    195232500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    195232500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    195232500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    195232500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    195232500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    195232500                       # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks         2881                       # number of writebacks
+system.cpu.icache.writebacks::total              2881                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4678                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4678                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4678                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4678                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4678                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4678                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    193755500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    193755500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    193755500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    193755500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    193755500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    193755500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000066                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000066                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000066                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41671.824973                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41671.824973                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41671.824973                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 41671.824973                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41671.824973                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 41671.824973                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41418.448055                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41418.448055                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41418.448055                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 41418.448055                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41418.448055                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 41418.448055                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2000.604140                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               5191                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2784                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.864583                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         1999.548128                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               5178                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             2783                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             1.860582                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.029285                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1506.756648                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   490.818207                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks     3.029345                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1506.706963                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   489.811820                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.000092                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.045983                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.014979                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.061054                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2784                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.045981                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.014948                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.061021                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2783                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::0           37                       # Occupied blocks per task id
 system.cpu.l2cache.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          524                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          151                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2004                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.084961                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            76658                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           76658                       # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          526                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          149                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2003                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.084930                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            76554                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           76554                       # Number of data accesses
 system.cpu.l2cache.WritebackDirty_hits::writebacks           16                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total           16                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         2566                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         2566                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         2559                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         2559                       # number of WritebackClean hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2524                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         2524                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data           80                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total           80                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         2524                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           88                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            2612                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         2524                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           88                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           2612                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1090                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1090                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         2517                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         2517                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           81                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           81                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         2517                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           89                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            2606                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2517                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           89                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           2606                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1091                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1091                       # number of ReadExReq misses
 system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2161                       # number of ReadCleanReq misses
 system.cpu.l2cache.ReadCleanReq_misses::total         2161                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          632                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          632                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          631                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          631                       # number of ReadSharedReq misses
 system.cpu.l2cache.demand_misses::cpu.inst         2161                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data         1722                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total          3883                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.inst         2161                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1722                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         3883                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     83327500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     83327500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    161329500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    161329500                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     49900500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     49900500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    161329500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    133228000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    294557500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    161329500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    133228000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    294557500                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     83479000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     83479000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    159937500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    159937500                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     50622000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     50622000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    159937500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    134101000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    294038500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    159937500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    134101000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    294038500                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks           16                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total           16                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         2566                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         2566                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1098                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1098                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4685                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         4685                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         2559                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         2559                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1099                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1099                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         4678                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         4678                       # number of ReadCleanReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          712                       # number of ReadSharedReq accesses(hits+misses)
 system.cpu.l2cache.ReadSharedReq_accesses::total          712                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         4685                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1810                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         6495                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         4685                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1810                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         6495                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992714                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.992714                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.461259                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.461259                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.887640                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.887640                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461259                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.951381                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.597844                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461259                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.951381                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.597844                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76447.247706                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76447.247706                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74655.020824                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74655.020824                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78956.487342                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78956.487342                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74655.020824                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77368.176539                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75858.228174                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74655.020824                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77368.176539                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75858.228174                       # average overall miss latency
+system.cpu.l2cache.demand_accesses::cpu.inst         4678                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1811                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         6489                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4678                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1811                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         6489                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992721                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.992721                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.461950                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.461950                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.886236                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.886236                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.461950                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.950856                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.598397                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.461950                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.950856                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.598397                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76516.040330                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76516.040330                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74010.874595                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74010.874595                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80225.039620                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80225.039620                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74010.874595                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77875.145180                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75724.568633                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74010.874595                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77875.145180                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75724.568633                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -738,97 +777,97 @@ system.cpu.l2cache.demand_mshr_hits::total           16                       #
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.data           14                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total           16                       # number of overall MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1090                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1090                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1091                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1091                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2159                       # number of ReadCleanReq MSHR misses
 system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2159                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          618                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          618                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          617                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          617                       # number of ReadSharedReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.inst         2159                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data         1708                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total         3867                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         2159                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1708                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         3867                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     72427500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     72427500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    139601500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    139601500                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     42758500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     42758500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    139601500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    115186000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    254787500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    139601500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    115186000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    254787500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992714                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992714                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.460832                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.460832                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.867978                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.867978                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.460832                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.595381                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.460832                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943646                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.595381                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66447.247706                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66447.247706                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64660.259379                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64660.259379                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69188.511327                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69188.511327                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64660.259379                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67439.110070                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65887.638997                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64660.259379                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67439.110070                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65887.638997                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     72569000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     72569000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    138134000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    138134000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     43490000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     43490000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    138134000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    116059000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    254193000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    138134000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    116059000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    254193000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992721                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992721                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.461522                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.461522                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.866573                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.866573                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.461522                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943125                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.595932                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.461522                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943125                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.595932                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66516.040330                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66516.040330                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63980.546549                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63980.546549                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70486.223663                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70486.223663                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63980.546549                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67950.234192                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65733.902250                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63980.546549                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67950.234192                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65733.902250                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests         9425                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         3064                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests         9412                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         3057                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests          328                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          5396                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp          5389                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty           16                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         2888                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         2881                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict           26                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1098                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1098                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         4685                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1099                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1099                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         4678                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::ReadSharedReq          712                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12257                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3662                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             15919                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       484608                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116864                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             601472                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        12236                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         3664                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             15900                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       483712                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       116928                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total             600640                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                           0                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         6495                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.071132                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.257064                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples         6489                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.071197                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.257174                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               6033     92.89%     92.89% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                462      7.11%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0               6027     92.88%     92.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1                462      7.12%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           6495                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy        7616500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total           6489                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy        7603000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy       7026998                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy       7016498                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       2721986                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       2723486                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               2776                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1090                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1090                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          2776                       # Transaction distribution
+system.membus.trans_dist::ReadResp               2775                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1091                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1091                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          2775                       # Transaction distribution
 system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port         7732                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_count::total                   7732                       # Packet count per connected master and slave (bytes)
 system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       247424                       # Cumulative packet size per connected master and slave (bytes)
@@ -844,9 +883,9 @@ system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Re
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::total                3866                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             4535500                       # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy             4516500                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           20543250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           20548250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 03798f86c..7b9f789c6 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,65 +1,65 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.085490                       # Number of seconds simulated
-sim_ticks                                 85490431000                       # Number of ticks simulated
-final_tick                                85490431000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.084938                       # Number of seconds simulated
+sim_ticks                                 84937723500                       # Number of ticks simulated
+final_tick                                84937723500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  61561                       # Simulator instruction rate (inst/s)
-host_op_rate                                    64896                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               30544518                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301600                       # Number of bytes of host memory used
-host_seconds                                  2798.88                       # Real time elapsed on the host
+host_inst_rate                                 146803                       # Simulator instruction rate (inst/s)
+host_op_rate                                   154755                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               72367413                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271624                       # Number of bytes of host memory used
+host_seconds                                  1173.70                       # Real time elapsed on the host
 sim_insts                                   172303022                       # Number of instructions simulated
 sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            587136                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            132032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher        70784                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               789952                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       587136                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          587136                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               9174                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2063                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher         1106                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 12343                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              6867856                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1544407                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher       827976                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 9240239                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         6867856                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            6867856                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             6867856                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1544407                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher       827976                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                9240239                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                         12344                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            587328                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            132096                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher        70976                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               790400                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       587328                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          587328                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               9177                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2064                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher         1109                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 12350                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              6914807                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1555210                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher       835624                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 9305641                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         6914807                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            6914807                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             6914807                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1555210                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher       835624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                9305641                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                         12351                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                       12344                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                       12351                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   790016                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   790464                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    790016                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    790464                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                1112                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 371                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                5091                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 435                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                1954                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 426                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 266                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 369                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 265                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 221                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                1113                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 381                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                5089                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 423                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                1959                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 424                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 265                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 373                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 266                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 219                       # Per bank write bursts
 system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                323                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                197                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                324                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                199                       # Per bank write bursts
 system.physmem.perBankRdBursts::13                249                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                227                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                229                       # Per bank write bursts
 system.physmem.perBankRdBursts::15                543                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
@@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     85490422000                       # Total gap between requests
+system.physmem.totGap                     84937714500                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                   12344                       # Read request sizes (log2)
+system.physmem.readPktSize::6                   12351                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -94,15 +94,15 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                     10928                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       977                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                     10935                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       975                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::2                       172                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        83                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                        58                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5                        37                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6                        31                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7                        29                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        85                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                        60                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5                        38                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7                        28                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
@@ -190,29 +190,29 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         7242                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      108.822977                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean      85.142878                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     132.567115                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127           5271     72.78%     72.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255         1523     21.03%     93.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          185      2.55%     96.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           87      1.20%     97.57% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           38      0.52%     98.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           26      0.36%     98.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           17      0.23%     98.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           18      0.25%     98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151           77      1.06%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           7242                       # Bytes accessed per row activation
-system.physmem.totQLat                      167084529                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 398534529                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     61720000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                       13535.69                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         7250                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      108.738207                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean      85.269087                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     131.624325                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127           5249     72.40%     72.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255         1564     21.57%     93.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          167      2.30%     96.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           93      1.28%     97.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           42      0.58%     98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           24      0.33%     98.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           18      0.25%     98.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           21      0.29%     99.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151           72      0.99%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           7250                       # Bytes accessed per row activation
+system.physmem.totQLat                      171430514                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 403011764                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     61755000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                       13879.89                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  32285.69                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           9.24                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  32629.89                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           9.31                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        9.24                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        9.31                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
@@ -220,49 +220,53 @@ system.physmem.busUtilRead                       0.07                       # Da
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
 system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       5095                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       5094                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   41.28                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   41.24                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                      6925666.07                       # Average gap between requests
-system.physmem.pageHitRate                      41.28                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                   48527640                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                   26478375                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  78156000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                      6876990.89                       # Average gap between requests
+system.physmem.pageHitRate                      41.24                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                   48452040                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                   26437125                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  78179400                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5583480240                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy            17009559810                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            36370632750                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              59116834815                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              691.542258                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    60400646468                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2854540000                       # Time in different power states
+system.physmem_0.refreshEnergy             5547372480                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy            16645874445                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            36357960750                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              58704276240                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              691.186004                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    60381088491                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      2836080000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT     22233687032                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT     21718991509                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    6199200                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    3382500                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  17869800                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    6335280                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    3456750                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  17877600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5583480240                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             3325437855                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            48374248500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              57310618095                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              670.413332                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    80466021414                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2854540000                       # Time in different power states
+system.physmem_1.refreshEnergy             5547372480                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             3295031490                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            48069226500                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              56939300100                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              670.405119                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    79958437412                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      2836080000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT      2165082586                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      2138239588                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                85927149                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          68408695                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           6018080                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             40104766                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                39018080                       # Number of BTB hits
+system.cpu.branchPred.lookups                85626366                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          68177013                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           5935452                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             39946926                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                38187698                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             97.290382                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 3702096                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              81897                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct             95.596087                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 3683716                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect              81912                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups          681689                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits             653746                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses            27943                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted        40316                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
@@ -381,233 +385,233 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        170980863                       # number of cpu cycles simulated
+system.cpu.numCycles                        169875448                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles            5755157                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      349305240                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    85927149                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           42720176                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     158448180                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                12049937                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles                 2618                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles            5671940                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      347162762                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    85626366                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           42525160                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     157499775                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                11884731                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles                 2609                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingQuiesceStallCycles           23                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles         3916                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  78960236                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                 19348                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          170234862                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.146650                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             1.050166                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles         3808                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  78326624                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                 18246                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          169120520                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.147875                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             1.049260                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 17669518     10.38%     10.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 30211265     17.75%     28.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 31838913     18.70%     46.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 90515166     53.17%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 17456404     10.32%     10.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 30071791     17.78%     28.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 31598997     18.68%     46.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 89993328     53.21%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            170234862                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.502554                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.042949                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 17700032                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              17289472                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 122672401                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               6722857                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                5850100                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved             11135652                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                190021                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              306632940                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts              27644957                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                5850100                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37887834                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 8551246                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles         582035                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 108933106                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               8430541                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              278671233                       # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts              13418761                       # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents               3051568                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 841704                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                2280860                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                  35921                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents            27095                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           483139430                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1196998780                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        297599206                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           3005965                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            169120520                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.504054                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.043631                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 17509987                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              17244874                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 121866560                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               6731455                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                5767644                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved             11064434                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                189777                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              304997911                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts              27240618                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                5767644                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37477523                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 8502539                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles         578983                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 108355768                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               8438063                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              277420851                       # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts              13180734                       # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents               3058487                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 843003                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                2280960                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                  36243                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents            27083                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           481449871                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1191735135                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        296461789                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups           3004325                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                190162501                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts              23526                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts          23429                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13338905                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             34139598                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            14476816                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           2548575                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1784456                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  264827834                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               45856                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 214914585                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           5192491                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        83237736                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    219939522                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            640                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     170234862                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.262459                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.017804                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                188472942                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts              23603                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts          23603                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13353784                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             33915046                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            14407100                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           2540378                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1803003                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  263798584                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               45955                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 214411803                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           5187874                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        82208585                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    217092419                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            739                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     169120520                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.267805                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.017994                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            53140673     31.22%     31.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            36118420     21.22%     52.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            65796647     38.65%     91.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            13561298      7.97%     99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             1570362      0.92%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5               47243      0.03%    100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 219      0.00%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            52408217     30.99%     30.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            35940187     21.25%     52.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            65510990     38.74%     90.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            13642635      8.07%     99.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             1570936      0.93%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5               47343      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 212      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       170234862                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       169120520                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                35603971     66.12%     66.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                 152944      0.28%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd              1066      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.40% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp             35746      0.07%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt               240      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc              952      0.00%     66.47% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult            34296      0.06%     66.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead               14072260     26.13%     92.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3948482      7.33%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                35659439     66.16%     66.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                 153265      0.28%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd              1066      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp             35730      0.07%     66.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt               240      0.00%     66.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.51% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc              958      0.00%     66.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult            34286      0.06%     66.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.58% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead               14056522     26.08%     92.66% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3955910      7.34%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             167357330     77.87%     77.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               918980      0.43%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.30% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd           33017      0.02%     78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.31% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp          165190      0.08%     78.39% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt          245699      0.11%     78.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc         460522      0.21%     78.76% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult         206694      0.10%     78.85% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             32005177     14.89%     93.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            13374016      6.22%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             166992897     77.88%     77.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               919175      0.43%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd           33015      0.02%     78.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp          165179      0.08%     78.41% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt          245702      0.11%     78.52% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc         460499      0.21%     78.77% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult         206683      0.10%     78.87% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.90% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             31868874     14.86%     93.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            13371819      6.24%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              214914585                       # Type of FU issued
-system.cpu.iq.rate                           1.256951                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    53850162                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.250565                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          655153476                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         346106935                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    204606292                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             3953209                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            2011310                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      1806290                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              266630626                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2134121                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1600828                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              214411803                       # Type of FU issued
+system.cpu.iq.rate                           1.262171                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    53897621                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.251374                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          653076785                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         344050437                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    204251594                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             3952836                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            2009578                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      1806333                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              266175663                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2133761                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1598827                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      6243454                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         7546                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation         6949                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      1832182                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      6018902                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         7447                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation         7034                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      1762466                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        25935                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           794                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        25527                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           769                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                5850100                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 5682962                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 61282                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           264889651                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles                5767644                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 5618767                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 62916                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           263864756                       # Number of instructions dispatched to IQ
 system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              34139598                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             14476816                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts              23448                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   3916                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 54251                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents           6949                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        3234598                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      3248118                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              6482716                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             207529725                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              30719767                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           7384860                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts              33915046                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             14407100                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              23547                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   3855                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 55872                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents           7034                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        3149041                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      3246654                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              6395695                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             207125960                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              30633355                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           7285843                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                         15961                       # number of nop insts executed
-system.cpu.iew.exec_refs                     43859608                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 44936158                       # Number of branches executed
-system.cpu.iew.exec_stores                   13139841                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.213760                       # Inst execution rate
-system.cpu.iew.wb_sent                      206746993                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     206412582                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 129474820                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 221691878                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.207226                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.584031                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        69543013                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop                         20217                       # number of nop insts executed
+system.cpu.iew.exec_refs                     43771495                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 44852998                       # Number of branches executed
+system.cpu.iew.exec_stores                   13138140                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.219281                       # Inst execution rate
+system.cpu.iew.wb_sent                      206368045                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     206057927                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 129397136                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 221651580                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.212994                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.583786                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts        68672645                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           5843212                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    158791205                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.143957                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.645227                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           5760731                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    157823719                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.150970                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.652577                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     73988497     46.59%     46.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     41295308     26.01%     72.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     22556711     14.21%     86.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      9630949      6.07%     92.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3552216      2.24%     95.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2148211      1.35%     96.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1284578      0.81%     97.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       986502      0.62%     97.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      3348233      2.11%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     73232232     46.40%     46.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     41142749     26.07%     72.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     22534270     14.28%     86.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      9514853      6.03%     92.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3552076      2.25%     95.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2143258      1.36%     96.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1327703      0.84%     97.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1008942      0.64%     97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      3367636      2.13%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    158791205                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    157823719                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
 system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -653,382 +657,383 @@ system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               3348233                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    406631126                       # The number of ROB reads
-system.cpu.rob.rob_writes                   513844376                       # The number of ROB writes
-system.cpu.timesIdled                            8957                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          746001                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               3367636                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    404773869                       # The number of ROB reads
+system.cpu.rob.rob_writes                   511956769                       # The number of ROB writes
+system.cpu.timesIdled                            9030                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          754928                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
 system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               0.992327                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.992327                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.007733                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.007733                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                218966992                       # number of integer regfile reads
-system.cpu.int_regfile_writes               114516229                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   2904204                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2441504                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 709589080                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                229556340                       # number of cc regfile writes
-system.cpu.misc_regfile_reads                59312089                       # number of misc regfile reads
+system.cpu.cpi                               0.985911                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.985911                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.014290                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.014290                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                218725741                       # number of integer regfile reads
+system.cpu.int_regfile_writes               114168991                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   2904222                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2441435                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 708194084                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                229512691                       # number of cc regfile writes
+system.cpu.misc_regfile_reads                59249211                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements             72854                       # number of replacements
-system.cpu.dcache.tags.tagsinuse           511.416253                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            41114439                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs             73366                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs            560.401807                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         507537500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data   511.416253                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.998860                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.998860                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements             72581                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.413915                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            41031177                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs             73093                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs            561.355766                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle         508221500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.413915                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.998855                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.998855                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0           56                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1          161                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          231                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3           42                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          229                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses          82527906                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses         82527906                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     28728233                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        28728233                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     12341290                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       12341290                       # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data          361                       # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total           361                       # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses          82360603                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses         82360603                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     28644947                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        28644947                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12341311                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12341311                       # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data          364                       # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total           364                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data        22148                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total        22148                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41069523                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41069523                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41069884                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41069884                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data        89457                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total         89457                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        22997                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        22997                       # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data          118                       # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total          118                       # number of SoftPFReq misses
+system.cpu.dcache.demand_hits::cpu.data      40986258                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         40986258                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     40986622                       # number of overall hits
+system.cpu.dcache.overall_hits::total        40986622                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        89227                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         89227                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        22976                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        22976                       # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data          116                       # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total          116                       # number of SoftPFReq misses
 system.cpu.dcache.LoadLockedReq_misses::cpu.data          259                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total          259                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       112454                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         112454                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       112572                       # number of overall misses
-system.cpu.dcache.overall_misses::total        112572                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1065753500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1065753500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    241354499                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    241354499                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2315500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total      2315500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   1307107999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   1307107999                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   1307107999                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   1307107999                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     28817690                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     28817690                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data       112203                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         112203                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       112319                       # number of overall misses
+system.cpu.dcache.overall_misses::total        112319                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1066843000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1066843000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    241030499                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    241030499                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2297500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total      2297500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   1307873499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   1307873499                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   1307873499                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   1307873499                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     28734174                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     28734174                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data          479                       # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total          479                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data          480                       # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total          480                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     41181977                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     41181977                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     41182456                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     41182456                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003104                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.003104                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001860                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001860                       # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.246347                       # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total     0.246347                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     41098461                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41098461                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41098941                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41098941                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003105                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.003105                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001858                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001858                       # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.241667                       # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total     0.241667                       # miss rate for SoftPFReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011559                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011559                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.002731                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.002731                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002730                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.002730                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002733                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002733                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11913.584180                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11913.584180                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10495.042788                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10495.042788                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8940.154440                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8940.154440                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 11623.490485                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 11623.490485                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 11611.306533                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 11611.306533                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8870.656371                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8870.656371                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 11656.314885                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 11644.276561                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs          166                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets        10450                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets        10738                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             866                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             864                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs           83                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets    12.066975                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    12.428241                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks        72854                       # number of writebacks
-system.cpu.dcache.writebacks::total             72854                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24777                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total        24777                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14426                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        14426                       # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks        72581                       # number of writebacks
+system.cpu.dcache.writebacks::total             72581                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24802                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        24802                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14421                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        14421                       # number of WriteReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          259                       # number of LoadLockedReq MSHR hits
 system.cpu.dcache.LoadLockedReq_mshr_hits::total          259                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data        39203                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total        39203                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data        39203                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total        39203                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64680                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total        64680                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8571                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         8571                       # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          115                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total          115                       # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data        73251                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total        73251                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data        73366                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total        73366                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    654439000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    654439000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     86279999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     86279999                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       978000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       978000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    740718999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    740718999                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    741696999                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    741696999                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002244                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002244                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000693                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000693                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.240084                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.240084                       # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001779                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.001779                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001781                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.001781                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10118.104515                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10118.104515                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10066.503208                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10066.503208                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8504.347826                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8504.347826                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10112.066716                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 10112.066716                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10109.546643                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 10109.546643                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data        39223                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        39223                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        39223                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        39223                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64425                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        64425                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8555                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         8555                       # number of WriteReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          113                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.SoftPFReq_mshr_misses::total          113                       # number of SoftPFReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data        72980                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total        72980                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data        73093                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total        73093                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    653903000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    653903000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85317499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     85317499                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       962000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       962000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    739220499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    739220499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    740182499                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    740182499                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002242                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002242                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000692                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000692                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.235417                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.235417                       # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001776                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.001776                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001778                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.001778                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9972.822794                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9972.822794                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8513.274336                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8513.274336                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements             54401                       # number of replacements
-system.cpu.icache.tags.tagsinuse           510.602972                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            78901806                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs             54913                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           1436.851128                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle       84733597500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst   510.602972                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.997271                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.997271                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements             53623                       # number of replacements
+system.cpu.icache.tags.tagsinuse           510.594536                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            78269055                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs             54135                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           1445.812413                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle       84183071500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   510.594536                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.997255                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.997255                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          103                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4           48                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4           51                       # Occupied blocks per task id
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses         157975329                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses        157975329                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     78901806                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        78901806                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      78901806                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         78901806                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     78901806                       # number of overall hits
-system.cpu.icache.overall_hits::total        78901806                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst        58402                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total         58402                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst        58402                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total          58402                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst        58402                       # number of overall misses
-system.cpu.icache.overall_misses::total         58402                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1157058425                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1157058425                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1157058425                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1157058425                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1157058425                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1157058425                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     78960208                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     78960208                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     78960208                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     78960208                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     78960208                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     78960208                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000740                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000740                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000740                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000740                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000740                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000740                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19811.965772                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 19811.965772                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 19811.965772                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 19811.965772                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 19811.965772                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 19811.965772                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs        72401                       # number of cycles access was blocked
+system.cpu.icache.tags.tag_accesses         156707315                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses        156707315                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     78269055                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        78269055                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      78269055                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         78269055                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     78269055                       # number of overall hits
+system.cpu.icache.overall_hits::total        78269055                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        57535                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         57535                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        57535                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          57535                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        57535                       # number of overall misses
+system.cpu.icache.overall_misses::total         57535                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1155198430                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1155198430                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1155198430                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1155198430                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1155198430                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1155198430                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     78326590                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     78326590                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     78326590                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     78326590                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     78326590                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     78326590                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000735                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000735                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000735                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000735                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000735                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000735                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20078.185974                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 20078.185974                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 20078.185974                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 20078.185974                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 20078.185974                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs        73195                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets           27                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs              3397                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs              3246                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs    21.313218                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    22.549291                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets    13.500000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks        54401                       # number of writebacks
-system.cpu.icache.writebacks::total             54401                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3488                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         3488                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         3488                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         3488                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         3488                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         3488                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54914                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total        54914                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst        54914                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total        54914                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst        54914                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total        54914                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1043630451                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   1043630451                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1043630451                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   1043630451                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1043630451                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   1043630451                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000695                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000695                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000695                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000695                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000695                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000695                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19004.815730                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19004.815730                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19004.815730                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 19004.815730                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19004.815730                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 19004.815730                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks        53623                       # number of writebacks
+system.cpu.icache.writebacks::total             53623                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3399                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         3399                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         3399                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         3399                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         3399                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         3399                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54136                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        54136                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        54136                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        54136                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        54136                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        54136                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1039886452                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1039886452                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1039886452                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1039886452                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1039886452                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1039886452                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000691                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000691                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000691                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued         9281                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified         9281                       # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued         9269                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified         9269                       # number of prefetch candidates identified
 system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
 system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
 system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage         1359                       # number of prefetches not generated due to page crossing
+system.cpu.l2cache.prefetcher.pfSpanPage         1371                       # number of prefetches not generated due to page crossing
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2148.551192                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs             159756                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3199                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs            49.939356                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2141.370901                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs             157591                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3198                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            49.277986                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks  1987.164357                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   161.386835                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.121287                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009850                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.131137                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks  1986.257511                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   155.113391                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.121232                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009467                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.130699                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1022          254                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2945                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1           15                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2           83                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4          156                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           81                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          193                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          854                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          163                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1654                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         2944                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1           24                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2           87                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4          141                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          856                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          162                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1653                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015503                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.179749                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses          3989175                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses         3989175                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks        64840                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total        64840                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks        51941                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total        51941                       # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data         8403                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total         8403                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        45734                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total        45734                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data        62891                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total        62891                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst        45734                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data        71294                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          117028                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst        45734                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data        71294                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         117028                       # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data          237                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total          237                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9180                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         9180                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1835                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total         1835                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         9180                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         2072                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         11252                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         9180                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         2072                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        11252                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     19043000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     19043000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    687767000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    687767000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    141031000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total    141031000                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    687767000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    160074000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    847841000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    687767000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    160074000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    847841000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks        64840                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total        64840                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks        51941                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total        51941                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         8640                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         8640                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54914                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total        54914                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64726                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total        64726                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst        54914                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data        73366                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       128280                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst        54914                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data        73366                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       128280                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027431                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.027431                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.167170                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.167170                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.028350                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.028350                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.167170                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.028242                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.087714                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167170                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.028242                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.087714                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80350.210970                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80350.210970                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74920.152505                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74920.152505                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76856.130790                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76856.130790                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74920.152505                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77255.791506                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75350.248845                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74920.152505                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77255.791506                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75350.248845                       # average overall miss latency
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.179688                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses          3955418                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses         3955418                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks        64698                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total        64698                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks        51033                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total        51033                       # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         8387                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         8387                       # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        44953                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total        44953                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data        62632                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total        62632                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        44953                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        71019                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          115972                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        44953                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        71019                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         115972                       # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data          235                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          235                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9183                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         9183                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1839                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total         1839                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         9183                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2074                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         11257                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         9183                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2074                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        11257                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     18101500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     18101500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    689865000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    689865000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    142794500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total    142794500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    689865000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    160896000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    850761000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    689865000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    160896000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    850761000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks        64698                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total        64698                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks        51033                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total        51033                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         8622                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         8622                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54136                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total        54136                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64471                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total        64471                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        54136                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data        73093                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       127229                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        54136                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data        73093                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       127229                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027256                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.027256                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.169628                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.169628                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.028524                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.028524                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.169628                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.028375                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.088478                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.169628                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.028375                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.088478                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77027.659574                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77027.659574                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75124.142437                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75124.142437                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77647.906471                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77647.906471                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75124.142437                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77577.627772                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75576.174825                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75124.142437                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77577.627772                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75576.174825                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1041,136 +1046,136 @@ system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1
 system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
 system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            8                       # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total            8                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            9                       # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total            9                       # number of ReadSharedReq MSHR hits
 system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         2046                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total         2046                       # number of HardPFReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          236                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total          236                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9175                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9175                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1827                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1827                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         9175                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         2063                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        11238                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         9175                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         2063                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         2046                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        13284                       # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     66908651                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     66908651                       # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     17421000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     17421000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    632417000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    632417000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    129587000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    129587000                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    632417000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    147008000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    779425000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    632417000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    147008000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     66908651                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    846333651                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         2007                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total         2007                       # number of HardPFReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          234                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total          234                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9178                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9178                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1830                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1830                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         9178                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2064                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        11242                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         9178                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2064                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         2007                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        13249                       # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     68828649                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     68828649                       # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     16491500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     16491500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    634496500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    634496500                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    131272000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    131272000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    634496500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    147763500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    782260000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    634496500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    147763500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     68828649                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    851088649                       # number of overall MSHR miss cycles
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
 system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027315                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027315                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.167079                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.167079                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.028227                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.028227                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.167079                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.028119                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.087605                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167079                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028119                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027140                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027140                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.169536                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.169536                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.028385                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.028385                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.169536                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.028238                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.088360                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.169536                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028238                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.103555                       # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 32702.175464                       # average HardPFReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73817.796610                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73817.796610                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68928.283379                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68928.283379                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70928.845101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70928.845101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68928.283379                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71259.331071                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69356.202171                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68928.283379                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71259.331071                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 32702.175464                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63710.753613                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.104135                       # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469                       # average HardPFReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests       255535                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests       127274                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10474                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops        11941                       # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3419                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops         8522                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp        119639                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty        64840                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean        62415                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict        11001                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq         2383                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         8640                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         8640                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq        54914                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq        64726                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       164228                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       219586                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total            383814                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6996096                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9358080                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total           16354176                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                       13384                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples       141664                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.218517                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.539520                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_filter.tot_requests       253433                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       126224                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10473                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops        11905                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3377                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops         8528                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp        118606                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty        64698                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean        61506                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict        11007                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq         2350                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         8622                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         8622                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq        54136                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq        64471                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       161894                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       218767                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total            380661                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6896512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9323136                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total           16219648                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                       13357                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples       140586                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.219979                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.541213                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0             119230     84.16%     84.16% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1              13912      9.82%     93.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2               8522      6.02%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             118188     84.07%     84.07% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1              13870      9.87%     93.93% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2               8528      6.07%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total         141664                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy      255022500                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total         140586                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy      252920500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      82377983                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      81207989                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy     110053990                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy     109644490                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp              12107                       # Transaction distribution
-system.membus.trans_dist::ReadExReq               236                       # Transaction distribution
-system.membus.trans_dist::ReadExResp              236                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq         12108                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        24687                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  24687                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       789952                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  789952                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp              12116                       # Transaction distribution
+system.membus.trans_dist::ReadExReq               234                       # Transaction distribution
+system.membus.trans_dist::ReadExResp              234                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq         12117                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        24701                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  24701                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       790400                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  790400                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples             12344                       # Request fanout histogram
+system.membus.snoop_fanout::samples             12351                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                   12344    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                   12351    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total               12344                       # Request fanout histogram
-system.membus.reqLayer0.occupancy            15598659                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total               12351                       # Request fanout histogram
+system.membus.reqLayer0.occupancy            15618188                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           66476550                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           66520835                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index ed3dbc17c..f0a8cbf5a 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -1,62 +1,62 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.079141                       # Number of seconds simulated
-sim_ticks                                 79140979500                       # Number of ticks simulated
-final_tick                                79140979500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.103324                       # Number of seconds simulated
+sim_ticks                                103324153500                       # Number of ticks simulated
+final_tick                               103324153500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  47467                       # Simulator instruction rate (inst/s)
-host_op_rate                                    79560                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               28443866                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 336904                       # Number of bytes of host memory used
-host_seconds                                  2782.36                       # Real time elapsed on the host
+host_inst_rate                                  72241                       # Simulator instruction rate (inst/s)
+host_op_rate                                   121082                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56516511                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 307592                       # Number of bytes of host memory used
+host_seconds                                  1828.21                       # Real time elapsed on the host
 sim_insts                                   132071192                       # Number of instructions simulated
 sim_ops                                     221363384                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.bytes_read::cpu.inst            221376                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125056                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               346432                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221376                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3459                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1954                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5413                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2797236                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1580167                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4377403                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2797236                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2797236                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2797236                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1580167                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4377403                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs                          5413                       # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst            231488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            130496                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               361984                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       231488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          231488                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3617                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2039                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5656                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2240405                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1262977                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3503382                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2240405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2240405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2240405                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1262977                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3503382                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs                          5656                       # Number of read requests accepted
 system.physmem.writeReqs                            0                       # Number of write requests accepted
-system.physmem.readBursts                        5413                       # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts                        5656                       # Number of DRAM read bursts, including those serviced by the write queue
 system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM                   346432                       # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM                   361984                       # Total number of bytes read from DRAM
 system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
 system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
-system.physmem.bytesReadSys                    346432                       # Total read bytes from the system interface side
+system.physmem.bytesReadSys                    361984                       # Total read bytes from the system interface side
 system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
 system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
 system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
 system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0                 298                       # Per bank write bursts
-system.physmem.perBankRdBursts::1                 346                       # Per bank write bursts
-system.physmem.perBankRdBursts::2                 461                       # Per bank write bursts
-system.physmem.perBankRdBursts::3                 349                       # Per bank write bursts
-system.physmem.perBankRdBursts::4                 340                       # Per bank write bursts
-system.physmem.perBankRdBursts::5                 326                       # Per bank write bursts
-system.physmem.perBankRdBursts::6                 402                       # Per bank write bursts
-system.physmem.perBankRdBursts::7                 384                       # Per bank write bursts
-system.physmem.perBankRdBursts::8                 341                       # Per bank write bursts
-system.physmem.perBankRdBursts::9                 281                       # Per bank write bursts
-system.physmem.perBankRdBursts::10                239                       # Per bank write bursts
-system.physmem.perBankRdBursts::11                285                       # Per bank write bursts
-system.physmem.perBankRdBursts::12                220                       # Per bank write bursts
-system.physmem.perBankRdBursts::13                466                       # Per bank write bursts
-system.physmem.perBankRdBursts::14                389                       # Per bank write bursts
-system.physmem.perBankRdBursts::15                286                       # Per bank write bursts
+system.physmem.perBankRdBursts::0                 310                       # Per bank write bursts
+system.physmem.perBankRdBursts::1                 382                       # Per bank write bursts
+system.physmem.perBankRdBursts::2                 476                       # Per bank write bursts
+system.physmem.perBankRdBursts::3                 358                       # Per bank write bursts
+system.physmem.perBankRdBursts::4                 362                       # Per bank write bursts
+system.physmem.perBankRdBursts::5                 335                       # Per bank write bursts
+system.physmem.perBankRdBursts::6                 419                       # Per bank write bursts
+system.physmem.perBankRdBursts::7                 385                       # Per bank write bursts
+system.physmem.perBankRdBursts::8                 389                       # Per bank write bursts
+system.physmem.perBankRdBursts::9                 295                       # Per bank write bursts
+system.physmem.perBankRdBursts::10                260                       # Per bank write bursts
+system.physmem.perBankRdBursts::11                270                       # Per bank write bursts
+system.physmem.perBankRdBursts::12                228                       # Per bank write bursts
+system.physmem.perBankRdBursts::13                484                       # Per bank write bursts
+system.physmem.perBankRdBursts::14                420                       # Per bank write bursts
+system.physmem.perBankRdBursts::15                283                       # Per bank write bursts
 system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
 system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
@@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14                  0                       # Pe
 system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
 system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
 system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
-system.physmem.totGap                     79140890500                       # Total gap between requests
+system.physmem.totGap                    103323899000                       # Total gap between requests
 system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
 system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
-system.physmem.readPktSize::6                    5413                       # Read request sizes (log2)
+system.physmem.readPktSize::6                    5656                       # Read request sizes (log2)
 system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
@@ -90,11 +90,11 @@ system.physmem.writePktSize::3                      0                       # Wr
 system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
 system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
-system.physmem.rdQLenPdf::0                      4301                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1                       904                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2                       176                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3                        27                       # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4                         4                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0                      4508                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1                       949                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2                       169                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3                        23                       # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
 system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
@@ -186,311 +186,316 @@ system.physmem.wrQLenPdf::60                        0                       # Wh
 system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
 system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples         1107                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean      311.790425                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean     180.924163                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev     329.273428                       # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127            441     39.84%     39.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255          229     20.69%     60.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383          106      9.58%     70.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511           59      5.33%     75.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639           51      4.61%     80.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767           54      4.88%     84.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895           23      2.08%     86.99% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023           18      1.63%     88.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151          126     11.38%    100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total           1107                       # Bytes accessed per row activation
-system.physmem.totQLat                       40702000                       # Total ticks spent queuing
-system.physmem.totMemAccLat                 142195750                       # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat                     27065000                       # Total ticks spent in databus transfers
-system.physmem.avgQLat                        7519.31                       # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples         1264                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean      286.278481                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean     164.439317                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev     318.670037                       # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127            554     43.83%     43.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255          264     20.89%     64.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383          105      8.31%     73.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511           69      5.46%     78.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639           45      3.56%     82.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767           57      4.51%     86.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895           28      2.22%     88.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023           17      1.34%     90.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151          125      9.89%    100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total           1264                       # Bytes accessed per row activation
+system.physmem.totQLat                       43672750                       # Total ticks spent queuing
+system.physmem.totMemAccLat                 149722750                       # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat                     28280000                       # Total ticks spent in databus transfers
+system.physmem.avgQLat                        7721.49                       # Average queueing delay per DRAM burst
 system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat                  26269.31                       # Average memory access latency per DRAM burst
-system.physmem.avgRdBW                           4.38                       # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat                  26471.49                       # Average memory access latency per DRAM burst
+system.physmem.avgRdBW                           3.50                       # Average DRAM read bandwidth in MiByte/s
 system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys                        4.38                       # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys                        3.50                       # Average system read bandwidth in MiByte/s
 system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
 system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
 system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
 system.physmem.busUtilRead                       0.03                       # Data bus utilization in percentage for reads
 system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen                         1.14                       # Average read queue length when enqueuing
+system.physmem.avgRdQLen                         1.06                       # Average read queue length when enqueuing
 system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
-system.physmem.readRowHits                       4302                       # Number of row buffer hits during reads
+system.physmem.readRowHits                       4391                       # Number of row buffer hits during reads
 system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
-system.physmem.readRowHitRate                   79.48                       # Row buffer hit rate for reads
+system.physmem.readRowHitRate                   77.63                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
-system.physmem.avgGap                     14620522.91                       # Average gap between requests
-system.physmem.pageHitRate                      79.48                       # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy                    4898880                       # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy                    2673000                       # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy                  22659000                       # Energy for read commands per rank (pJ)
+system.physmem.avgGap                     18268016.09                       # Average gap between requests
+system.physmem.pageHitRate                      77.63                       # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy                    5624640                       # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy                    3069000                       # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy                  23610600                       # Energy for read commands per rank (pJ)
 system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy             5169003840                       # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy             2477527515                       # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy            45310553250                       # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy              52987315485                       # Total energy per rank (pJ)
-system.physmem_0.averagePower              669.541483                       # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE    75375284000                       # Time in different power states
-system.physmem_0.memoryStateTime::REF      2642640000                       # Time in different power states
+system.physmem_0.refreshEnergy             6748591200                       # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy             3147948405                       # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy            59232949500                       # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy              69161793345                       # Total energy per rank (pJ)
+system.physmem_0.averagePower              669.369133                       # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE    98535205500                       # Time in different power states
+system.physmem_0.memoryStateTime::REF      3450200000                       # Time in different power states
 system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_0.memoryStateTime::ACT      1122708000                       # Time in different power states
+system.physmem_0.memoryStateTime::ACT      1338454000                       # Time in different power states
 system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.physmem_1.actEnergy                    3470040                       # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy                    1893375                       # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy                  19406400                       # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy                    3931200                       # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy                    2145000                       # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy                  20490600                       # Energy for read commands per rank (pJ)
 system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy             5169003840                       # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy             2315256210                       # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy            45452899500                       # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy              52961929365                       # Total energy per rank (pJ)
-system.physmem_1.averagePower              669.220665                       # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE    75612477000                       # Time in different power states
-system.physmem_1.memoryStateTime::REF      2642640000                       # Time in different power states
+system.physmem_1.refreshEnergy             6748591200                       # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy             2964574845                       # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy            59393774250                       # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy              69133507095                       # Total energy per rank (pJ)
+system.physmem_1.averagePower              669.095685                       # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE    98803806250                       # Time in different power states
+system.physmem_1.memoryStateTime::REF      3450200000                       # Time in different power states
 system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
-system.physmem_1.memoryStateTime::ACT       884606250                       # Time in different power states
+system.physmem_1.memoryStateTime::ACT      1069805000                       # Time in different power states
 system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
-system.cpu.branchPred.lookups                20604101                       # Number of BP lookups
-system.cpu.branchPred.condPredicted          20604101                       # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect           1328804                       # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups             12707128                       # Number of BTB lookups
-system.cpu.branchPred.BTBHits                12016946                       # Number of BTB hits
+system.cpu.branchPred.lookups                40908032                       # Number of BP lookups
+system.cpu.branchPred.condPredicted          40908032                       # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect           6741329                       # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups             35316490                       # Number of BTB lookups
+system.cpu.branchPred.BTBHits                       0                       # Number of BTB hits
 system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct             94.568545                       # BTB Hit Percentage
-system.cpu.branchPred.usedRAS                 1442846                       # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect              16873                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct              0.000000                       # BTB Hit Percentage
+system.cpu.branchPred.usedRAS                 3206071                       # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect             604531                       # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups        35316490                       # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits            9869044                       # Number of indirect target hits.
+system.cpu.branchPred.indirectMisses         25447446                       # Number of indirect misses.
+system.cpu.branchPredindirectMispredicted      5035252                       # Number of mispredicted indirect branches.
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        158281960                       # number of cpu cycles simulated
+system.cpu.numCycles                        206648308                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles           25261178                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      227540211                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    20604101                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           13459792                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     131194128                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 3196201                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                         20                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles                 1974                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         21216                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles           13                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles           47                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  24267790                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                266999                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          158076676                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.380152                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.324972                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           46351281                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      420030465                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    40908032                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           13075115                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     152558958                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                14935189                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                        126                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles                 5881                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         68758                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles          764                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          179                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  41261989                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1525874                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                       8                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          206453541                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.416062                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.660543                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 95737541     60.56%     60.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  4758449      3.01%     63.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  3804662      2.41%     65.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4365114      2.76%     68.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  4234763      2.68%     71.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  4816060      3.05%     74.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4706873      2.98%     77.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3702906      2.34%     79.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 31950308     20.21%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 99211398     48.06%     48.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  5135847      2.49%     50.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  5374620      2.60%     53.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  5328555      2.58%     55.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  6013612      2.91%     58.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5856529      2.84%     61.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  5733209      2.78%     64.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  4747222      2.30%     66.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 69052549     33.45%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            158076676                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.130173                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.437563                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 15410588                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              96165480                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  23286258                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              21616250                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1598100                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              336629357                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                1598100                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 23294906                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                31785653                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          30420                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  36005070                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              65362527                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              328266704                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1575                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               57713164                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents                7745606                       # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents                 167786                       # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands           380441390                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             910027714                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        600617838                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups           4182134                       # Number of floating rename lookups
+system.cpu.fetch.rateDist::total            206453541                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.197960                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.032586                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32305475                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              86547165                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  62440790                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              17692517                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                7467594                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              591140753                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                7467594                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 42099614                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                46622929                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          29580                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  68917298                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              41316526                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              552365156                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  1615                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               36415427                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents                4818042                       # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents                 146051                       # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands           629691896                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1486514399                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        974943820                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          15152274                       # Number of floating rename lookups
 system.cpu.rename.CommittedMaps             259429450                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                121011940                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1942                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1920                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 120996238                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             82787388                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            29790681                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          59618218                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         20385333                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  317847098                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                5129                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 259397684                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             74444                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        96488843                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    197170698                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           3884                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     158076676                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.640961                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.524821                       # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps                370262446                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               2381                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           2386                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  89347483                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            128815998                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            45923960                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          77358410                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         25275137                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  490566423                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               62065                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 338414549                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1099553                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       269265104                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    527048763                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          60820                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     206453541                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.639180                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.804126                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            40037945     25.33%     25.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            47502914     30.05%     55.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            33077309     20.92%     76.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            17993682     11.38%     87.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            10964082      6.94%     94.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4766949      3.02%     97.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2459936      1.56%     99.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              882455      0.56%     99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              391404      0.25%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            73345677     35.53%     35.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            46646037     22.59%     58.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            32854801     15.91%     74.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            20905072     10.13%     84.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            15063521      7.30%     91.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8409386      4.07%     95.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             5213188      2.53%     98.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             2363320      1.14%     99.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1652539      0.80%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       158076676                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       206453541                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  232294      7.31%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2560752     80.62%     87.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                383461     12.07%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  758238     19.31%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     19.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2733075     69.60%     88.91% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                435620     11.09%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1212757      0.47%      0.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             161810976     62.38%     62.85% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult               789695      0.30%     63.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv               7037932      2.71%     65.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1186383      0.46%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             64896241     25.02%     91.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            22463700      8.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1211810      0.36%      0.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             216608884     64.01%     64.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult               799973      0.24%     64.60% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv               7048329      2.08%     66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1813849      0.54%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             84312637     24.91%     92.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            26619067      7.87%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              259397684                       # Type of FU issued
-system.cpu.iq.rate                           1.638833                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     3176507                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.012246                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          675268326                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         410944101                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    253662317                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             4854669                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            3693735                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2339703                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              258916823                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2444611                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18724072                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              338414549                       # Type of FU issued
+system.cpu.iq.rate                           1.637635                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     3926933                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.011604                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          880106724                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         745207821                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    316030450                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             8202401                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes           15512263                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      3567674                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              337013730                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 4115942                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18154732                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     26137801                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        13130                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       303242                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      9274964                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     72166411                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        54986                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       863760                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     25408243                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        49887                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked            39                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        50543                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked            53                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1598100                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                12496395                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                489060                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           317852227                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             92568                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              82787388                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             29790681                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               2962                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 383739                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 63074                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         303242                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         551670                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       826736                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1378406                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             257339859                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              64084689                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           2057825                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                7467594                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                35770303                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                592137                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           490628488                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           1259959                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             128815998                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             45923960                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts              22654                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 545800                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 38626                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         863760                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1294864                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      6880130                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              8174994                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             326485130                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              80685795                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          11929419                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     86369700                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14330688                       # Number of branches executed
-system.cpu.iew.exec_stores                   22285011                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.625832                       # Inst execution rate
-system.cpu.iew.wb_sent                      256690834                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     256002020                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 204396152                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 369708063                       # num instructions consuming a value
-system.cpu.iew.wb_rate                       1.617380                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.552858                       # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts        96496520                       # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs                    106318426                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 18939296                       # Number of branches executed
+system.cpu.iew.exec_stores                   25632631                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.579907                       # Inst execution rate
+system.cpu.iew.wb_sent                      322610085                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     319598124                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 256503247                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 435667509                       # num instructions consuming a value
+system.cpu.iew.wb_rate                       1.546580                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.588759                       # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts       269290512                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1245                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1330625                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    144920750                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.527479                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.956907                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           6746174                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    163890954                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.350675                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.933271                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     45508635     31.40%     31.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     57312379     39.55%     70.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     14158343      9.77%     80.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     11991163      8.27%     88.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4086516      2.82%     91.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2858052      1.97%     93.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       923800      0.64%     94.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1073190      0.74%     95.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      7008672      4.84%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     67206524     41.01%     41.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     54940140     33.52%     74.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     13261155      8.09%     82.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     10687834      6.52%     89.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      5446779      3.32%     92.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3132108      1.91%     94.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1092307      0.67%     95.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1156922      0.71%     95.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      6967185      4.25%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    144920750                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total    163890954                       # Number of insts commited each cycle
 system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
 system.cpu.commit.committedOps              221363384                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
@@ -536,347 +541,347 @@ system.cpu.commit.op_class_0::MemWrite       20515717      9.27%    100.00% # Cl
 system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
 system.cpu.commit.op_class_0::total         221363384                       # Class of committed instruction
-system.cpu.commit.bw_lim_events               7008672                       # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads                    455771982                       # The number of ROB reads
-system.cpu.rob.rob_writes                   648913279                       # The number of ROB writes
-system.cpu.timesIdled                            2665                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                          205284                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events               6967185                       # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads                    647577665                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1024269930                       # The number of ROB writes
+system.cpu.timesIdled                            2819                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                          194767                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
 system.cpu.committedOps                     221363384                       # Number of Ops (including micro ops) Simulated
-system.cpu.cpi                               1.198459                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.198459                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.834405                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.834405                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                448575240                       # number of integer regfile reads
-system.cpu.int_regfile_writes               232602901                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3212636                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  1997796                       # number of floating regfile writes
-system.cpu.cc_regfile_reads                 102540235                       # number of cc regfile reads
-system.cpu.cc_regfile_writes                 59516419                       # number of cc regfile writes
-system.cpu.misc_regfile_reads               132474842                       # number of misc regfile reads
+system.cpu.cpi                               1.564674                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.564674                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.639111                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.639111                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                524516370                       # number of integer regfile reads
+system.cpu.int_regfile_writes               289029189                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   4536413                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  3331836                       # number of floating regfile writes
+system.cpu.cc_regfile_reads                 107017358                       # number of cc regfile reads
+system.cpu.cc_regfile_writes                 65774990                       # number of cc regfile writes
+system.cpu.misc_regfile_reads               176892429                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                   1689                       # number of misc regfile writes
-system.cpu.dcache.tags.replacements                51                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1429.115986                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            65747319                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs              1995                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs          32956.049624                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements                72                       # number of replacements
+system.cpu.dcache.tags.tagsinuse          1525.498489                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            82766316                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs              2113                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs          39170.050166                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1429.115986                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.348905                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.348905                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024         1944                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data  1525.498489                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.372436                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.372436                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024         2041                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           15                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1           34                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2          498                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4         1394                       # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024     0.474609                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         131501477                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        131501477                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     45233030                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        45233030                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20513912                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20513912                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      65746942                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         65746942                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     65746942                       # number of overall hits
-system.cpu.dcache.overall_hits::total        65746942                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          980                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           980                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1819                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1819                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2799                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2799                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2799                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2799                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     65149000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     65149000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data    128515000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total    128515000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    193664000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    193664000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    193664000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    193664000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     45234010                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     45234010                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::1           32                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2          101                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3          409                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4         1484                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024     0.498291                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         165539971                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        165539971                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     62251936                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        62251936                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20513707                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20513707                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      82765643                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         82765643                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     82765643                       # number of overall hits
+system.cpu.dcache.overall_hits::total        82765643                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1262                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1262                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         2024                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2024                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         3286                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           3286                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         3286                       # number of overall misses
+system.cpu.dcache.overall_misses::total          3286                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     84231000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     84231000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    131983500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    131983500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    216214500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    216214500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    216214500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    216214500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     62253198                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     62253198                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515731                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515731                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     65749741                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     65749741                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     65749741                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     65749741                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000022                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000043                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66478.571429                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66478.571429                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70651.456844                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70651.456844                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.425152                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69190.425152                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.425152                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69190.425152                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs          656                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets           70                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs                 7                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets               1                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs    93.714286                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets           70                       # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data     82768929                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     82768929                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     82768929                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     82768929                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000020                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000020                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000099                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000099                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000040                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000040                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000040                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000040                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66744.057052                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66744.057052                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65209.239130                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 65209.239130                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65798.691418                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65798.691418                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65798.691418                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65798.691418                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs          369                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets           73                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs                 8                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets               2                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs    46.125000                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets    36.500000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks           10                       # number of writebacks
-system.cpu.dcache.writebacks::total                10                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          526                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          526                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data            2                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          528                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          528                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          528                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          528                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          454                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          454                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1817                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1817                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2271                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2271                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2271                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2271                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     36063500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     36063500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    126552000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total    126552000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    162615500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    162615500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    162615500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    162615500                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
+system.cpu.dcache.writebacks::total                18                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          661                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          661                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data            7                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total            7                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          668                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          668                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          668                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          668                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          601                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          601                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2017                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2017                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2618                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2618                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2618                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2618                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     47710000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     47710000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    129636500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    129636500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    177346500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    177346500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    177346500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    177346500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.000035                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.000035                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79435.022026                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79435.022026                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69648.871767                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69648.871767                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71605.239982                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71605.239982                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71605.239982                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71605.239982                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000098                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000098                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.000032                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000032                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.000032                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79384.359401                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79384.359401                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64271.938523                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64271.938523                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67741.214668                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 67741.214668                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67741.214668                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67741.214668                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements              5017                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1636.805094                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs            24258360                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs              6993                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs           3468.948949                       # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements              6515                       # number of replacements
+system.cpu.icache.tags.tagsinuse          1663.291735                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            41248897                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs              8499                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs           4853.382398                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1636.805094                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.799221                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.799221                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024         1976                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0          111                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1          188                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2          869                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3           20                       # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4          788                       # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024     0.964844                       # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses          48542846                       # Number of tag accesses
-system.cpu.icache.tags.data_accesses         48542846                       # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst     24258361                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        24258361                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      24258361                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         24258361                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     24258361                       # number of overall hits
-system.cpu.icache.overall_hits::total        24258361                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         9428                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          9428                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         9428                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           9428                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         9428                       # number of overall misses
-system.cpu.icache.overall_misses::total          9428                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    409015499                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    409015499                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    409015499                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    409015499                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    409015499                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    409015499                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     24267789                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     24267789                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     24267789                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     24267789                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     24267789                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     24267789                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000388                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000388                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000388                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000388                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000388                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000388                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43383.060989                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 43383.060989                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 43383.060989                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 43383.060989                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 43383.060989                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 43383.060989                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs          793                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs                13                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs           61                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst  1663.291735                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.812154                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.812154                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024         1984                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0           97                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          845                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3          155                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4          736                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024     0.968750                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          82532972                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         82532972                       # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst     41248897                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        41248897                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      41248897                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         41248897                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     41248897                       # number of overall hits
+system.cpu.icache.overall_hits::total        41248897                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        13089                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         13089                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        13089                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          13089                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        13089                       # number of overall misses
+system.cpu.icache.overall_misses::total         13089                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    485791000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    485791000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    485791000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    485791000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    485791000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    485791000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     41261986                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     41261986                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     41261986                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     41261986                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     41261986                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     41261986                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000317                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000317                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000317                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000317                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000317                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000317                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37114.447246                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 37114.447246                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37114.447246                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 37114.447246                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37114.447246                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 37114.447246                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs         2090                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets          305                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs                30                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs    69.666667                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets          305                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::writebacks         5017                       # number of writebacks
-system.cpu.icache.writebacks::total              5017                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2159                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         2159                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         2159                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         2159                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         2159                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         2159                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7269                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         7269                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         7269                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         7269                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         7269                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         7269                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    311106499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    311106499                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    311106499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    311106499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    311106499                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    311106499                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000300                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000300                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000300                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000300                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000300                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000300                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42799.078140                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42799.078140                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42799.078140                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 42799.078140                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42799.078140                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 42799.078140                       # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks         6515                       # number of writebacks
+system.cpu.icache.writebacks::total              6515                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4088                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4088                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4088                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4088                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4088                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4088                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         9001                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         9001                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         9001                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         9001                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         9001                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         9001                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    340708000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    340708000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    340708000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    340708000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    340708000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    340708000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000218                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000218                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000218                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000218                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000218                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000218                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37852.238640                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37852.238640                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37852.238640                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 37852.238640                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37852.238640                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 37852.238640                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         2581.252539                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               8528                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             3879                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             2.198505                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2796.844278                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs              11471                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             4155                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.760770                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     1.770890                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  2276.984589                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   302.497060                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000054                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.069488                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.009231                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.078774                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         3879                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           46                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1          182                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          999                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3           41                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2611                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.118378                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses           119253                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses          119253                       # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks           10                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total           10                       # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks         4917                       # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total         4917                       # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu.l2cache.tags.occ_blocks::writebacks     4.971138                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  2402.103394                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data   389.769746                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks     0.000152                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.073306                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.011895                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.085353                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         4155                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           41                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          151                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          992                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          147                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2824                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.126801                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses           146881                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses          146881                       # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks           18                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total           18                       # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks         6469                       # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total         6469                       # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            6                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            6                       # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         3531                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total         3531                       # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data           35                       # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total           35                       # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3531                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           41                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            3572                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3531                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           41                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           3572                       # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          275                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          275                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1535                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1535                       # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3460                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total         3460                       # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data          419                       # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total          419                       # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3460                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1954                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5414                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3460                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1954                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5414                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    115784500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    115784500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    262406000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    262406000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     34977500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     34977500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    262406000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    150762000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    413168000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    262406000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    150762000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    413168000                       # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks           10                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total           10                       # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks         4917                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total         4917                       # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          276                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          276                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1541                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1541                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         6991                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total         6991                       # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          454                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total          454                       # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         6991                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1995                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         8986                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         6991                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1995                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         8986                       # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.996377                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.996377                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.996106                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.996106                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.494922                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.494922                       # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.922907                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.922907                       # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.494922                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.979449                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.602493                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.494922                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.979449                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.602493                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75429.641694                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75429.641694                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75839.884393                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75839.884393                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83478.520286                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83478.520286                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75839.884393                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.578301                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76314.739564                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75839.884393                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.578301                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76314.739564                       # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst         4877                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total         4877                       # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data           68                       # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total           68                       # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         4877                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           74                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            4951                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         4877                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           74                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           4951                       # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          500                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          500                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1507                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1507                       # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         3617                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total         3617                       # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data          532                       # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total          532                       # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3617                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2039                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5656                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3617                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2039                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5656                       # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    112056000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    112056000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    275028000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    275028000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     45953000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     45953000                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    275028000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    158009000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    433037000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    275028000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    158009000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    433037000                       # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks           18                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total           18                       # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks         6469                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total         6469                       # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          505                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          505                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1513                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1513                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst         8494                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total         8494                       # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data          600                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total          600                       # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         8494                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2113                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        10607                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         8494                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2113                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        10607                       # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.990099                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.990099                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.996034                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.996034                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.425830                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.425830                       # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.886667                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.886667                       # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.425830                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.964979                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.533233                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.425830                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.964979                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.533233                       # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74357.000664                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74357.000664                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76037.600221                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76037.600221                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86377.819549                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86377.819549                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76037.600221                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77493.379107                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76562.411598                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76037.600221                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77493.379107                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76562.411598                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -885,128 +890,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          275                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          275                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1535                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1535                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3460                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3460                       # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          419                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total          419                       # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3460                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1954                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5414                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3460                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1954                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5414                       # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      5217500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      5217500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    100434500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    100434500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    227816000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    227816000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     30787500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     30787500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    227816000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    131222000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    359038000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    227816000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    131222000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    359038000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.996377                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.996377                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.996106                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.996106                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.494922                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.494922                       # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.922907                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.922907                       # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.494922                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.979449                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.602493                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.494922                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.979449                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.602493                       # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18972.727273                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18972.727273                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.774566                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.774566                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73478.520286                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73478.520286                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.774566                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.578301                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.774566                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.578301                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627                       # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          500                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          500                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1507                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1507                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         3617                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total         3617                       # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data          532                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total          532                       # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3617                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2039                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5656                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3617                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2039                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5656                       # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      9503500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      9503500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     96986000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     96986000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    238858000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    238858000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     40633000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     40633000                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    238858000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    137619000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    376477000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    238858000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    137619000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    376477000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.990099                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.990099                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.996034                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.996034                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.425830                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.425830                       # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.886667                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.886667                       # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.425830                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964979                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.533233                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.425830                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964979                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.533233                       # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        19007                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        19007                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64357.000664                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64357.000664                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66037.600221                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66037.600221                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76377.819549                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76377.819549                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66037.600221                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67493.379107                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66562.411598                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66037.600221                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67493.379107                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66562.411598                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests        14608                       # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests         5367                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests          376                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests        18206                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests         7138                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests          549                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp          7722                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty           10                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean         5017                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict           41                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq          276                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp          276                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq         1541                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp         1541                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq         7269                       # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq          454                       # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        19276                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         4593                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total             23869                       # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       768448                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       128320                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total             896768                       # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops                         278                       # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples         9540                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        0.070650                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.256253                       # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp          9600                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty           18                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean         6515                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict           54                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq          505                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp          505                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq         1513                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp         1513                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq         9001                       # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq          600                       # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        24009                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side         5308                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total             29317                       # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       960512                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       136384                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total            1096896                       # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops                         507                       # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples        11619                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.094328                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.292297                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0               8866     92.94%     92.94% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1                674      7.06%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0              10523     90.57%     90.57% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               1096      9.43%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total           9540                       # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy       12331000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total          11619                       # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy       15636499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy      10902000                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy      13500000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy       3131498                       # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy       3422499                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.trans_dist::ReadResp               3878                       # Transaction distribution
-system.membus.trans_dist::UpgradeReq              275                       # Transaction distribution
-system.membus.trans_dist::ReadExReq              1535                       # Transaction distribution
-system.membus.trans_dist::ReadExResp             1535                       # Transaction distribution
-system.membus.trans_dist::ReadSharedReq          3878                       # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11101                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11101                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total                  11101                       # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       346432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total       346432                       # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total                  346432                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp               4149                       # Transaction distribution
+system.membus.trans_dist::UpgradeReq              500                       # Transaction distribution
+system.membus.trans_dist::ReadExReq              1507                       # Transaction distribution
+system.membus.trans_dist::ReadExResp             1507                       # Transaction distribution
+system.membus.trans_dist::ReadSharedReq          4149                       # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        11812                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total        11812                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total                  11812                       # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       361984                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total       361984                       # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total                  361984                       # Cumulative packet size per connected master and slave (bytes)
 system.membus.snoops                                0                       # Total snoops (count)
-system.membus.snoop_fanout::samples              5688                       # Request fanout histogram
+system.membus.snoop_fanout::samples              6156                       # Request fanout histogram
 system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
 system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
 system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
-system.membus.snoop_fanout::0                    5688    100.00%    100.00% # Request fanout histogram
+system.membus.snoop_fanout::0                    6156    100.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
 system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
 system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
-system.membus.snoop_fanout::total                5688                       # Request fanout histogram
-system.membus.reqLayer0.occupancy             6954000                       # Layer occupancy (ticks)
+system.membus.snoop_fanout::total                6156                       # Request fanout histogram
+system.membus.reqLayer0.occupancy             7649501                       # Layer occupancy (ticks)
 system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
-system.membus.respLayer1.occupancy           28681250                       # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy           30011250                       # Layer occupancy (ticks)
 system.membus.respLayer1.utilization              0.0                       # Layer utilization (%)
 
 ---------- End Simulation Statistics   ----------