diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
| commit | 09b2430e95df4f744a000bac34100eeb9ebcb878 (patch) | |
| tree | 1db0ab99b4186f15335a866fd7239ba51755b7d9 /tests/long/se | |
| parent | f205d83359dfb3c4f75159f83081b5e356c3c4b4 (diff) | |
| download | gem5-09b2430e95df4f744a000bac34100eeb9ebcb878.tar.xz | |
stats: update patches for branch predictor and fetch updates.
Diffstat (limited to 'tests/long/se')
17 files changed, 2486 insertions, 2486 deletions
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 7a8202b52..ed4236d5d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -528,9 +528,9 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser +executable=/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in +input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -555,6 +555,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 5400b92b5..78db76e29 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:38:19 -gem5 started Feb 13 2013 19:20:32 -gem5 executing on u200540-lin +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 00:58:30 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 199938942500 because target called exit() +Exiting @ tick 199930442500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 4facf02db..83f6a1bd8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,116 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.199960 # Number of seconds simulated -sim_ticks 199959919500 # Number of ticks simulated -final_tick 199959919500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.199930 # Number of seconds simulated +sim_ticks 199930442500 # Number of ticks simulated +final_tick 199930442500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126038 # Simulator instruction rate (inst/s) -host_op_rate 142101 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49882714 # Simulator tick rate (ticks/s) -host_mem_usage 278340 # Number of bytes of host memory used -host_seconds 4008.60 # Real time elapsed on the host +host_inst_rate 127290 # Simulator instruction rate (inst/s) +host_op_rate 143512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50370674 # Simulator tick rate (ticks/s) +host_mem_usage 265580 # Number of bytes of host memory used +host_seconds 3969.18 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9260800 # Number of bytes read from this memory -system.physmem.bytes_read::total 9477568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6246592 # Number of bytes written to this memory -system.physmem.bytes_written::total 6246592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144700 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148087 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97603 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97603 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1084057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46313281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47397339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1084057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1084057 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31239220 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31239220 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31239220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1084057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46313281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78636559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148088 # Total number of read requests seen -system.physmem.writeReqs 97603 # Total number of write requests seen -system.physmem.cpureqs 247534 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9477568 # Total number of bytes read from memory -system.physmem.bytesWritten 6246592 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9477568 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6246592 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 77 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 6 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9156 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9186 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9506 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9385 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9094 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9054 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 9284 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9051 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5987 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6274 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6476 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6222 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6039 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 216192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9265152 # Number of bytes read from this memory +system.physmem.bytes_read::total 9481344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6247552 # Number of bytes written to this memory +system.physmem.bytes_written::total 6247552 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144768 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97618 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97618 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1081336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 46341877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47423213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1081336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1081336 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 31248628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 31248628 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 31248628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1081336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 46341877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 78671841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148147 # Total number of read requests seen +system.physmem.writeReqs 97618 # Total number of write requests seen +system.physmem.cpureqs 247832 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9481344 # Total number of bytes read from memory +system.physmem.bytesWritten 6247552 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9481344 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6247552 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9166 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9182 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9622 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 9866 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9514 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9403 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 9092 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 9052 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 9254 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8851 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9220 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9034 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 9025 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9210 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5950 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5982 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6482 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6230 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6032 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 5973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6195 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5906 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6101 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5980 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5943 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6048 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6101 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5908 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6109 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5940 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6062 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6095 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1837 # Number of times wr buffer was full causing retry -system.physmem.totGap 199959894000 # Total gap between requests +system.physmem.numWrRetry 2058 # Number of times wr buffer was full causing retry +system.physmem.totGap 199930425500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148088 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 99440 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 6 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 138077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.readPktSize::6 148147 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 97618 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 137980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9444 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -137,70 +124,68 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4234 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1699469983 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4970281233 # Sum of mem lat for all requests -system.physmem.totBusLat 740055000 # Total cycles spent in databus access -system.physmem.totBankLat 2530756250 # Total cycles spent in bank access -system.physmem.avgQLat 11482.05 # Average queueing delay per request -system.physmem.avgBankLat 17098.43 # Average bank access latency per request +system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.totQLat 1712037750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4981606500 # Sum of mem lat for all requests +system.physmem.totBusLat 740435000 # Total cycles spent in databus access +system.physmem.totBankLat 2529133750 # Total cycles spent in bank access +system.physmem.avgQLat 11561.03 # Average queueing delay per request +system.physmem.avgBankLat 17078.70 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33580.49 # Average memory access latency -system.physmem.avgRdBW 47.40 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 31.24 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.40 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 31.24 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 33639.73 # Average memory access latency +system.physmem.avgRdBW 47.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 47.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.80 # Average write queue length over time -system.physmem.readRowHits 125322 # Number of row buffer hits during reads -system.physmem.writeRowHits 52822 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.12 # Row buffer hit rate for writes -system.physmem.avgGap 813867.39 # Average gap between requests -system.cpu.branchPred.lookups 182791909 # Number of BP lookups -system.cpu.branchPred.condPredicted 143104920 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7263448 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93100856 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87211306 # Number of BTB hits +system.physmem.avgWrQLen 8.71 # Average write queue length over time +system.physmem.readRowHits 125393 # Number of row buffer hits during reads +system.physmem.writeRowHits 52794 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 54.08 # Row buffer hit rate for writes +system.physmem.avgGap 813502.43 # Average gap between requests +system.cpu.branchPred.lookups 182807672 # Number of BP lookups +system.cpu.branchPred.condPredicted 143119940 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265200 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 92612738 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87226650 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.674011 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12676660 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116192 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.184290 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12677704 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116304 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -244,136 +229,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 399919840 # number of cpu cycles simulated +system.cpu.numCycles 399860886 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119359242 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761526244 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182791909 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99887966 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170136962 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35675847 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75471629 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114518172 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2437097 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 392580882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.175648 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.990337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119358222 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761608008 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182807672 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99904354 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170147877 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35680811 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75396284 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 468 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 45 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114514342 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2439022 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 392517505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.176152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.990501 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222456572 56.67% 56.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14184957 3.61% 60.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22893267 5.83% 66.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22743461 5.79% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20901253 5.32% 77.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11599327 2.95% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13055185 3.33% 83.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11991563 3.05% 86.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52755297 13.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222382247 56.66% 56.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14190044 3.62% 60.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22888927 5.83% 66.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22740218 5.79% 71.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20908888 5.33% 77.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11594217 2.95% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13063164 3.33% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11994936 3.06% 86.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52754864 13.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392580882 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457071 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.904197 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129017942 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70989640 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158833179 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6202041 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27538080 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26128135 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 77010 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825507648 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 295471 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27538080 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135602175 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9653631 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46459749 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158272352 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15054895 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800579867 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1059 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3045560 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8808243 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 238 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954266949 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500439750 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500438390 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 392517505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.457178 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.904682 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129005298 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 70927026 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158858538 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6186097 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27540546 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26127343 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76683 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825553021 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 296390 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27540546 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135586345 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9628782 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46469860 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158285767 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15006205 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800628342 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1130 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3045894 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8758928 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 294 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954382842 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500628672 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500627387 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1285 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288014658 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292979 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292975 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41576680 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170252258 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73485876 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28570132 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15813364 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755065776 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775319 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665331498 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1369025 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187382058 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479835806 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797687 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 392580882 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.694763 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735550 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288130551 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292970 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41448640 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170247105 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73473871 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28488219 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15923707 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755060750 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775315 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665323167 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1373619 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187375419 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479909972 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797683 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 392517505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.695015 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735938 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 137175345 34.94% 34.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69848009 17.79% 52.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71421264 18.19% 70.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53409606 13.60% 84.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31213744 7.95% 92.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16052398 4.09% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8748856 2.23% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2891239 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1820421 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 137188203 34.95% 34.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69757763 17.77% 52.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71444239 18.20% 70.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53382766 13.60% 84.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31199092 7.95% 92.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16084863 4.10% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8731670 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2913347 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1815562 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 392580882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 392517505 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 477908 5.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6514153 68.18% 73.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2562402 26.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 478854 5.03% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6518035 68.44% 73.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2526744 26.53% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447790588 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383397 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447790300 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383235 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 96 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -399,84 +384,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153366793 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63790621 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153391187 23.06% 90.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63758352 9.58% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665331498 # Type of FU issued -system.cpu.iq.rate 1.663662 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9554463 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014360 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1734167139 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947029128 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646060992 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665323167 # Type of FU issued +system.cpu.iq.rate 1.663887 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9523633 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014314 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1734060876 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 947018314 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646045006 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674885846 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 115 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8559648 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674846691 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8570702 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44222703 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810061 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16625399 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44217550 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 42225 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810789 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16613394 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19536 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4374 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19530 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4440 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27538080 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5027706 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 374233 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760399793 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1113000 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170252258 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73485876 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286777 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 218846 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12338 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810061 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4335774 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4000856 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8336630 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655910156 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150087379 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9421342 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27540546 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5027645 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 374127 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760395240 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1110246 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170247105 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73473871 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286773 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 218357 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 11618 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810789 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4336068 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4004006 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8340074 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655902697 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150107572 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9420470 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558698 # number of nop insts executed -system.cpu.iew.exec_refs 212584480 # number of memory reference insts executed -system.cpu.iew.exec_branches 138500041 # Number of branches executed -system.cpu.iew.exec_stores 62497101 # Number of stores executed -system.cpu.iew.exec_rate 1.640104 # Inst execution rate -system.cpu.iew.wb_sent 651032473 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646061008 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374768785 # num instructions producing a value -system.cpu.iew.wb_consumers 646479955 # num instructions consuming a value +system.cpu.iew.exec_nop 1559175 # number of nop insts executed +system.cpu.iew.exec_refs 212574642 # number of memory reference insts executed +system.cpu.iew.exec_branches 138502057 # Number of branches executed +system.cpu.iew.exec_stores 62467070 # Number of stores executed +system.cpu.iew.exec_rate 1.640327 # Inst execution rate +system.cpu.iew.wb_sent 651021062 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646045022 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374765758 # num instructions producing a value +system.cpu.iew.wb_consumers 646459860 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615476 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579707 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615674 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579720 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189458167 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189453742 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7189194 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 365042802 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.564113 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233409 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7191165 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 364976959 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.564395 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233817 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157342257 43.10% 43.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98505195 26.98% 70.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33835922 9.27% 79.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18767828 5.14% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16196095 4.44% 88.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7449740 2.04% 90.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6969572 1.91% 92.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3172412 0.87% 93.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22803781 6.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 157310366 43.10% 43.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98490082 26.99% 70.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33805907 9.26% 79.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18787402 5.15% 84.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16180614 4.43% 88.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7431287 2.04% 90.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6987633 1.91% 92.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3169968 0.87% 93.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22813700 6.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 365042802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 364976959 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -487,199 +472,199 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22803781 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22813700 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1102658217 # The number of ROB reads -system.cpu.rob.rob_writes 1548511592 # The number of ROB writes -system.cpu.timesIdled 308911 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7338958 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1102578030 # The number of ROB reads +system.cpu.rob.rob_writes 1548505178 # The number of ROB writes +system.cpu.timesIdled 308567 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7343381 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.791548 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.791548 # CPI: Total CPI of All Threads -system.cpu.ipc 1.263347 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.263347 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058721385 # number of integer regfile reads -system.cpu.int_regfile_writes 752002162 # number of integer regfile writes +system.cpu.cpi 0.791431 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.791431 # CPI: Total CPI of All Threads +system.cpu.ipc 1.263534 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.263534 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058706465 # number of integer regfile reads +system.cpu.int_regfile_writes 752037507 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210835812 # number of misc regfile reads +system.cpu.misc_regfile_reads 210820275 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.icache.replacements 15017 # number of replacements -system.cpu.icache.tagsinuse 1100.275071 # Cycle average of tags in use -system.cpu.icache.total_refs 114497128 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16875 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6785.014993 # Average number of references to valid blocks. +system.cpu.icache.replacements 15019 # number of replacements +system.cpu.icache.tagsinuse 1100.569602 # Cycle average of tags in use +system.cpu.icache.total_refs 114493231 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16877 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6783.980032 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1100.275071 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537244 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537244 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114497128 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114497128 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114497128 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114497128 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114497128 # number of overall hits -system.cpu.icache.overall_hits::total 114497128 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21044 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21044 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21044 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21044 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21044 # number of overall misses -system.cpu.icache.overall_misses::total 21044 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 498168000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 498168000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 498168000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 498168000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 498168000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 498168000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114518172 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114518172 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114518172 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114518172 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114518172 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114518172 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1100.569602 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537388 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537388 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114493231 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114493231 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114493231 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114493231 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114493231 # number of overall hits +system.cpu.icache.overall_hits::total 114493231 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21111 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21111 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21111 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21111 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21111 # number of overall misses +system.cpu.icache.overall_misses::total 21111 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 514757500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 514757500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 514757500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 514757500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 514757500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 514757500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114514342 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114514342 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114514342 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114514342 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114514342 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114514342 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23672.685801 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23672.685801 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23672.685801 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23672.685801 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24383.378334 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 24383.378334 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 24383.378334 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 24383.378334 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 24383.378334 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1152 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38.100000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 88.615385 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97603 # number of writebacks -system.cpu.l2cache.writebacks::total 97603 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43401 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46789 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101299 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101299 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3388 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144700 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148088 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3388 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144700 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148088 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175595014 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2357208396 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2532803410 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 60006 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 60006 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3964657000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3964657000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175595014 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6321865396 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6497460410 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175595014 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6321865396 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6497460410 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051181 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054100 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.065217 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.065217 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290408 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290408 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122016 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122016 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51828.516529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54312.306076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54132.454423 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 97618 # number of writebacks +system.cpu.l2cache.writebacks::total 97618 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43455 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46833 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101314 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101314 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3378 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144769 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148147 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3378 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144769 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148147 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180723170 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2376770410 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2557493580 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3952267092 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3952267092 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180723170 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6329037502 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6509760672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180723170 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6329037502 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6509760672 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051252 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.109756 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.109756 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290422 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290422 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122073 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200237 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122073 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53500.050326 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54694.981245 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54608.792518 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39138.165234 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39138.165234 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39010.078489 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39010.078489 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53500.050326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43718.182083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43941.225080 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192712 # number of replacements -system.cpu.dcache.tagsinuse 4058.214665 # Cycle average of tags in use -system.cpu.dcache.total_refs 190183804 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196808 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.909202 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1192631 # number of replacements +system.cpu.dcache.tagsinuse 4058.209057 # Cycle average of tags in use +system.cpu.dcache.total_refs 190187917 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196727 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.923394 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.214665 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990775 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990775 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136214217 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136214217 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50991947 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50991947 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488812 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488812 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 4058.209057 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990774 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990774 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136218647 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136218647 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50991635 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50991635 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488827 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488827 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187206164 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187206164 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187206164 # number of overall hits -system.cpu.dcache.overall_hits::total 187206164 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1696297 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1696297 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3247359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3247359 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 187210282 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187210282 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187210282 # number of overall hits +system.cpu.dcache.overall_hits::total 187210282 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1699163 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1699163 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3247671 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3247671 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4943656 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4943656 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4943656 # number of overall misses -system.cpu.dcache.overall_misses::total 4943656 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26545297500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26545297500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57237294950 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57237294950 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 659000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 659000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83782592450 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83782592450 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83782592450 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83782592450 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137910514 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137910514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4946834 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4946834 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4946834 # number of overall misses +system.cpu.dcache.overall_misses::total 4946834 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26685574500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26685574500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57046648448 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57046648448 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83732222948 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83732222948 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83732222948 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83732222948 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137917810 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137917810 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488853 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488853 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488868 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488868 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192149820 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192149820 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192149820 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192149820 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012300 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012300 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059871 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059871 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 192157116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192157116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192157116 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192157116 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012320 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012320 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025728 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025728 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025728 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025728 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15648.968017 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15648.968017 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17625.798364 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17625.798364 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16073.170732 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16073.170732 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16947.496438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16947.496438 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18139 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17902 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1666 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 610 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.887755 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 29.347541 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15705.129231 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15705.129231 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17565.402545 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17565.402545 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15012.195122 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15012.195122 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16926.426670 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16926.426670 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16926.426670 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 18054 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15751 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1658 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 601 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.889023 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 26.207987 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1111113 # number of writebacks -system.cpu.dcache.writebacks::total 1111113 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847762 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 847762 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898994 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2898994 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1110977 # number of writebacks +system.cpu.dcache.writebacks::total 1110977 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850754 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 850754 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2899270 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3746756 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3746756 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3746756 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3746756 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848535 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848535 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348365 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348365 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196900 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196900 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196900 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196900 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11831456500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11831456500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8103165495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8103165495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19934621995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19934621995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19934621995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19934621995 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006153 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006153 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 3750024 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3750024 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3750024 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3750024 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848409 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848409 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348401 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348401 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196810 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196810 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196810 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196810 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11849237000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11849237000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8091181496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8091181496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19940418496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19940418496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19940418496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19940418496 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006152 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.392435 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.392435 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23260.561466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23260.561466 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13966.420677 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13966.420677 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23223.760827 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23223.760827 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16661.306720 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16661.306720 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 4cd0f21e4..fc49f2d63 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -527,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr index bf930ad43..e8096c4c9 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr @@ -1,4 +1,5 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[15], opc1[7], crm[4], opc2[6] getting pixel output filename pixels_out.cook opening control file chair.control.cook opening camera file chair.camera diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 6de8db104..30ec371c4 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 20:14:28 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 01:05:57 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -15,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.060000 -Exiting @ tick 68071881000 because target called exit() +Exiting @ tick 68244180000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 3aa47fab4..60dc6772d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068358 # Number of seconds simulated -sim_ticks 68358106500 # Number of ticks simulated -final_tick 68358106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068244 # Number of seconds simulated +sim_ticks 68244180000 # Number of ticks simulated +final_tick 68244180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 161957 # Simulator instruction rate (inst/s) -host_op_rate 207054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40547923 # Simulator tick rate (ticks/s) -host_mem_usage 250356 # Number of bytes of host memory used -host_seconds 1685.86 # Real time elapsed on the host +host_inst_rate 137663 # Simulator instruction rate (inst/s) +host_op_rate 175996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34408261 # Simulator tick rate (ticks/s) +host_mem_usage 247964 # Number of bytes of host memory used +host_seconds 1983.37 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272576 # Number of bytes read from this memory -system.physmem.bytes_read::total 465728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193152 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3018 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4259 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7277 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2825590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3987471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6813062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2825590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2825590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2825590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3987471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6813062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7278 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 194624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272640 # Number of bytes read from this memory +system.physmem.bytes_read::total 467264 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194624 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4260 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7301 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2851877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3995066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6846943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2851877 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2851877 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2851877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3995066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6846943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7301 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7280 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 465728 # Total number of bytes read from memory +system.physmem.cpureqs 7303 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 467264 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 465728 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 467264 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 414 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 413 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 411 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 478 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 504 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 546 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 585 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 480 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 506 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 490 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 545 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 589 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 454 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 451 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 454 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 414 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68358086000 # Total gap between requests +system.physmem.totGap 68243977000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7278 # Categorize read packet sizes +system.physmem.readPktSize::6 7301 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,10 +85,10 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 194 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4270 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 190 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 46720000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 192175000 # Sum of mem lat for all requests -system.physmem.totBusLat 36390000 # Total cycles spent in databus access -system.physmem.totBankLat 109065000 # Total cycles spent in bank access -system.physmem.avgQLat 6419.35 # Average queueing delay per request -system.physmem.avgBankLat 14985.57 # Average bank access latency per request +system.physmem.totQLat 46265250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 192440250 # Sum of mem lat for all requests +system.physmem.totBusLat 36505000 # Total cycles spent in databus access +system.physmem.totBankLat 109670000 # Total cycles spent in bank access +system.physmem.avgQLat 6336.84 # Average queueing delay per request +system.physmem.avgBankLat 15021.23 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26404.92 # Average memory access latency -system.physmem.avgRdBW 6.81 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26358.07 # Average memory access latency +system.physmem.avgRdBW 6.85 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.81 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.85 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6070 # Number of row buffer hits during reads +system.physmem.readRowHits 6086 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.40 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.36 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9392427.32 # Average gap between requests -system.cpu.branchPred.lookups 41732744 # Number of BP lookups -system.cpu.branchPred.condPredicted 21038238 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1652729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26040996 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16764116 # Number of BTB hits +system.physmem.avgGap 9347209.56 # Average gap between requests +system.cpu.branchPred.lookups 35347226 # Number of BP lookups +system.cpu.branchPred.condPredicted 21179372 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1632309 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18774732 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16740348 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.375863 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6744035 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 7274 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.164245 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6786825 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8584 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -222,100 +222,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136716214 # number of cpu cycles simulated +system.cpu.numCycles 136488361 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38933938 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317883912 # Number of instructions fetch has processed -system.cpu.fetch.Branches 41732744 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23508151 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70884226 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6817030 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21520624 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1371 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37551869 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 523991 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136493185 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.988959 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.456313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 38874281 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317253074 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35347226 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23527173 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70748427 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6762105 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21521098 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1748 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37491442 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 499448 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136264051 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.985356 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454882 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66238954 48.53% 48.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6780831 4.97% 53.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5636861 4.13% 57.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6036296 4.42% 62.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4884969 3.58% 65.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4157247 3.05% 68.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3216539 2.36% 71.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4148137 3.04% 74.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35393351 25.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66141604 48.54% 48.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6763728 4.96% 53.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5687382 4.17% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6073172 4.46% 62.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4900819 3.60% 65.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4081259 3.00% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3178170 2.33% 71.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4143187 3.04% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35294730 25.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136493185 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305251 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.325137 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45460656 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16697353 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66694244 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2556726 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5084206 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7272433 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69135 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401643990 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 218444 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5084206 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50968262 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1914523 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 308341 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63676495 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14541358 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393775984 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 63 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1667283 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10312278 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1126 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 432122953 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2331950900 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1259654779 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072296121 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136264051 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258976 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.324397 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45367973 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16681900 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66615179 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2549386 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5049613 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7322660 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 69153 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 400837616 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 209818 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5049613 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50901379 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1945385 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 310174 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63573069 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14484431 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393292714 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1657143 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10217675 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 990 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 431691317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2328660715 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1256261052 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072399663 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47556760 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11781 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11780 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36361756 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103536184 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91503384 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4302647 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5369286 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 384225176 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22747 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 374106691 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1237893 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34434852 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 85933398 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 627 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136493185 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.740845 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023746 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47125124 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11983 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11982 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36474755 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103439968 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91241620 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4261673 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5285781 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 383905556 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22939 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373879260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1212222 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34116216 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 85509152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 819 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136264051 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.743785 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.022773 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24947846 18.28% 18.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19979954 14.64% 32.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20599928 15.09% 48.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18110176 13.27% 61.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 23967090 17.56% 78.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15779150 11.56% 90.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8840932 6.48% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3358221 2.46% 99.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 909888 0.67% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24800729 18.20% 18.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19931248 14.63% 32.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20555324 15.08% 47.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18170547 13.33% 61.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24015276 17.62% 78.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15694879 11.52% 90.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8802527 6.46% 96.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3373106 2.48% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 920415 0.68% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136493185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136264051 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8903 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4693 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8942 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4698 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -334,329 +334,329 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46069 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 45953 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7541 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 384 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 189821 1.07% 1.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 6023 0.03% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241770 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7540 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 377 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190605 1.08% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 3637 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241259 1.36% 2.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9327128 52.38% 55.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7975640 44.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9279550 52.34% 55.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7945926 44.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126244558 33.75% 33.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2174203 0.58% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6782034 1.81% 36.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8468832 2.26% 38.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3426641 0.92% 39.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1600511 0.43% 39.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20905751 5.59% 45.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7170121 1.92% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7133236 1.91% 49.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101536664 27.14% 76.35% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88488853 23.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126287490 33.78% 33.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175875 0.58% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6775486 1.81% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8466993 2.26% 38.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3427515 0.92% 39.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1596271 0.43% 39.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20850336 5.58% 45.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7171756 1.92% 47.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7125550 1.91% 49.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101538371 27.16% 76.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88288328 23.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 374106691 # Type of FU issued -system.cpu.iq.rate 2.736374 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17807974 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047601 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654078451 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 288293032 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 250000264 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249673983 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130403978 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118157993 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263169120 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128745545 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11104268 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373879260 # Type of FU issued +system.cpu.iq.rate 2.739276 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17728490 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047418 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653579688 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 287780184 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249896445 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249383595 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130278814 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118034540 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263004554 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128603196 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11120232 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8887436 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 113793 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14364 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9127801 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8791220 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 109151 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14386 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8866037 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 171663 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1472 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 183726 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1452 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5084206 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 279212 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 42812 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 384249465 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 945099 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103536184 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91503384 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11713 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 308 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 361 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14364 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1301821 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 354554 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1656375 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 370204175 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100335709 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3902516 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5049613 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 296711 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36519 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 383930075 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 867040 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103439968 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91241620 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11905 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 347 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 346 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14386 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1268963 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 369292 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1638255 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 369960329 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100240998 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3918931 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1542 # number of nop insts executed -system.cpu.iew.exec_refs 187704225 # number of memory reference insts executed -system.cpu.iew.exec_branches 38278467 # Number of branches executed -system.cpu.iew.exec_stores 87368516 # Number of stores executed -system.cpu.iew.exec_rate 2.707829 # Inst execution rate -system.cpu.iew.wb_sent 368827623 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 368158257 # cumulative count of insts written-back -system.cpu.iew.wb_producers 183056844 # num instructions producing a value -system.cpu.iew.wb_consumers 364050324 # num instructions consuming a value +system.cpu.iew.exec_nop 1580 # number of nop insts executed +system.cpu.iew.exec_refs 187474433 # number of memory reference insts executed +system.cpu.iew.exec_branches 31994663 # Number of branches executed +system.cpu.iew.exec_stores 87233435 # Number of stores executed +system.cpu.iew.exec_rate 2.710563 # Inst execution rate +system.cpu.iew.wb_sent 368586369 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 367930985 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182884452 # num instructions producing a value +system.cpu.iew.wb_consumers 363518435 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.692865 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502834 # average fanout of values written-back +system.cpu.iew.wb_rate 2.695695 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503095 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 35184491 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34865105 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1583973 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131408979 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.656326 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.660791 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1563496 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131214438 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.660264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659830 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34626776 26.35% 26.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28501850 21.69% 48.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13315357 10.13% 58.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11364955 8.65% 66.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13794993 10.50% 77.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7395322 5.63% 82.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3829564 2.91% 85.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3937630 3.00% 88.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14642532 11.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34444562 26.25% 26.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28434634 21.67% 47.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13308561 10.14% 58.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11464288 8.74% 66.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13753280 10.48% 77.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7411902 5.65% 82.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3868194 2.95% 85.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3893489 2.97% 88.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14635528 11.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131408979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131214438 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 177024331 # Number of memory references committed system.cpu.commit.loads 94648748 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 36546710 # Number of branches committed +system.cpu.commit.branches 30563497 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14642532 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14635528 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 501013476 # The number of ROB reads -system.cpu.rob.rob_writes 773587232 # The number of ROB writes -system.cpu.timesIdled 6387 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223029 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 500506553 # The number of ROB reads +system.cpu.rob.rob_writes 772913753 # The number of ROB writes +system.cpu.timesIdled 6384 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 224310 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.500725 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.500725 # CPI: Total CPI of All Threads -system.cpu.ipc 1.997106 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.997106 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1769939132 # number of integer regfile reads -system.cpu.int_regfile_writes 232882500 # number of integer regfile writes -system.cpu.fp_regfile_reads 188356577 # number of floating regfile reads -system.cpu.fp_regfile_writes 132592082 # number of floating regfile writes -system.cpu.misc_regfile_reads 567391435 # number of misc regfile reads +system.cpu.cpi 0.499890 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.499890 # CPI: Total CPI of All Threads +system.cpu.ipc 2.000440 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.000440 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768566472 # number of integer regfile reads +system.cpu.int_regfile_writes 232719908 # number of integer regfile writes +system.cpu.fp_regfile_reads 188077369 # number of floating regfile reads +system.cpu.fp_regfile_writes 132460333 # number of floating regfile writes +system.cpu.misc_regfile_reads 566743063 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.icache.replacements 13893 # number of replacements -system.cpu.icache.tagsinuse 1849.968594 # Cycle average of tags in use -system.cpu.icache.total_refs 37534809 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15782 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2378.330313 # Average number of references to valid blocks. +system.cpu.icache.replacements 13969 # number of replacements +system.cpu.icache.tagsinuse 1853.582812 # Cycle average of tags in use +system.cpu.icache.total_refs 37474292 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15862 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2362.519985 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1849.968594 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.903305 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.903305 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37534809 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37534809 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37534809 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37534809 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37534809 # number of overall hits -system.cpu.icache.overall_hits::total 37534809 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17059 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17059 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17059 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17059 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17059 # number of overall misses -system.cpu.icache.overall_misses::total 17059 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 362452498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 362452498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 362452498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 362452498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 362452498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 362452498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37551868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37551868 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37551868 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37551868 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37551868 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37551868 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000454 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000454 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000454 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000454 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000454 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000454 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21246.995603 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21246.995603 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21246.995603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21246.995603 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21246.995603 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 477 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1853.582812 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.905070 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.905070 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37474292 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37474292 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37474292 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37474292 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37474292 # number of overall hits +system.cpu.icache.overall_hits::total 37474292 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17149 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17149 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17149 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17149 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17149 # number of overall misses +system.cpu.icache.overall_misses::total 17149 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 365626498 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 365626498 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 365626498 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 365626498 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 365626498 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 365626498 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37491441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37491441 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37491441 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37491441 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37491441 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37491441 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000457 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000457 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000457 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000457 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000457 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000457 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21320.572512 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21320.572512 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21320.572512 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21320.572512 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21320.572512 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21320.572512 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 571 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 17 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.058824 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.826087 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1275 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1275 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1275 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1275 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1275 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1275 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15784 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15784 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15784 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15784 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15784 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15784 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 296328498 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 296328498 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 296328498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 296328498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 296328498 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 296328498 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000420 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000420 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000420 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000420 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18773.979853 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18773.979853 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18773.979853 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18773.979853 # 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miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192572 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.932134 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359191 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50704.485920 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54196.535643 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51855.214050 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 48440.850608 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 48440.850608 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50704.485920 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50450.453594 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50555.963552 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50704.485920 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50450.453594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50555.963552 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -666,176 +666,176 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 39 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163905102 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 278952909 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115047807 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163905102 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 278952909 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.815000 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255176 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 101204481 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101204481 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116555085 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162927604 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 279482689 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116555085 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162927604 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 279482689 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191752 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.813578 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255041 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993594 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356940 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191318 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923861 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356940 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38107.918847 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42933.797546 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39686.065091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993961 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993961 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191752 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923677 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356651 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191752 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923677 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356651 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38327.880631 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42218.278386 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39590.985565 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36146.569126 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36146.569126 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38107.918847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38484.409955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38328.237016 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36170.293424 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36170.293424 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38327.880631 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38245.916432 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38280.056020 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38327.880631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38245.916432 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38280.056020 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1413 # number of replacements -system.cpu.dcache.tagsinuse 3109.949983 # Cycle average of tags in use -system.cpu.dcache.total_refs 170925187 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4610 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37077.047072 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1412 # number of replacements +system.cpu.dcache.tagsinuse 3109.263410 # Cycle average of tags in use +system.cpu.dcache.total_refs 170806114 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4612 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37035.150477 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3109.949983 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.759265 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.759265 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88871803 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88871803 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031525 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031525 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10952 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10952 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 3109.263410 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.759098 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.759098 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88752695 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88752695 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031490 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031490 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11022 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11022 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170903328 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170903328 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170903328 # number of overall hits -system.cpu.dcache.overall_hits::total 170903328 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4023 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4023 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21140 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21140 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170784185 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170784185 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170784185 # number of overall hits +system.cpu.dcache.overall_hits::total 170784185 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4014 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4014 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21175 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21175 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25163 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25163 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25163 # number of overall misses -system.cpu.dcache.overall_misses::total 25163 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177641500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177641500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 874574146 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 874574146 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25189 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25189 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25189 # number of overall misses +system.cpu.dcache.overall_misses::total 25189 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 176938000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 176938000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 876193651 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 876193651 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 116000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1052215646 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1052215646 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1052215646 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1052215646 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88875826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88875826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 1053131651 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1053131651 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1053131651 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1053131651 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88756709 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88756709 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10954 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10954 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11024 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170928491 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170928491 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170928491 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170928491 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 170809374 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170809374 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170809374 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170809374 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000183 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000183 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000181 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000181 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000147 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000147 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000147 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000147 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44156.475267 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44156.475267 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41370.584011 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41370.584011 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44080.219233 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44080.219233 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41378.684817 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41378.684817 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41815.985614 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41815.985614 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41815.985614 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15531 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 796 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 449 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41809.188574 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41809.188574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41809.188574 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41809.188574 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15380 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 834 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 443 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.590200 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.230769 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.717833 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 64.153846 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks -system.cpu.dcache.writebacks::total 1043 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2222 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2222 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18329 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18329 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1038 # number of writebacks +system.cpu.dcache.writebacks::total 1038 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2216 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2216 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18359 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18359 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20551 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20551 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20551 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20551 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1801 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1801 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2811 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2811 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4612 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4612 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4612 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 87720000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 87720000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138213500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 138213500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225933500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 225933500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225933500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 225933500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20575 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20575 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20575 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20575 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1798 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1798 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2816 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2816 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4614 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4614 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4614 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4614 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86261500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 86261500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 138581500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224843000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 224843000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224843000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 224843000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses @@ -844,14 +844,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48706.274292 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48706.274292 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49168.801138 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49168.801138 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48988.183001 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48988.183001 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47976.362625 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47976.362625 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49212.180398 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49212.180398 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48730.602514 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48730.602514 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48730.602514 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48730.602514 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 89ba10791..0f1bf2663 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -527,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 63003fae2..a5e7d0a83 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 20:27:21 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 01:12:21 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1387,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 625047295000 because target called exit() +Exiting @ tick 627439125000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 675c50cd2..2c1851d5a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.627778 # Number of seconds simulated -sim_ticks 627777658000 # Number of ticks simulated -final_tick 627777658000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.627439 # Number of seconds simulated +sim_ticks 627439125000 # Number of ticks simulated +final_tick 627439125000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109787 # Simulator instruction rate (inst/s) -host_op_rate 149515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49785649 # Simulator tick rate (ticks/s) -host_mem_usage 262368 # Number of bytes of host memory used -host_seconds 12609.61 # Real time elapsed on the host +host_inst_rate 96597 # Simulator instruction rate (inst/s) +host_op_rate 131552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43780556 # Simulator tick rate (ticks/s) +host_mem_usage 260984 # Number of bytes of host memory used +host_seconds 14331.46 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 154944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory -system.physmem.bytes_read::total 30397824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154944 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30242368 # Number of bytes read from this memory +system.physmem.bytes_read::total 30397376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474959 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 246813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48174508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48421322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 246813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6738488 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6738488 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6738488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 246813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48174508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55159809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474966 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 247049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48199685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48446733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6742123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6742123 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6742123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48199685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55188857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474959 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545372 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30397824 # Total number of bytes read from memory +system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30397376 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30397824 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30397376 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 160 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4308 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29690 # Track reads on a per bank basis +system.physmem.servicedByWrQ 149 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4291 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29712 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29706 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29691 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29689 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 29720 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29750 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29747 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 29651 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29680 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29627 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29600 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29682 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29629 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29602 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 29611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29633 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29628 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29649 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis @@ -77,14 +77,14 @@ system.physmem.perBankWrReqs::14 4133 # Tr system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 627777588500 # Total gap between requests +system.physmem.totGap 627439056500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474966 # Categorize read packet sizes +system.physmem.readPktSize::6 474959 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,12 +92,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 66098 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 405913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 405906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -156,36 +156,36 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3182824500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 21162788250 # Sum of mem lat for all requests -system.physmem.totBusLat 2374030000 # Total cycles spent in databus access -system.physmem.totBankLat 15605933750 # Total cycles spent in bank access -system.physmem.avgQLat 6703.42 # Average queueing delay per request -system.physmem.avgBankLat 32868.02 # Average bank access latency per request +system.physmem.totQLat 3462811500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 21441489000 # Sum of mem lat for all requests +system.physmem.totBusLat 2374050000 # Total cycles spent in databus access +system.physmem.totBankLat 15604627500 # Total cycles spent in bank access +system.physmem.avgQLat 7293.05 # Average queueing delay per request +system.physmem.avgBankLat 32864.99 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 44571.44 # Average memory access latency -system.physmem.avgRdBW 48.42 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 45158.04 # Average memory access latency +system.physmem.avgRdBW 48.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.42 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.45 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.43 # Data bus utilization in percentage system.physmem.avgRdQLen 0.03 # Average read queue length over time system.physmem.avgWrQLen 17.42 # Average write queue length over time -system.physmem.readRowHits 143321 # Number of row buffer hits during reads -system.physmem.writeRowHits 45521 # Number of row buffer hits during writes +system.physmem.readRowHits 143341 # Number of row buffer hits during reads +system.physmem.writeRowHits 45511 # Number of row buffer hits during writes system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.87 # Row buffer hit rate for writes -system.physmem.avgGap 1160264.94 # Average gap between requests -system.cpu.branchPred.lookups 438315942 # Number of BP lookups -system.cpu.branchPred.condPredicted 349727890 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30635219 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 247833723 # Number of BTB lookups -system.cpu.branchPred.BTBHits 226959266 # Number of BTB hits +system.physmem.writeRowHitRate 68.85 # Row buffer hit rate for writes +system.physmem.avgGap 1159654.26 # Average gap between requests +system.cpu.branchPred.lookups 440649573 # Number of BP lookups +system.cpu.branchPred.condPredicted 353682166 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30631043 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 252533039 # Number of BTB lookups +system.cpu.branchPred.BTBHits 230279415 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.577233 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 52304914 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806740 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.187837 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 51764959 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806562 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,100 +229,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1255555317 # number of cpu cycles simulated +system.cpu.numCycles 1254878251 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 353470076 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2285596018 # Number of instructions fetch has processed -system.cpu.fetch.Branches 438315942 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 279264180 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 600835401 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 157814267 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 132517239 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11276 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 333121635 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10719821 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1213961612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.592462 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.190927 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 354654463 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2286055838 # Number of instructions fetch has processed +system.cpu.fetch.Branches 440649573 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282044374 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601927539 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 156613440 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 130193180 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 518 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10572 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 335557697 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11970074 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1212716808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.588686 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.181757 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 613170569 50.51% 50.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42771992 3.52% 54.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 95714848 7.88% 61.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55497081 4.57% 66.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 71974346 5.93% 72.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 42167023 3.47% 75.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30997748 2.55% 78.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31607119 2.60% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 230060886 18.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 610833811 50.37% 50.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43093126 3.55% 53.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 96161904 7.93% 61.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 57061464 4.71% 66.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 71748155 5.92% 72.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 43390011 3.58% 76.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 30893705 2.55% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 32839857 2.71% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226694775 18.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1213961612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.349101 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.820387 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 402973570 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105164432 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561876513 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16833922 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 127113175 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44705454 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 15362 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3047243320 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28333 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 127113175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 438520828 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34437480 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 439400 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 541081761 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 72368968 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2975054899 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4810930 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 57090211 # Number of times rename has blocked due to LSQ full +system.cpu.fetch.rateDist::total 1212716808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.351149 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.821735 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405646781 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 102637713 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 561793047 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16722466 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 125916801 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 44665335 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13931 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3029413956 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28108 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 125916801 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441580002 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 34476908 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 437379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 540507560 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 69798158 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2946364126 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 76 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4812832 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54672934 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2946030115 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14164064845 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13593631976 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 570432869 # Number of floating rename lookups +system.cpu.rename.RenamedOperands 2931066413 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14023290204 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13452684524 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570605680 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 952890025 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25236 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 22720 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 195466614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 973207403 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 490834559 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36203648 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40613980 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2806590515 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29404 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2437414876 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13391013 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 908731819 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2361150824 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 8020 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1213961612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.007819 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.875089 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 937926323 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 22415 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19926 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179121288 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 970649993 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 487168712 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36377618 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 40069949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2792240287 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29328 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2432835777 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13263841 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 894381457 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2312630775 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 7944 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1212716808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.006104 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 377942739 31.13% 31.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183591536 15.12% 46.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 202672014 16.70% 62.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169721523 13.98% 76.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132842970 10.94% 87.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 93759245 7.72% 95.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37926008 3.12% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12454026 1.03% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3051551 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 376728714 31.06% 31.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183811265 15.16% 46.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 203907049 16.81% 63.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169580498 13.98% 77.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132860198 10.96% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92416507 7.62% 95.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37964146 3.13% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12426731 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3021700 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1213961612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1212716808 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 716787 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24382 0.03% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 716116 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24381 0.03% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available @@ -350,322 +350,322 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55152382 62.89% 63.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31800755 36.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55122687 62.92% 63.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31746374 36.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1108357154 45.47% 45.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223525 0.46% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5502588 0.23% 46.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.50% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23405386 0.96% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838249094 34.39% 81.85% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442425361 18.15% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1103971506 45.38% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11223452 0.46% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502427 0.23% 46.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23409752 0.96% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838269607 34.46% 81.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 442207267 18.18% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2437414876 # Type of FU issued -system.cpu.iq.rate 1.941304 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87694306 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035978 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6067362312 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3632711697 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2254358254 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122514371 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82707334 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56439819 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2461788341 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63320841 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84306513 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2432835777 # Type of FU issued +system.cpu.iq.rate 1.938703 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87609558 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036011 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6056740662 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3603968769 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2248867979 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122521099 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82749412 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56444030 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2457121441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63323894 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84335781 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 341820222 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8583 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429956 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 213839262 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 339262812 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8485 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1431215 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 210173415 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 315 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 311 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 127113175 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12638633 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1558332 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2806632387 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1396294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 973207403 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 490834559 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19418 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1554341 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 125916801 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12646480 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1559895 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2792282007 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1384453 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 970649993 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 487168712 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19342 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1555909 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2519 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429956 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32461974 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1494406 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33956380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2363518752 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792548156 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 73896124 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 1431215 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32433063 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1530059 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33963122 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2358070725 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792574818 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 74765052 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12468 # number of nop insts executed -system.cpu.iew.exec_refs 1216269086 # number of memory reference insts executed -system.cpu.iew.exec_branches 322574286 # Number of branches executed -system.cpu.iew.exec_stores 423720930 # Number of stores executed -system.cpu.iew.exec_rate 1.882449 # Inst execution rate -system.cpu.iew.wb_sent 2336489228 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2310798073 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347631579 # num instructions producing a value -system.cpu.iew.wb_consumers 2523967689 # num instructions consuming a value +system.cpu.iew.exec_nop 12392 # number of nop insts executed +system.cpu.iew.exec_refs 1216182478 # number of memory reference insts executed +system.cpu.iew.exec_branches 319878188 # Number of branches executed +system.cpu.iew.exec_stores 423607660 # Number of stores executed +system.cpu.iew.exec_rate 1.879123 # Inst execution rate +system.cpu.iew.wb_sent 2331089515 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2305312009 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347373640 # num instructions producing a value +system.cpu.iew.wb_consumers 2522763992 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.840459 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533934 # average fanout of values written-back +system.cpu.iew.wb_rate 1.837080 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534086 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 921296175 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 906945779 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30621418 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1086848437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.734682 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.398805 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30617374 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1086800007 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.734759 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.398832 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 446548721 41.09% 41.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288590719 26.55% 67.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95114953 8.75% 76.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70229595 6.46% 82.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46461870 4.27% 87.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22187798 2.04% 89.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15847039 1.46% 90.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10983692 1.01% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90884050 8.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 446471329 41.08% 41.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288644992 26.56% 67.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95109223 8.75% 76.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70211025 6.46% 82.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46444999 4.27% 87.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22203598 2.04% 89.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15846659 1.46% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10983551 1.01% 91.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90884631 8.36% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1086848437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1086800007 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 908382478 # Number of memory references committed system.cpu.commit.loads 631387181 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 299634395 # Number of branches committed +system.cpu.commit.branches 298259106 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90884050 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90884631 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3802578575 # The number of ROB reads -system.cpu.rob.rob_writes 5740389473 # The number of ROB writes -system.cpu.timesIdled 353174 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 41593705 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3788179168 # The number of ROB reads +system.cpu.rob.rob_writes 5710492063 # The number of ROB writes +system.cpu.timesIdled 353297 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42161443 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.906950 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.906950 # CPI: Total CPI of All Threads -system.cpu.ipc 1.102596 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.102596 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11774707263 # number of integer regfile reads -system.cpu.int_regfile_writes 2226782267 # number of integer regfile writes -system.cpu.fp_regfile_reads 68797357 # number of floating regfile reads -system.cpu.fp_regfile_writes 49551943 # number of floating regfile writes -system.cpu.misc_regfile_reads 1364040345 # number of misc regfile reads +system.cpu.cpi 0.906461 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.906461 # CPI: Total CPI of All Threads +system.cpu.ipc 1.103191 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.103191 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11756795674 # number of integer regfile reads +system.cpu.int_regfile_writes 2218922402 # number of integer regfile writes +system.cpu.fp_regfile_reads 68796713 # number of floating regfile reads +system.cpu.fp_regfile_writes 49556201 # number of floating regfile writes +system.cpu.misc_regfile_reads 1363984791 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.icache.replacements 22740 # number of replacements -system.cpu.icache.tagsinuse 1642.119596 # Cycle average of tags in use -system.cpu.icache.total_refs 333085977 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24420 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13639.884398 # Average number of references to valid blocks. +system.cpu.icache.replacements 22806 # number of replacements +system.cpu.icache.tagsinuse 1643.708828 # Cycle average of tags in use +system.cpu.icache.total_refs 335522072 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24489 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13700.929887 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1642.119596 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.801816 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.801816 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 333090004 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 333090004 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 333090004 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 333090004 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 333090004 # number of overall hits -system.cpu.icache.overall_hits::total 333090004 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 31630 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 31630 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 31630 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 31630 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 31630 # number of overall misses -system.cpu.icache.overall_misses::total 31630 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 481232999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 481232999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 481232999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 481232999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 481232999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 481232999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 333121634 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 333121634 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 333121634 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 333121634 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 333121634 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 333121634 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000095 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000095 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000095 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000095 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000095 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000095 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15214.448277 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15214.448277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15214.448277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15214.448277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15214.448277 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1643.708828 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.802592 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.802592 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 335526084 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 335526084 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 335526084 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 335526084 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 335526084 # number of overall hits +system.cpu.icache.overall_hits::total 335526084 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 31612 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 31612 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 31612 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 31612 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 31612 # number of overall misses +system.cpu.icache.overall_misses::total 31612 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 479792499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 479792499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 479792499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 479792499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 479792499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 479792499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 335557696 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 335557696 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 335557696 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 335557696 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 335557696 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 335557696 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15177.543306 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15177.543306 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15177.543306 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15177.543306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15177.543306 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15177.543306 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 835 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 25 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 32.692308 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2899 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2899 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2899 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2899 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2899 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2899 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28731 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 28731 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 28731 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 28731 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 28731 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 28731 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386564499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 386564499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386564499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 386564499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386564499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 386564499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2827 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2827 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2827 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2827 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2827 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28785 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 28785 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 28785 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 28785 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 28785 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 28785 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386126499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 386126499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386126499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 386126499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 386126499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 386126499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13454.613449 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13454.613449 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13454.613449 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13454.613449 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13414.156644 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13414.156644 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13414.156644 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13414.156644 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13414.156644 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13414.156644 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 442184 # number of replacements -system.cpu.l2cache.tagsinuse 32692.574562 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1110053 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 474931 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.337293 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 442178 # number of replacements +system.cpu.l2cache.tagsinuse 32692.553116 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1110010 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 474925 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.337232 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1286.532429 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 50.222145 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31355.819987 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039262 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 1287.010485 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 50.235756 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31355.306875 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.039276 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.inst 0.001533 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.956904 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.956888 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.997698 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 21996 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1058215 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1080211 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 96321 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 96321 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 6442 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 6442 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21996 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1064657 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1086653 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21996 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1064657 # number of overall hits -system.cpu.l2cache.overall_hits::total 1086653 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2425 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 406491 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 408916 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4308 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4308 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2425 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 472566 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 474991 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2425 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 472566 # number of overall misses -system.cpu.l2cache.overall_misses::total 474991 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 133322500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28783806000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28917128500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3174251000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3174251000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 133322500 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55796.582001 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55726.717788 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533127 # number of replacements -system.cpu.dcache.tagsinuse 4094.656080 # Cycle average of tags in use -system.cpu.dcache.total_refs 969988245 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 631.000346 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1533005 # number of replacements +system.cpu.dcache.tagsinuse 4094.655355 # Cycle average of tags in use +system.cpu.dcache.total_refs 969956043 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537101 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 631.029479 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 319304000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.656080 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 4094.655355 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999672 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999672 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 693861536 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 693861536 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276093810 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276093810 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 693829407 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 693829407 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276093791 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276093791 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9998 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9998 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 969955346 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 969955346 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 969955346 # number of overall hits -system.cpu.dcache.overall_hits::total 969955346 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1953541 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1953541 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 841868 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 841868 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 969923198 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 969923198 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 969923198 # number of overall hits +system.cpu.dcache.overall_hits::total 969923198 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953276 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953276 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 841887 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 841887 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2795409 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2795409 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2795409 # number of overall misses -system.cpu.dcache.overall_misses::total 2795409 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 66484216000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 66484216000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39427025969 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39427025969 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 215500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 215500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 105911241969 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 105911241969 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 105911241969 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 105911241969 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695815077 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695815077 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2795163 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795163 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795163 # number of overall misses +system.cpu.dcache.overall_misses::total 2795163 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66762023500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66762023500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 39426392469 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 39426392469 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106188415969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106188415969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106188415969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106188415969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695782683 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695782683 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10001 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972750755 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972750755 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972750755 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972750755 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972718361 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972718361 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972718361 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972718361 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003040 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.003040 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses @@ -801,52 +801,52 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34032.669906 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34032.669906 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46832.788476 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46832.788476 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37887.565637 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37887.565637 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37887.565637 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34179.513545 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34179.513545 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46830.979061 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46830.979061 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37990.062107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37990.062107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37990.062107 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 1756 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 747 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 726 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 57 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 90 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807018 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.300000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.157303 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96321 # number of writebacks -system.cpu.dcache.writebacks::total 96321 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488834 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488834 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765041 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765041 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96323 # number of writebacks +system.cpu.dcache.writebacks::total 96323 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488688 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488688 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765077 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765077 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1253875 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1253875 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1253875 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1253875 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464707 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464707 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76827 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541534 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541534 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541534 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541534 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40831573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40831573000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3409419500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3409419500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44240992500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44240992500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44240992500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44240992500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 1253765 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1253765 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1253765 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1253765 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464588 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464588 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76810 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76810 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541398 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541398 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541398 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541398 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41111704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41111704000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3408970500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3408970500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44520674500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44520674500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44520674500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44520674500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses @@ -855,14 +855,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27876.956279 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27876.956279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44377.881474 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44377.881474 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28699.329694 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28699.329694 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28070.490814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28070.490814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44381.857831 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44381.857831 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28883.308853 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28883.308853 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 0d9336fbc..39e20487b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -527,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr index e45cd058f..b6a1a957f 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections +warn: CP14 unimplemented crn[15], opc1[7], crm[8], opc2[4] hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index b7ae68a85..9f7f9be51 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,13 +1,11 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 20:59:12 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 01:35:26 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 26275145500 because target called exit() +Exiting @ tick 25578307500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bd8287e69..6f25374e1 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.025578 # Number of seconds simulated -sim_ticks 25577832000 # Number of ticks simulated -final_tick 25577832000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25578307500 # Number of ticks simulated +final_tick 25578307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133487 # Simulator instruction rate (inst/s) -host_op_rate 189436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48151664 # Simulator tick rate (ticks/s) -host_mem_usage 268312 # Number of bytes of host memory used -host_seconds 531.19 # Real time elapsed on the host +host_inst_rate 122516 # Simulator instruction rate (inst/s) +host_op_rate 173866 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44194830 # Simulator tick rate (ticks/s) +host_mem_usage 267056 # Number of bytes of host memory used +host_seconds 578.76 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943552 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372416 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128779 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83944 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83944 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11662599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 310563929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 322226528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11662599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11662599 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 210041883 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 210041883 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 210041883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11662599 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 310563929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 532268411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128779 # Total number of read requests seen -system.physmem.writeReqs 83944 # Total number of write requests seen -system.physmem.cpureqs 213035 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8241856 # Total number of bytes read from memory -system.physmem.bytesWritten 5372416 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8241856 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372416 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7943424 # Number of bytes read from this memory +system.physmem.bytes_read::total 8241536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372288 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124116 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128774 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83942 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83942 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11654876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 310553151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 322208027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11654876 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11654876 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 210032974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 210032974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 210032974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11654876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 310553151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 532241001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128775 # Total number of read requests seen +system.physmem.writeReqs 83942 # Total number of write requests seen +system.physmem.cpureqs 213036 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8241536 # Total number of bytes read from memory +system.physmem.bytesWritten 5372288 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8241536 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372288 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 7976 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8062 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8171 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 319 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 7977 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8191 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8064 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8170 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8108 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 8006 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 8046 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 7997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7991 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7993 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8127 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8038 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 7996 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 8126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 8035 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7981 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7987 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 7944 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5141 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 5142 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 5262 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5371 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5372 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5263 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5277 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 5311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5350 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5125 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5133 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25577735000 # Total gap between requests +system.physmem.totGap 25578289000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128779 # Categorize read packet sizes +system.physmem.readPktSize::6 128775 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83944 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56485 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83942 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 70073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 56517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,11 +124,11 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3640 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -139,53 +139,53 @@ system.physmem.wrQLenPdf::11 3650 # Wh system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3204596500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5248699000 # Sum of mem lat for all requests -system.physmem.totBusLat 643885000 # Total cycles spent in databus access -system.physmem.totBankLat 1400217500 # Total cycles spent in bank access -system.physmem.avgQLat 24884.85 # Average queueing delay per request -system.physmem.avgBankLat 10873.20 # Average bank access latency per request +system.physmem.totQLat 3208033250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 5250782000 # Sum of mem lat for all requests +system.physmem.totBusLat 643865000 # Total cycles spent in databus access +system.physmem.totBankLat 1398883750 # Total cycles spent in bank access +system.physmem.avgQLat 24912.31 # Average queueing delay per request +system.physmem.avgBankLat 10863.18 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40758.05 # Average memory access latency -system.physmem.avgRdBW 322.23 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 210.04 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 322.23 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 210.04 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 40775.49 # Average memory access latency +system.physmem.avgRdBW 322.21 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 210.03 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 322.21 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 210.03 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 4.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.21 # Average read queue length over time -system.physmem.avgWrQLen 9.73 # Average write queue length over time -system.physmem.readRowHits 116758 # Number of row buffer hits during reads -system.physmem.writeRowHits 52879 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.59 # Average write queue length over time +system.physmem.readRowHits 116753 # Number of row buffer hits during reads +system.physmem.writeRowHits 52875 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate 62.99 # Row buffer hit rate for writes -system.physmem.avgGap 120239.63 # Average gap between requests -system.cpu.branchPred.lookups 16629564 # Number of BP lookups -system.cpu.branchPred.condPredicted 12762911 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 603280 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10503277 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7769578 # Number of BTB hits +system.physmem.avgGap 120245.63 # Average gap between requests +system.cpu.branchPred.lookups 16623364 # Number of BP lookups +system.cpu.branchPred.condPredicted 12760071 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 602765 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10462695 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7764975 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.972894 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1825196 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113459 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 74.215821 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1825729 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113390 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +229,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 51155665 # number of cpu cycles simulated +system.cpu.numCycles 51156616 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12532708 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85214691 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16629564 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9594774 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21193802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2370777 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10561405 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 619 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11680132 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179651 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46029532 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.592208 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.335378 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12528030 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85177625 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16623364 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9590704 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21186632 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2363015 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10581483 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 64 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 556 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11675113 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 179601 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46030680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.591102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.335075 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24855932 54.00% 54.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2137922 4.64% 58.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1963242 4.27% 62.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2041100 4.43% 67.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1466538 3.19% 70.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1380808 3.00% 73.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 959441 2.08% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1192836 2.59% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10031713 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24864286 54.02% 54.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2136700 4.64% 58.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1964680 4.27% 62.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2042011 4.44% 67.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1465176 3.18% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1378812 3.00% 73.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 958023 2.08% 75.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1192746 2.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10028246 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46029532 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.325078 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.665792 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14615115 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8910863 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19475067 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1390462 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1638025 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3332403 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 104704 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116875388 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 362618 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1638025 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16327942 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2554176 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 876402 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19102307 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5530680 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 115006208 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 128 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 16441 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4672604 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 267 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115315076 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529845478 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529838377 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7101 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46030680 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324950 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.665036 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14611647 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8930047 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19464619 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1393461 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1630906 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3329793 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104768 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116826129 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 364020 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1630906 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16323488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2561901 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 880060 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19095828 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5538497 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114955733 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 140 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 16360 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4684188 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 269 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115265758 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529627924 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529622592 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5332 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16182404 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20249 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20243 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13070399 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29628857 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22448482 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3867260 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4365710 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111562544 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35868 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107265054 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 274406 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10824806 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25919657 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2082 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46029532 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.330353 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.988634 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16133086 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20210 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13085457 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29620481 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22434207 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3897313 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4409985 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111515856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35838 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107234062 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 271666 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10778201 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25823888 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2052 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46030680 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.329622 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.987561 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10776737 23.41% 23.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8085644 17.57% 40.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7427640 16.14% 57.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7135127 15.50% 72.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5408613 11.75% 84.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3911083 8.50% 92.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1839405 4.00% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 869812 1.89% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 575471 1.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10772740 23.40% 23.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8089543 17.57% 40.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7436956 16.16% 57.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7132439 15.49% 72.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5411666 11.76% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3908589 8.49% 92.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1839107 4.00% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 868081 1.89% 98.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 571559 1.24% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46029532 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46030680 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112614 4.57% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1347948 54.70% 59.28% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1003472 40.72% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112263 4.55% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1357458 55.03% 59.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 996979 40.42% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56638968 52.80% 52.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91700 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56624593 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91608 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 212 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 187 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued @@ -384,292 +384,292 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28903478 26.95% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21630689 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28897959 26.95% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21619708 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107265054 # Type of FU issued -system.cpu.iq.rate 2.096836 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2464036 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022971 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263297485 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122451085 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105577838 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 597 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 998 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109728798 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 292 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2178424 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107234062 # Type of FU issued +system.cpu.iq.rate 2.096191 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2466700 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023003 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263236655 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122357738 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105553758 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 515 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 808 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 170 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109700502 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 260 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2179129 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2321749 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6850 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30026 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1892744 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2313373 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6760 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29813 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1878469 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 510 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 507 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1638025 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1048533 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45693 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111608173 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 293378 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29628857 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22448482 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19948 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6875 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5227 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30026 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 391684 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 181878 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 573562 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106234971 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28603939 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030083 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1630906 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1049242 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 45608 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111561445 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 293593 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29620481 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22434207 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19918 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6795 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5249 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29813 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 391440 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181697 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573137 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106207608 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28598944 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1026454 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9761 # number of nop insts executed -system.cpu.iew.exec_refs 49948503 # number of memory reference insts executed -system.cpu.iew.exec_branches 14602542 # Number of branches executed -system.cpu.iew.exec_stores 21344564 # Number of stores executed -system.cpu.iew.exec_rate 2.076700 # Inst execution rate -system.cpu.iew.wb_sent 105797758 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105578007 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53282087 # num instructions producing a value -system.cpu.iew.wb_consumers 103565099 # num instructions consuming a value +system.cpu.iew.exec_nop 9751 # number of nop insts executed +system.cpu.iew.exec_refs 49933957 # number of memory reference insts executed +system.cpu.iew.exec_branches 14599960 # Number of branches executed +system.cpu.iew.exec_stores 21335013 # Number of stores executed +system.cpu.iew.exec_rate 2.076127 # Inst execution rate +system.cpu.iew.wb_sent 105772826 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105553928 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53290488 # num instructions producing a value +system.cpu.iew.wb_consumers 103570522 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.063858 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514479 # average fanout of values written-back +system.cpu.iew.wb_rate 2.063349 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514533 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10976636 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10929916 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 500410 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44391507 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.266930 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.764737 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 499809 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44399774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.266508 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.764024 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15317930 34.51% 34.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11646230 26.24% 60.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3462929 7.80% 68.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2873664 6.47% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1875708 4.23% 79.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1949349 4.39% 83.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 685850 1.55% 85.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 564105 1.27% 86.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6015742 13.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15322992 34.51% 34.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11640164 26.22% 60.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3466305 7.81% 68.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2879897 6.49% 75.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880990 4.24% 79.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1948005 4.39% 83.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 685170 1.54% 85.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 565050 1.27% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6011201 13.54% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44391507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44399774 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 47862846 # Number of memory references committed system.cpu.commit.loads 27307108 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13741505 # Number of branches committed +system.cpu.commit.branches 13741485 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6015742 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6011201 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149959530 # The number of ROB reads -system.cpu.rob.rob_writes 224865260 # The number of ROB writes -system.cpu.timesIdled 74070 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5126133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 149925618 # The number of ROB reads +system.cpu.rob.rob_writes 224764611 # The number of ROB writes +system.cpu.timesIdled 74074 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5125936 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.721441 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.721441 # CPI: Total CPI of All Threads -system.cpu.ipc 1.386115 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.386115 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511661173 # number of integer regfile reads -system.cpu.int_regfile_writes 103341311 # number of integer regfile writes -system.cpu.fp_regfile_reads 804 # number of floating regfile reads -system.cpu.fp_regfile_writes 688 # number of floating regfile writes -system.cpu.misc_regfile_reads 49186243 # number of misc regfile reads +system.cpu.cpi 0.721454 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.721454 # CPI: Total CPI of All Threads +system.cpu.ipc 1.386089 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.386089 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511542927 # number of integer regfile reads +system.cpu.int_regfile_writes 103323311 # number of integer regfile writes +system.cpu.fp_regfile_reads 788 # number of floating regfile reads +system.cpu.fp_regfile_writes 660 # number of floating regfile writes +system.cpu.misc_regfile_reads 49174075 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.icache.replacements 28586 # number of replacements -system.cpu.icache.tagsinuse 1814.278271 # Cycle average of tags in use -system.cpu.icache.total_refs 11645439 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30619 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 380.333747 # Average number of references to valid blocks. +system.cpu.icache.replacements 28620 # number of replacements +system.cpu.icache.tagsinuse 1814.212486 # Cycle average of tags in use +system.cpu.icache.total_refs 11640356 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 30656 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 379.708899 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.278271 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885878 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885878 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11645446 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11645446 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11645446 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11645446 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11645446 # number of overall hits -system.cpu.icache.overall_hits::total 11645446 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34686 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34686 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34686 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34686 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34686 # number of overall misses -system.cpu.icache.overall_misses::total 34686 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739337000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739337000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 739337000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739337000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 739337000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739337000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11680132 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11680132 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11680132 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11680132 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11680132 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11680132 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002970 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002970 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002970 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002970 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21315.141556 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21315.141556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21315.141556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21315.141556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21315.141556 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 761 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1814.212486 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885846 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885846 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11640361 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11640361 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11640361 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11640361 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11640361 # number of overall hits +system.cpu.icache.overall_hits::total 11640361 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 34752 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 34752 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 34752 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 34752 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 34752 # number of overall misses +system.cpu.icache.overall_misses::total 34752 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 732057000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 732057000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 732057000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 732057000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 732057000 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6604408020 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6849454811 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152569 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394681 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.308632 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.943787 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.943787 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955441 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955441 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152569 # 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number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98261042480 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98261042480 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 892500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 892500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102507941480 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102507941480 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102507941480 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102507941480 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26195168 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26195168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1707140 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1707140 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1707140 # number of overall misses +system.cpu.dcache.overall_misses::total 1707140 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4243660500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4243660500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 98452063982 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 98452063982 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 102695724482 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 102695724482 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 102695724482 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 102695724482 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26189302 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26189302 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16026 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16026 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16031 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16031 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46045069 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46045069 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46045069 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46045069 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 46039203 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46039203 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46039203 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46039203 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079732 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079732 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002808 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002808 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037076 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037076 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037076 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037076 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34117.941467 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34117.941467 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62085.341785 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62085.341785 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19833.333333 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60046.100984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60046.100984 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60046.100984 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5655 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079733 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079733 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002807 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002807 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037080 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037080 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037080 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037080 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34100.965093 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34100.965093 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62205.290202 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62205.290202 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 28822.222222 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 28822.222222 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60156.592009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60156.592009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60156.592009 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5240 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 122 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.352459 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.305785 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129109 # number of writebacks -system.cpu.dcache.writebacks::total 129109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69064 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69064 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475334 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475334 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 129088 # number of writebacks +system.cpu.dcache.writebacks::total 129088 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69028 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69028 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475364 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1475364 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1544398 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1544398 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1544398 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1544398 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55413 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55413 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107343 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107343 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162756 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162756 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162756 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162756 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1877758500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1877758500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6803307490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6803307490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8681065990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8681065990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8681065990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8681065990 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002115 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002115 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1544392 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1544392 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1544392 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1544392 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55416 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55416 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162748 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162748 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162748 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162748 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1874890000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1874890000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6816019991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6816019991 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8690909991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8690909991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8690909991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8690909991 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002116 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003535 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003535 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003535 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33886.606031 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33886.606031 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63379.144332 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63379.144332 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53337.916820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53337.916820 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33833.008517 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33833.008517 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63504.080712 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63504.080712 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53401.024842 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53401.024842 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index b3f283cca..c948b1f36 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -527,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -550,25 +552,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index fa5d435db..8a302018f 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 21:12:52 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Mar 3 2013 21:21:53 +gem5 started Mar 4 2013 01:41:28 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 506353996500 because target called exit() +Exiting @ tick 517371024000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index dd9108dcd..8f6283962 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517371 # Nu sim_ticks 517371024000 # Number of ticks simulated final_tick 517371024000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 170437 # Simulator instruction rate (inst/s) -host_op_rate 190135 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57090080 # Simulator tick rate (ticks/s) -host_mem_usage 485276 # Number of bytes of host memory used -host_seconds 9062.36 # Real time elapsed on the host +host_inst_rate 139447 # Simulator instruction rate (inst/s) +host_op_rate 155563 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46709499 # Simulator tick rate (ticks/s) +host_mem_usage 485516 # Number of bytes of host memory used +host_seconds 11076.36 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory @@ -177,13 +177,13 @@ system.physmem.writeRowHits 271156 # Nu system.physmem.readRowHitRate 36.86 # Row buffer hit rate for reads system.physmem.writeRowHitRate 24.63 # Row buffer hit rate for writes system.physmem.avgGap 154562.37 # Average gap between requests -system.cpu.branchPred.lookups 303290886 # Number of BP lookups +system.cpu.branchPred.lookups 303290873 # Number of BP lookups system.cpu.branchPred.condPredicted 249488582 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15222231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 174596646 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 174596633 # Number of BTB lookups system.cpu.branchPred.BTBHits 161469311 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.481336 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 92.481343 # BTB Hit Percentage system.cpu.branchPred.usedRAS 17557313 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 202 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -234,7 +234,7 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 298209547 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 2186343540 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303290886 # Number of branches that fetch encountered +system.cpu.fetch.Branches 303290873 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 179026624 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 435120674 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 87852250 # Number of cycles fetch has spent squashing @@ -430,7 +430,7 @@ system.cpu.iew.iewExecSquashedInsts 29996171 # Nu system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 130 # number of nop insts executed system.cpu.iew.exec_refs 764045166 # number of memory reference insts executed -system.cpu.iew.exec_branches 238330381 # Number of branches executed +system.cpu.iew.exec_branches 238330373 # Number of branches executed system.cpu.iew.exec_stores 190143920 # Number of stores executed system.cpu.iew.exec_rate 1.921365 # Inst execution rate system.cpu.iew.wb_sent 1965882705 # cumulative count of insts sent to commit |