diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/long/se | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/long/se')
90 files changed, 12268 insertions, 12600 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini index 3938653f4..8b738959d 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout index be80117c3..d0ca2b5a8 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 02:29:01 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x45a0240 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -24,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 61589191500 because target called exit() +Exiting @ tick 61240850500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 1f83c039b..8f24165d3 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061280 # Number of seconds simulated -sim_ticks 61279840500 # Number of ticks simulated -final_tick 61279840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061241 # Number of seconds simulated +sim_ticks 61240850500 # Number of ticks simulated +final_tick 61240850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263178 # Simulator instruction rate (inst/s) -host_op_rate 264489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 178002192 # Simulator tick rate (ticks/s) -host_mem_usage 447788 # Number of bytes of host memory used -host_seconds 344.26 # Real time elapsed on the host +host_inst_rate 182783 # Simulator instruction rate (inst/s) +host_op_rate 183693 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123547949 # Simulator tick rate (ticks/s) +host_mem_usage 442472 # Number of bytes of host memory used +host_seconds 495.69 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49536 # Nu system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 808357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15456959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16265316 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 808357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 808357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 808357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15456959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16265316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 808872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15466800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16275672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 808872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 808872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 808872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15466800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16275672 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15574 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61279747000 # Total gap between requests +system.physmem.totGap 61240757000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1531 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 650.032658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 444.829113 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.661041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 243 15.87% 15.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 186 12.15% 28.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 73 4.77% 32.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 4.25% 37.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 75 4.90% 41.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 100 6.53% 48.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 43 2.81% 51.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 51 3.33% 54.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 695 45.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1531 # Bytes accessed per row activation -system.physmem.totQLat 71795500 # Total ticks spent queuing -system.physmem.totMemAccLat 363808000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 644.601036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 438.502120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.393837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 247 16.00% 16.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189 12.24% 28.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 92 5.96% 34.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 68 4.40% 38.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 69 4.47% 43.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 87 5.63% 48.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.59% 51.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 47 3.04% 54.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.66% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1544 # Bytes accessed per row activation +system.physmem.totQLat 73458500 # Total ticks spent queuing +system.physmem.totMemAccLat 365471000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4609.96 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4716.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23359.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23466.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.28 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14039 # Number of row buffer hits during reads +system.physmem.readRowHits 14026 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3934746.82 # Average gap between requests -system.physmem.pageHitRate 90.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6259680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3415500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 3932243.29 # Average gap between requests +system.physmem.pageHitRate 90.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6305040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3440250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63780600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4002367200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2491685460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34581139500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41148640140 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.507037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57518843500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2046200000 # Time in different power states +system.physmem_0.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2494978920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34554891750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41123220960 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.518851 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57475186750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1713017750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1719043250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 5367600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2928750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 57517200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4002367200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2548940535 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34530915750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41147955240 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.495861 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57435989500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2046200000 # Time in different power states +system.physmem_1.refreshEnergy 3999824400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2555622360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34501695750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41122956060 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.514525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57387265750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2044900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1796249000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1807269750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20766613 # Number of BP lookups -system.cpu.branchPred.condPredicted 17069686 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765538 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8958713 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8857097 # Number of BTB hits +system.cpu.branchPred.lookups 20752188 # Number of BP lookups +system.cpu.branchPred.condPredicted 17062075 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 757746 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8939036 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8856390 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.865730 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.075448 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 61984 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,67 +377,67 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122559681 # number of cpu cycles simulated +system.cpu.numCycles 122481701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2197712 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2176622 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.352713 # CPI: cycles per instruction -system.cpu.ipc 0.739255 # IPC: instructions per cycle -system.cpu.tickCycles 109336366 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13223315 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 946108 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.962336 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267632 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 950204 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644203 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20520732500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.962336 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.883047 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.883047 # Average percentage of cache occupancy +system.cpu.cpi 1.351853 # CPI: cycles per instruction +system.cpu.ipc 0.739726 # IPC: instructions per cycle +system.cpu.tickCycles 109255125 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13226576 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 946097 # number of replacements +system.cpu.dcache.tags.tagsinuse 3616.871508 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26263183 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950193 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.639841 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20511562500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.871508 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.883025 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.883025 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 254 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2248 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2246 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463928 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463928 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598652 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598652 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660698 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660698 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55455001 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55455001 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21594211 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21594211 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660690 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660690 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259858 # number of overall hits -system.cpu.dcache.overall_hits::total 26259858 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 914943 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914943 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74283 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74283 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26254901 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26254901 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26255409 # number of overall hits +system.cpu.dcache.overall_hits::total 26255409 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914926 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914926 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74291 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74291 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 989226 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 989226 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 989230 # number of overall misses -system.cpu.dcache.overall_misses::total 989230 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918923000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11918923000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2541568000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2541568000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14460491000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14460491000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14460491000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14460491000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513595 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 989217 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989217 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989221 # number of overall misses +system.cpu.dcache.overall_misses::total 989221 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918942500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11918942500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2542548000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2542548000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14461490500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14461490500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14461490500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14461490500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22509137 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22509137 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -446,28 +446,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248576 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248576 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27249088 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27249088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 27244118 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27244118 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27244630 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27244630 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040647 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040647 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015690 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015690 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036304 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036304 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036303 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036303 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.956871 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.956871 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34214.665536 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34214.665536 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14617.985172 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14617.985172 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.926064 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14617.926064 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.036309 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036309 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036309 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036309 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13027.220234 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13027.220234 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34224.172511 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34224.172511 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14619.128563 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14619.128563 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14619.069450 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14619.069450 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,109 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 943289 # number of writebacks -system.cpu.dcache.writebacks::total 943289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11509 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11509 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27516 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27516 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39025 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39025 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39025 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39025 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903434 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903434 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 943278 # number of writebacks +system.cpu.dcache.writebacks::total 943278 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11501 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11501 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27526 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27526 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39027 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39027 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39027 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39027 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903425 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903425 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46765 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46765 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 950201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 950204 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950204 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865211000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865211000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1480610000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1480610000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 950190 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950190 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950193 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950193 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10865257500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10865257500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1481584500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1481584500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345821000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12345821000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345977500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12345977500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12346842000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12346842000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12346998500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12346998500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.568626 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.568626 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31659.289670 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31659.289670 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034877 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.034877 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034876 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034876 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12026.739906 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12026.739906 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31681.481877 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31681.481877 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52166.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52166.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.852039 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.852039 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.975719 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.975719 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12994.076974 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12994.076974 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12994.200652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12994.200652 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 690.428077 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27792848 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 5 # number of replacements +system.cpu.icache.tags.tagsinuse 689.439690 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27770466 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34654.423940 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34626.516209 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.428077 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337123 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337123 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 689.439690 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336640 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55588102 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55588102 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27792848 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27792848 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27792848 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27792848 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27792848 # number of overall hits -system.cpu.icache.overall_hits::total 27792848 # number of overall hits +system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55543338 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55543338 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27770466 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27770466 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27770466 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27770466 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27770466 # number of overall hits +system.cpu.icache.overall_hits::total 27770466 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 59599500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 59599500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 59599500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 59599500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 59599500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 59599500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27793650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27793650 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27793650 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27793650 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27793650 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27793650 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 60107000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 60107000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 60107000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 60107000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 60107000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 60107000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27771268 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27771268 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27771268 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27771268 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27771268 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27771268 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74313.591022 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74313.591022 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74313.591022 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74313.591022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74313.591022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74313.591022 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74946.384040 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74946.384040 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74946.384040 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74946.384040 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74946.384040 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 58797500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 58797500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 58797500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 58797500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 58797500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 58797500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59305000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59305000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59305000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59305000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59305000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59305000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73313.591022 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73313.591022 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73313.591022 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73313.591022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73313.591022 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73313.591022 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73946.384040 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73946.384040 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73946.384040 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73946.384040 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10246.423743 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1834010 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10245.543243 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1833992 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.889696 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.888539 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9356.530979 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.454442 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.438322 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285539 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020583 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9355.642515 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.444420 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.456307 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285512 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020582 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006575 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312696 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312669 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -632,22 +632,22 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1095 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13876 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15238060 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15238060 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 943289 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 943289 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits +system.cpu.l2cache.tags.tag_accesses 15237898 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15237898 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 943278 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 943278 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 32221 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 32221 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 26 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 26 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903175 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 903175 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903166 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 903166 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 935398 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935424 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 935387 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 935413 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 935398 # number of overall hits -system.cpu.l2cache.overall_hits::total 935424 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 935387 # number of overall hits +system.cpu.l2cache.overall_hits::total 935413 # number of overall hits system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 776 # number of ReadCleanReq misses @@ -660,34 +660,34 @@ system.cpu.l2cache.demand_misses::total 15582 # nu system.cpu.l2cache.overall_misses::cpu.inst 776 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses system.cpu.l2cache.overall_misses::total 15582 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1066648000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1066648000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57320500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 57320500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21756000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21756000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 57320500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1088404000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1145724500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 57320500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1088404000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1145724500 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 943289 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 943289 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1067640500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1067640500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57828000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 57828000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21914500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 21914500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 57828000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1089555000 # 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number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 903437 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903428 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 903428 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 950204 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 950193 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 950995 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 950204 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses +system.cpu.l2cache.overall_accesses::cpu.data 950193 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 950995 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311002 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.311002 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.967581 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.967581 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000290 # miss rate for ReadSharedReq accesses @@ -698,18 +698,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.016385 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967581 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73339.383938 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73339.383938 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73866.623711 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73866.623711 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83038.167939 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83038.167939 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73866.623711 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73511.009050 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73528.719035 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73866.623711 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73511.009050 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73528.719035 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.625138 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.625138 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74520.618557 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74520.618557 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83643.129771 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83643.129771 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73635.155949 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74520.618557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73588.747805 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73635.155949 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -740,73 +740,73 @@ system.cpu.l2cache.demand_mshr_misses::total 15574 system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49433000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 940013000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 989446000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 922200500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 922200500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 49941000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 49941000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 18963500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 18963500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 49941000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 941164000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 991105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 49941000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 941164000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 991105000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311002 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311002 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000283 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63339.383938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63339.383938 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63866.925065 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63866.925065 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73457.031250 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73457.031250 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63866.925065 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63514.391892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63531.912161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63866.925065 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63514.391892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63531.912161 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63407.625138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63407.625138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64523.255814 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64523.255814 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74076.171875 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74076.171875 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64523.255814 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63592.162162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63638.435855 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 943289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2672 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 943278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2674 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 903437 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846366 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2847973 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51328 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121234880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1897118 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1897097 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1897118 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1897097 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1897118 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1891848000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1897097 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891826500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1203998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1425308994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1425292494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadResp 1030 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution @@ -827,9 +827,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21740500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21739500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82134000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82130500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index a092bf499..86dba512f 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -688,9 +688,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf gid=100 -input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index eaa0003ec..976e948eb 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,13 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 10:58:25 -gem5 started Apr 22 2015 11:34:28 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 02:12:41 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x299b730 info: Entering event queue @ 0. Starting simulation... MCF SPEC version 1.6.I @@ -25,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 58202727500 because target called exit() +Exiting @ tick 58182114500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index 263d31358..a3f3e3177 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -118,7 +118,7 @@ eventq_index=0 size=64 [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -166,7 +166,7 @@ eventq_index=0 size=64 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 009ef705f..e66d5ccc4 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,13 @@ +Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout +Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:04:27 -gem5 started Jan 22 2014 19:43:22 -gem5 executing on u200540-lin -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing +gem5 compiled Sep 14 2015 22:05:26 +gem5 started Sep 14 2015 22:06:13 +gem5 executing on ribera.cs.wisc.edu +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 361488530000 because target called exit() +Exiting @ tick 361488535500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index 399eedece..d4aa178ac 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -156,7 +156,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -513,7 +513,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -579,7 +579,7 @@ system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -642,9 +642,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/mcf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf gid=100 -input=/home/stever/m5/dist/cpu2000/data/mcf/smred/input/mcf.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index d8c79ae54..efb33d70a 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 08:10:29 -gem5 started Apr 22 2015 09:28:24 -gem5 executing on phenom -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing +gem5 compiled Sep 14 2015 22:13:36 +gem5 started Sep 14 2015 22:43:54 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -17,12 +19,12 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 +info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 simplex iterations : 2663 -info: Increasing stack size by one page. flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 62113055500 because target called exit() +Exiting @ tick 61602395500 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 6f4514f73..40c2eacfb 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,75 +1,75 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062104 # Number of seconds simulated -sim_ticks 62103992500 # Number of ticks simulated -final_tick 62103992500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061602 # Number of seconds simulated +sim_ticks 61602395500 # Number of ticks simulated +final_tick 61602395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108853 # Simulator instruction rate (inst/s) -host_op_rate 191673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42789284 # Simulator tick rate (ticks/s) -host_mem_usage 455804 # Number of bytes of host memory used -host_seconds 1451.39 # Real time elapsed on the host +host_inst_rate 83209 # Simulator instruction rate (inst/s) +host_op_rate 146518 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32444685 # Simulator tick rate (ticks/s) +host_mem_usage 451056 # Number of bytes of host memory used +host_seconds 1898.69 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1883648 # Number of bytes read from this memory -system.physmem.bytes_read::total 1948480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947008 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 11776 # Number of bytes written to this memory system.physmem.bytes_written::total 11776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29432 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30445 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29424 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30422 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 184 # Number of write requests responded to by this memory system.physmem.num_writes::total 184 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30330546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31374472 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 189617 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 189617 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 189617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30330546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31564090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30446 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 1036843 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30569201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31606044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1036843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1036843 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 191161 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 191161 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 191161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1036843 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30569201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31797205 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30422 # Number of read requests accepted system.physmem.writeReqs 184 # Number of write requests accepted -system.physmem.readBursts 30446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 30422 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 184 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1943488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 1941952 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 5056 # Total number of bytes read from write queue -system.physmem.bytesWritten 10368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1948544 # Total read bytes from the system interface side +system.physmem.bytesWritten 10304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1947008 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 11776 # Total written bytes from the system interface side system.physmem.servicedByWrQ 79 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1927 # Per bank write bursts -system.physmem.perBankRdBursts::1 2069 # Per bank write bursts -system.physmem.perBankRdBursts::2 2026 # Per bank write bursts -system.physmem.perBankRdBursts::3 1929 # Per bank write bursts +system.physmem.perBankRdBursts::0 1928 # Per bank write bursts +system.physmem.perBankRdBursts::1 2065 # Per bank write bursts +system.physmem.perBankRdBursts::2 2023 # Per bank write bursts +system.physmem.perBankRdBursts::3 1928 # Per bank write bursts system.physmem.perBankRdBursts::4 2026 # Per bank write bursts system.physmem.perBankRdBursts::5 1901 # Per bank write bursts -system.physmem.perBankRdBursts::6 1959 # Per bank write bursts -system.physmem.perBankRdBursts::7 1865 # Per bank write bursts +system.physmem.perBankRdBursts::6 1952 # Per bank write bursts +system.physmem.perBankRdBursts::7 1864 # Per bank write bursts system.physmem.perBankRdBursts::8 1938 # Per bank write bursts -system.physmem.perBankRdBursts::9 1937 # Per bank write bursts -system.physmem.perBankRdBursts::10 1805 # Per bank write bursts -system.physmem.perBankRdBursts::11 1796 # Per bank write bursts +system.physmem.perBankRdBursts::9 1932 # Per bank write bursts +system.physmem.perBankRdBursts::10 1804 # Per bank write bursts +system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts -system.physmem.perBankRdBursts::14 1819 # Per bank write bursts +system.physmem.perBankRdBursts::14 1818 # Per bank write bursts system.physmem.perBankRdBursts::15 1778 # Per bank write bursts -system.physmem.perBankWrBursts::0 25 # Per bank write bursts -system.physmem.perBankWrBursts::1 94 # Per bank write bursts -system.physmem.perBankWrBursts::2 8 # Per bank write bursts -system.physmem.perBankWrBursts::3 7 # Per bank write bursts -system.physmem.perBankWrBursts::4 7 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 10 # Per bank write bursts +system.physmem.perBankWrBursts::1 82 # Per bank write bursts +system.physmem.perBankWrBursts::2 7 # Per bank write bursts +system.physmem.perBankWrBursts::3 28 # Per bank write bursts +system.physmem.perBankWrBursts::4 6 # Per bank write bursts +system.physmem.perBankWrBursts::5 7 # Per bank write bursts system.physmem.perBankWrBursts::6 13 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62103972000 # Total gap between requests +system.physmem.totGap 61602210500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30446 # Read request sizes (log2) +system.physmem.readPktSize::6 30422 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,11 +97,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 184 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29885 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 29859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,8 +144,8 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 10 # What write queue length does an incoming req see @@ -153,7 +153,7 @@ system.physmem.wrQLenPdf::20 10 # Wh system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see @@ -193,324 +193,326 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2720 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 718.117647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 516.851204 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 389.329010 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 349 12.83% 12.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 252 9.26% 22.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 126 4.63% 26.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 106 3.90% 30.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 106 3.90% 34.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 118 4.34% 38.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 88 3.24% 42.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 74 2.72% 44.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1501 55.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2720 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 2722 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 716.414401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 516.531797 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 387.717070 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 355 13.04% 13.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 240 8.82% 21.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 126 4.63% 26.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 120 4.41% 30.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 92 3.38% 34.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 131 4.81% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 110 4.04% 43.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 2.46% 45.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1481 54.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2722 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 9 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3367.333333 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 25.147360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10062.626521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3364.888889 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 25.331779 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10055.293027 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 8 88.89% 88.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::29696-30719 1 11.11% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 9 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 9 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 9 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.888889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.873018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.781736 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 11.11% 11.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 7 77.78% 88.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 11.11% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 9 # Writes before turning the bus around for reads -system.physmem.totQLat 131808750 # Total ticks spent queuing -system.physmem.totMemAccLat 701190000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4340.53 # Average queueing delay per DRAM burst +system.physmem.totQLat 132992250 # Total ticks spent queuing +system.physmem.totMemAccLat 701923500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151715000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4382.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23090.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23132.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 31.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 31.38 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 31.61 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.25 # Data bus utilization in percentage -system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 13.82 # Average write queue length when enqueuing -system.physmem.readRowHits 27697 # Number of row buffer hits during reads -system.physmem.writeRowHits 108 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.70 # Row buffer hit rate for writes -system.physmem.avgGap 2027553.77 # Average gap between requests -system.physmem.pageHitRate 91.01 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 10848600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5919375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 122421000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 997920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2874471525 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34740567750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41811500730 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.256335 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57777967000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2073760000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.66 # Average write queue length when enqueuing +system.physmem.readRowHits 27667 # Number of row buffer hits during reads +system.physmem.writeRowHits 105 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.38 # Row buffer hit rate for writes +system.physmem.avgGap 2012749.48 # Average gap between requests +system.physmem.pageHitRate 90.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 10924200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5960625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 122031000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 991440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2832651765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34473588000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41469365190 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.233667 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57335439750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2251676750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2206407250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114371400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9608760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5242875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114207600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4056274560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3081237030 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34559194500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41826144555 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.492132 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57475856750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2073760000 # Time in different power states +system.physmem_1.refreshEnergy 4023218160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3020113080 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34309140000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41481582315 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.432156 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57061058750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2056860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2554341750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2480990750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37407153 # Number of BP lookups -system.cpu.branchPred.condPredicted 37407153 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 797525 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21397569 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21291133 # Number of BTB hits +system.cpu.branchPred.lookups 36908902 # Number of BP lookups +system.cpu.branchPred.condPredicted 36908902 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 741640 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 21094595 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21013332 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.502579 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5522199 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5378 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.614769 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5443329 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4414 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 124207986 # number of cpu cycles simulated +system.cpu.numCycles 123204792 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28243826 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 201531916 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37407153 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26813332 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 95053081 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1666271 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 14570 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27815548 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 199030226 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36908902 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26456661 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 94542157 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1553197 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 368 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5286 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 27854872 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 208775 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 124145503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.860655 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.369153 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 27443892 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 182896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 123139971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.847273 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.366420 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 63227150 50.93% 50.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3664165 2.95% 53.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3505505 2.82% 56.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5966108 4.81% 61.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7642313 6.16% 67.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5450974 4.39% 72.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3347715 2.70% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2079081 1.67% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29262492 23.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 62945586 51.12% 51.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3649644 2.96% 54.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3480667 2.83% 56.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5913875 4.80% 61.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7544210 6.13% 67.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5413973 4.40% 72.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3251113 2.64% 74.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2020097 1.64% 76.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 28920806 23.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 124145503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.301165 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.622536 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13298609 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63688691 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 36532978 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9792090 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 833135 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 335053232 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 833135 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18606460 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8830273 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16174 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40807487 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 55051974 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328692220 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2265 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 765831 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48323645 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4961410 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 330669691 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 873156420 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537756143 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 567 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 123139971 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.299574 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.615442 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12941533 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63708539 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 35887594 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9825707 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 776598 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 331225454 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 776598 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18253440 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8529181 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16791 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 40202739 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55361222 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 325142962 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1786 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 778279 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48626761 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4947640 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 327068193 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 863737847 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 532004044 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 425 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51456944 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 481 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 481 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66169497 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106330183 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36531613 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49817317 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8395275 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 325507363 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2500 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 308019505 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50533 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 47317399 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68952386 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2055 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 124145503 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.481117 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.143684 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47855446 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 492 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 490 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 66412230 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36169393 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49402360 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8500454 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322302016 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1714 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 306103022 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 44111266 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 63884636 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1269 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 123139971 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.485814 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.139103 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30872061 24.87% 24.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19525697 15.73% 40.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16787256 13.52% 54.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17357634 13.98% 68.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 14846406 11.96% 80.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12689504 10.22% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6302474 5.08% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3917362 3.16% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1847109 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30260082 24.57% 24.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19566754 15.89% 40.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16687046 13.55% 54.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17331207 14.07% 68.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14759369 11.99% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12567445 10.21% 90.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6273255 5.09% 95.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3904180 3.17% 98.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1790633 1.45% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 124145503 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 123139971 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 329941 8.31% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3456308 87.04% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 184474 4.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 338797 8.53% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3433517 86.49% 95.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 197609 4.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 175410718 56.95% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11212 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 340 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98529790 31.99% 88.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34034069 11.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33341 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 174121945 56.88% 56.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11182 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 343 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98066351 32.04% 88.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33869829 11.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 308019505 # Type of FU issued -system.cpu.iq.rate 2.479869 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3970723 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012891 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 744205245 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 372866875 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 306008038 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 524 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 864 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 168 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 311956642 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 248 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58273942 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 306103022 # Type of FU issued +system.cpu.iq.rate 2.484506 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3969923 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012969 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 739361487 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 366454631 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 304282654 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 357 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 618 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 133 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 310039424 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 58196276 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15550798 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67136 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41716 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5091861 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14556809 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 63678 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41328 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4729641 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3678 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 142532 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3641 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141546 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 833135 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5706209 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3030570 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 325509863 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125935 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106330183 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36531613 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 471 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2800 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3033928 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41716 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 402612 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445047 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847659 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 306958421 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98183223 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1061084 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 776598 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5329301 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3100547 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322303730 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36169393 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3102570 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 371679 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 414777 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 786456 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 305156723 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 97750585 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 946299 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 132003276 # number of memory reference insts executed -system.cpu.iew.exec_branches 31537655 # Number of branches executed -system.cpu.iew.exec_stores 33820053 # Number of stores executed -system.cpu.iew.exec_rate 2.471326 # Inst execution rate -system.cpu.iew.wb_sent 306335531 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 306008206 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231609196 # num instructions producing a value -system.cpu.iew.wb_consumers 336109097 # num instructions consuming a value +system.cpu.iew.exec_refs 131430383 # number of memory reference insts executed +system.cpu.iew.exec_branches 31401847 # Number of branches executed +system.cpu.iew.exec_stores 33679798 # Number of stores executed +system.cpu.iew.exec_rate 2.476825 # Inst execution rate +system.cpu.iew.wb_sent 304565841 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 304282787 # cumulative count of insts written-back +system.cpu.iew.wb_producers 230213925 # num instructions producing a value +system.cpu.iew.wb_consumers 333861001 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.463676 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689089 # average fanout of values written-back +system.cpu.iew.wb_rate 2.469732 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.689550 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 47420049 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 44209684 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 798401 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117693042 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.363712 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.086908 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 742009 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117119203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.375293 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.092758 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 53351319 45.33% 45.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15952359 13.55% 58.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10962553 9.31% 68.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8763534 7.45% 75.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1923790 1.63% 77.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1729278 1.47% 78.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 853123 0.72% 79.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 692579 0.59% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23464507 19.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 52926109 45.19% 45.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15815586 13.50% 58.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10978620 9.37% 68.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8749339 7.47% 75.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1860123 1.59% 77.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1720770 1.47% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 865930 0.74% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 690109 0.59% 79.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23512617 20.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117693042 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117119203 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -556,330 +558,334 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23464507 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 419841048 # The number of ROB reads -system.cpu.rob.rob_writes 657686557 # The number of ROB writes -system.cpu.timesIdled 566 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 62483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23512617 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 416008734 # The number of ROB reads +system.cpu.rob.rob_writes 650833809 # The number of ROB writes +system.cpu.timesIdled 568 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64821 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.786183 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.786183 # CPI: Total CPI of All Threads -system.cpu.ipc 1.271968 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.271968 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 493729388 # number of integer regfile reads -system.cpu.int_regfile_writes 240917610 # number of integer regfile writes -system.cpu.fp_regfile_reads 146 # number of floating regfile reads -system.cpu.fp_regfile_writes 96 # number of floating regfile writes -system.cpu.cc_regfile_reads 107705980 # number of cc regfile reads -system.cpu.cc_regfile_writes 64576396 # number of cc regfile writes -system.cpu.misc_regfile_reads 196329384 # number of misc regfile reads +system.cpu.cpi 0.779834 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.779834 # CPI: Total CPI of All Threads +system.cpu.ipc 1.282325 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.282325 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 491477122 # number of integer regfile reads +system.cpu.int_regfile_writes 239432261 # number of integer regfile writes +system.cpu.fp_regfile_reads 110 # number of floating regfile reads +system.cpu.fp_regfile_writes 84 # number of floating regfile writes +system.cpu.cc_regfile_reads 107533023 # number of cc regfile reads +system.cpu.cc_regfile_writes 64416979 # number of cc regfile writes +system.cpu.misc_regfile_reads 195275944 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072430 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.090496 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68424035 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076526 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.951206 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19739908500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.090496 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993186 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993186 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072313 # number of replacements +system.cpu.dcache.tags.tagsinuse 4068.012942 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68071048 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076409 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.783063 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19455459500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4068.012942 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993167 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993167 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 595 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3373 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 630 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3339 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 144493228 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 144493228 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37078222 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37078222 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345813 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345813 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68424035 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68424035 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68424035 # number of overall hits -system.cpu.dcache.overall_hits::total 68424035 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2690377 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2690377 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93939 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93939 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2784316 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2784316 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2784316 # number of overall misses -system.cpu.dcache.overall_misses::total 2784316 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32316565000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32316565000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2955969494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2955969494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35272534494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35272534494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35272534494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35272534494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39768599 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39768599 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 143788667 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 143788667 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 36725223 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 36725223 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345824 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345824 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68071047 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2956618494 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2956618494 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35261040494 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35261040494 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35261040494 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35261040494 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39416377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39416377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 71208351 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 71208351 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 71208351 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 71208351 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067651 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067651 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 70856129 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 70856129 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 70856129 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 70856129 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068275 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.068275 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002988 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.002988 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.039101 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.039101 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039101 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039101 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12011.909483 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12011.909483 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31466.903991 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31466.903991 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12668.294293 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12668.294293 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12668.294293 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 221313 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.039306 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039306 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039306 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039306 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12003.929169 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12003.929169 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31477.498659 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31477.498659 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12660.683059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12660.683059 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12660.683059 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 221512 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43094 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43222 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.135587 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.124983 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066711 # number of writebacks -system.cpu.dcache.writebacks::total 2066711 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 695911 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 695911 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11877 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11877 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 707788 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 707788 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 707788 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 707788 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994466 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994466 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82062 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24203306500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24203306500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2798613994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2798613994 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27001920494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27001920494 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27001920494 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27001920494 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050152 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050152 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066601 # number of writebacks +system.cpu.dcache.writebacks::total 2066601 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 696788 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 696788 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11884 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11884 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 708672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 708672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 708672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 708672 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994366 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994366 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076410 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076410 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076410 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076410 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24196094000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24196094000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2799396995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2799396995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26995490995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26995490995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26995490995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26995490995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050597 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050597 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002610 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002610 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12135.231435 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12135.231435 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34103.653262 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34103.653262 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13003.398218 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13003.398218 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029305 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029305 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029305 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12132.223474 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12132.223474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34120.679087 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34120.679087 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13001.040736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13001.040736 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 64 # number of replacements -system.cpu.icache.tags.tagsinuse 833.320748 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27853507 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1032 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26989.832364 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 53 # number of replacements +system.cpu.icache.tags.tagsinuse 825.040012 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27442569 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1013 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 27090.393880 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 833.320748 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.406895 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.406895 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 968 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.472656 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55710776 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55710776 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27853507 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27853507 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27853507 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27853507 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 98783500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27854872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27854872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27854872 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27854872 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27854872 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27854872 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000049 # 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Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.402852 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 870 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 54888798 # Number of tag accesses +system.cpu.icache.tags.data_accesses 54888798 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27442569 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27442569 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27442569 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27442569 # 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number of cycles access was blocked @@ -890,116 +896,118 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 184 # number of writebacks system.cpu.l2cache.writebacks::total 184 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1013 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1013 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 437 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 437 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856763500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1922503500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353213 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353213 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.981589 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.981589 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000219 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000219 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.984221 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000214 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014644 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984221 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014171 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014644 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63044.847921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63044.847921 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.743487 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.743487 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67110.328638 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67110.328638 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.743487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63103.707858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63194.513839 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 1995466 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6085 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82092 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82092 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994436 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2128 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225475 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6227603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265167168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265233216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 495 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4150549 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.000119 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010920 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066785 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6227173 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265217536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 487 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4150277 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.000117 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.010832 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4150054 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 495 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4149790 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 487 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4150549 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4141738000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4150277 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4141496000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1548000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1521000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3114789000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1448 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 3114614000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 5.1 # Layer utilization (%) +system.membus.trans_dist::ReadResp 1424 # Transaction distribution system.membus.trans_dist::Writeback 184 # Transaction distribution -system.membus.trans_dist::CleanEvict 34 # Transaction distribution -system.membus.trans_dist::ReadExReq 28996 # Transaction distribution -system.membus.trans_dist::ReadExResp 28996 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1450 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61108 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61108 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1960192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1960192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1960192 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 30 # Transaction distribution +system.membus.trans_dist::ReadExReq 28998 # Transaction distribution +system.membus.trans_dist::ReadExResp 28998 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1424 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61058 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61058 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1958784 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30664 # Request fanout histogram +system.membus.snoop_fanout::samples 30636 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30636 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30664 # Request fanout histogram -system.membus.reqLayer0.occupancy 42854000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30636 # Request fanout histogram +system.membus.reqLayer0.occupancy 42746500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 160427250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 160323750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index fecf9a5e9..f0cb43f99 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -84,7 +84,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -134,7 +134,7 @@ system=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -200,7 +200,7 @@ system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 42e3e20b3..dc48bfe97 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,13 @@ +Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 20:18:36 -gem5 executing on u200540-lin -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing +gem5 compiled Sep 14 2015 22:13:36 +gem5 started Sep 14 2015 23:02:52 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +26,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 365989065000 because target called exit() +Exiting @ tick 365988859500 because target called exit() diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini index 9aa92cf18..9e17532ff 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini @@ -125,7 +125,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -548,7 +548,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -597,7 +597,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr index 354ea5068..f0a9a7c93 100644..100755 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr @@ -1,10 +1,6 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway -warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway -warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway -warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway -warn: system.cpu.execute.inFlightInsts: No space to push data into queue of capacity 26, pushing anyway warn: ignoring syscall sigprocmask(1, ...) diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout index 6e5c2e80e..f3df2a37b 100644..100755 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout @@ -3,10 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:41:53 -gem5 started May 7 2014 16:13:15 -gem5 executing on cz3212c2d7 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 21:15:04 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -68,4 +69,4 @@ Echoing of input sentence turned on. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 409513954500 because target called exit() +Exiting @ tick 412080064500 because target called exit() diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 721b096f0..0819be4e4 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.412968 # Number of seconds simulated -sim_ticks 412968287500 # Number of ticks simulated -final_tick 412968287500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.412080 # Number of seconds simulated +sim_ticks 412080064500 # Number of ticks simulated +final_tick 412080064500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 309752 # Simulator instruction rate (inst/s) -host_op_rate 309752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 209049423 # Simulator tick rate (ticks/s) -host_mem_usage 299216 # Number of bytes of host memory used -host_seconds 1975.46 # Real time elapsed on the host +host_inst_rate 229857 # Simulator instruction rate (inst/s) +host_op_rate 229857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154795079 # Simulator tick rate (ticks/s) +host_mem_usage 293864 # Number of bytes of host memory used +host_seconds 2662.10 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24125568 # Number of bytes read from this memory -system.physmem.bytes_read::total 24296576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 170880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24123968 # Number of bytes read from this memory +system.physmem.bytes_read::total 24294848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 18781376 # Number of bytes written to this memory system.physmem.bytes_written::total 18781376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 376962 # Number of read requests responded to by this memory -system.physmem.num_reads::total 379634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 376937 # Number of read requests responded to by this memory +system.physmem.num_reads::total 379607 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 293459 # Number of write requests responded to by this memory system.physmem.num_writes::total 293459 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 414095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58419905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 58833999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 414095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 414095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45478979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45478979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45478979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 414095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58419905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104312978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 379634 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 414677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58541944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58956621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 414677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 414677 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45577007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45577007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45577007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 414677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58541944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104533628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 379607 # Number of read requests accepted system.physmem.writeReqs 293459 # Number of write requests accepted -system.physmem.readBursts 379634 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 379607 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 293459 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24275200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21376 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 24271744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 23104 # Total number of bytes read from write queue system.physmem.bytesWritten 18779968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24296576 # Total read bytes from the system interface side +system.physmem.bytesReadSys 24294848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 18781376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 334 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 361 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23720 # Per bank write bursts -system.physmem.perBankRdBursts::1 23189 # Per bank write bursts -system.physmem.perBankRdBursts::2 23443 # Per bank write bursts -system.physmem.perBankRdBursts::3 24493 # Per bank write bursts -system.physmem.perBankRdBursts::4 25427 # Per bank write bursts -system.physmem.perBankRdBursts::5 23582 # Per bank write bursts -system.physmem.perBankRdBursts::6 23638 # Per bank write bursts -system.physmem.perBankRdBursts::7 23957 # Per bank write bursts -system.physmem.perBankRdBursts::8 23144 # Per bank write bursts -system.physmem.perBankRdBursts::9 23961 # Per bank write bursts -system.physmem.perBankRdBursts::10 24713 # Per bank write bursts -system.physmem.perBankRdBursts::11 22767 # Per bank write bursts -system.physmem.perBankRdBursts::12 23721 # Per bank write bursts -system.physmem.perBankRdBursts::13 24378 # Per bank write bursts -system.physmem.perBankRdBursts::14 22727 # Per bank write bursts +system.physmem.perBankRdBursts::0 23711 # Per bank write bursts +system.physmem.perBankRdBursts::1 23184 # Per bank write bursts +system.physmem.perBankRdBursts::2 23442 # Per bank write bursts +system.physmem.perBankRdBursts::3 24496 # Per bank write bursts +system.physmem.perBankRdBursts::4 25435 # Per bank write bursts +system.physmem.perBankRdBursts::5 23571 # Per bank write bursts +system.physmem.perBankRdBursts::6 23637 # Per bank write bursts +system.physmem.perBankRdBursts::7 23952 # Per bank write bursts +system.physmem.perBankRdBursts::8 23149 # Per bank write bursts +system.physmem.perBankRdBursts::9 23951 # Per bank write bursts +system.physmem.perBankRdBursts::10 24706 # Per bank write bursts +system.physmem.perBankRdBursts::11 22760 # Per bank write bursts +system.physmem.perBankRdBursts::12 23713 # Per bank write bursts +system.physmem.perBankRdBursts::13 24379 # Per bank write bursts +system.physmem.perBankRdBursts::14 22720 # Per bank write bursts system.physmem.perBankRdBursts::15 22440 # Per bank write bursts -system.physmem.perBankWrBursts::0 17784 # Per bank write bursts -system.physmem.perBankWrBursts::1 17460 # Per bank write bursts -system.physmem.perBankWrBursts::2 17942 # Per bank write bursts -system.physmem.perBankWrBursts::3 18842 # Per bank write bursts -system.physmem.perBankWrBursts::4 19508 # Per bank write bursts -system.physmem.perBankWrBursts::5 18590 # Per bank write bursts -system.physmem.perBankWrBursts::6 18730 # Per bank write bursts -system.physmem.perBankWrBursts::7 18662 # Per bank write bursts -system.physmem.perBankWrBursts::8 18408 # Per bank write bursts -system.physmem.perBankWrBursts::9 18932 # Per bank write bursts -system.physmem.perBankWrBursts::10 19251 # Per bank write bursts -system.physmem.perBankWrBursts::11 18034 # Per bank write bursts +system.physmem.perBankWrBursts::0 17781 # Per bank write bursts +system.physmem.perBankWrBursts::1 17456 # Per bank write bursts +system.physmem.perBankWrBursts::2 17945 # Per bank write bursts +system.physmem.perBankWrBursts::3 18847 # Per bank write bursts +system.physmem.perBankWrBursts::4 19513 # Per bank write bursts +system.physmem.perBankWrBursts::5 18587 # Per bank write bursts +system.physmem.perBankWrBursts::6 18727 # Per bank write bursts +system.physmem.perBankWrBursts::7 18653 # Per bank write bursts +system.physmem.perBankWrBursts::8 18413 # Per bank write bursts +system.physmem.perBankWrBursts::9 18933 # Per bank write bursts +system.physmem.perBankWrBursts::10 19255 # Per bank write bursts +system.physmem.perBankWrBursts::11 18037 # Per bank write bursts system.physmem.perBankWrBursts::12 18264 # Per bank write bursts -system.physmem.perBankWrBursts::13 18730 # Per bank write bursts -system.physmem.perBankWrBursts::14 17177 # Per bank write bursts -system.physmem.perBankWrBursts::15 17123 # Per bank write bursts +system.physmem.perBankWrBursts::13 18729 # Per bank write bursts +system.physmem.perBankWrBursts::14 17175 # Per bank write bursts +system.physmem.perBankWrBursts::15 17122 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 412968199500 # Total gap between requests +system.physmem.totGap 412079976500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 379634 # Read request sizes (log2) +system.physmem.readPktSize::6 379607 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 293459 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 377911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 377839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -193,125 +193,129 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.814019 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.682339 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.904056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50781 35.72% 35.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38739 27.25% 62.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13305 9.36% 72.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8117 5.71% 78.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5703 4.01% 82.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3753 2.64% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3029 2.13% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2502 1.76% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16252 11.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142181 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17324 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.893847 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 236.830288 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17315 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.629870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.695929 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.359961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50814 35.72% 35.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38804 27.28% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13098 9.21% 72.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8314 5.84% 78.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5760 4.05% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3818 2.68% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2956 2.08% 86.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2613 1.84% 88.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16081 11.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142258 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17331 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.881888 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 237.076982 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17323 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17324 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17324 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.938178 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.866265 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.087562 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 17274 99.71% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 36 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 4 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 3 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::328-335 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17324 # Writes before turning the bus around for reads -system.physmem.totQLat 4037980750 # Total ticks spent queuing -system.physmem.totMemAccLat 11149855750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1896500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10645.88 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17331 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17331 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.931337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.860812 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.636907 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17131 98.85% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 149 0.86% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 30 0.17% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 5 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 5 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17331 # Writes before turning the bus around for reads +system.physmem.totQLat 4068932250 # Total ticks spent queuing +system.physmem.totMemAccLat 11179794750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1896230000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10729.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29395.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 58.78 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.48 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 58.83 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.48 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29479.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.81 # Data bus utilization in percentage +system.physmem.busUtil 0.82 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.84 # Average write queue length when enqueuing -system.physmem.readRowHits 314187 # Number of row buffer hits during reads -system.physmem.writeRowHits 216366 # Number of row buffer hits during writes +system.physmem.avgWrQLen 20.54 # Average write queue length when enqueuing +system.physmem.readRowHits 314133 # Number of row buffer hits during reads +system.physmem.writeRowHits 216290 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.73 # Row buffer hit rate for writes -system.physmem.avgGap 613538.10 # Average gap between requests -system.physmem.pageHitRate 78.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 547268400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 298608750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1493302200 # Energy for read commands per rank (pJ) +system.physmem.writeRowHitRate 73.70 # Row buffer hit rate for writes +system.physmem.avgGap 612243.04 # Average gap between requests +system.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 548364600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 299206875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1493138400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 955858320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26973005280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62129952405 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 193280474250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 285678469605 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.770048 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 320991140250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13789880000 # Time in different power states +system.physmem_0.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62103866355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 192770777250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 285086241240 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.822973 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 320142846250 # Time in different power states +system.physmem_0.memoryStateTime::REF 13760240000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78186381000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78176682500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 527582160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 287867250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1465152000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 945535680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26973005280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 59078125665 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 195957550500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 285234818535 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.695650 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 325462585000 # Time in different power states -system.physmem_1.memoryStateTime::REF 13789880000 # Time in different power states +system.physmem_1.actEnergy 527105880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 287607375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1464957000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 945613440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26915029440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59197387905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 195320319750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 284658020790 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.783804 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 324404039000 # Time in different power states +system.physmem_1.memoryStateTime::REF 13760240000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 73715009750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 73915489750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 124207922 # Number of BP lookups -system.cpu.branchPred.condPredicted 87898525 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6402854 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71417252 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67405039 # Number of BTB hits +system.cpu.branchPred.lookups 123917174 # Number of BP lookups +system.cpu.branchPred.condPredicted 87658941 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6214604 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71577859 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67272092 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.382012 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15056477 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126637 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.984499 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15041850 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126019 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149440392 # DTB read hits -system.cpu.dtb.read_misses 563754 # DTB read misses +system.cpu.dtb.read_hits 149344667 # DTB read hits +system.cpu.dtb.read_misses 549014 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 150004146 # DTB read accesses -system.cpu.dtb.write_hits 57327101 # DTB write hits -system.cpu.dtb.write_misses 66835 # DTB write misses +system.cpu.dtb.read_accesses 149893681 # DTB read accesses +system.cpu.dtb.write_hits 57319597 # DTB write hits +system.cpu.dtb.write_misses 63704 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57393936 # DTB write accesses -system.cpu.dtb.data_hits 206767493 # DTB hits -system.cpu.dtb.data_misses 630589 # DTB misses +system.cpu.dtb.write_accesses 57383301 # DTB write accesses +system.cpu.dtb.data_hits 206664264 # DTB hits +system.cpu.dtb.data_misses 612718 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207398082 # DTB accesses -system.cpu.itb.fetch_hits 226564860 # ITB hits +system.cpu.dtb.data_accesses 207276982 # DTB accesses +system.cpu.itb.fetch_hits 226051197 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226564908 # ITB accesses +system.cpu.itb.fetch_accesses 226051245 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -325,82 +329,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 825936575 # number of cpu cycles simulated +system.cpu.numCycles 824160129 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13262650 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12834592 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.349787 # CPI: cycles per instruction -system.cpu.ipc 0.740858 # IPC: instructions per cycle -system.cpu.tickCycles 740975160 # Number of cycles that the object actually ticked -system.cpu.idleCycles 84961415 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535462 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.659006 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202664910 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539558 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.803222 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1636438500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.659006 # Average occupied blocks per requestor +system.cpu.cpi 1.346883 # CPI: cycles per instruction +system.cpu.ipc 0.742455 # IPC: instructions per cycle +system.cpu.tickCycles 739333640 # Number of cycles that the object actually ticked +system.cpu.idleCycles 84826489 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535265 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.660702 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202570424 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539361 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.772204 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1635033500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.660702 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414773666 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414773666 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146998717 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146998717 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666193 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666193 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202664910 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202664910 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202664910 # number of overall hits -system.cpu.dcache.overall_hits::total 202664910 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1908303 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908303 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543841 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543841 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3452144 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452144 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3452144 # number of overall misses -system.cpu.dcache.overall_misses::total 3452144 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37694000500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37694000500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 47697864000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 47697864000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 85391864500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 85391864500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 85391864500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 85391864500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148907020 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148907020 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414584973 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414584973 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146904267 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146904267 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666157 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666157 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 202570424 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202570424 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202570424 # number of overall hits +system.cpu.dcache.overall_hits::total 202570424 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1908505 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908505 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543877 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543877 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3452382 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452382 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3452382 # number of overall misses +system.cpu.dcache.overall_misses::total 3452382 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37715152000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37715152000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 47725761500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 47725761500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85440913500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85440913500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85440913500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85440913500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148812772 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148812772 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206117054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206117054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206117054 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206117054 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012815 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012815 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016748 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016748 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016748 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016748 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19752.628644 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19752.628644 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30895.580568 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30895.580568 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24735.892970 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24735.892970 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24735.892970 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24735.892970 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 206022806 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206022806 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206022806 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206022806 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012825 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012825 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026986 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.026986 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016757 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016757 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016757 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016757 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19761.620745 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19761.620745 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30912.929916 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30912.929916 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24748.395021 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24748.395021 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24748.395021 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24748.395021 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,103 +413,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2339794 # number of writebacks -system.cpu.dcache.writebacks::total 2339794 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143529 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143529 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769057 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769057 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 912586 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912586 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 912586 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912586 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764774 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764774 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774784 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774784 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539558 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539558 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539558 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539558 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33188844000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33188844000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23330038500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 23330038500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56518882500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56518882500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56518882500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56518882500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011852 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011852 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2339622 # number of writebacks +system.cpu.dcache.writebacks::total 2339622 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143967 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143967 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769054 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769054 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 913021 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 913021 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 913021 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 913021 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764538 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764538 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774823 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774823 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539361 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539361 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539361 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539361 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33198964500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 33198964500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23344010000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23344010000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56542974500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 56542974500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56542974500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 56542974500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011857 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011857 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012321 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012321 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012321 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012321 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18806.285677 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18806.285677 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30111.667897 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30111.667897 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22255.401334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22255.401334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22255.401334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22255.401334 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012326 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012326 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012326 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18814.536440 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18814.536440 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30128.184114 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30128.184114 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22266.615302 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22266.615302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22266.615302 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22266.615302 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3160 # number of replacements -system.cpu.icache.tags.tagsinuse 1117.196292 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226559871 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4989 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45411.880337 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3153 # number of replacements +system.cpu.icache.tags.tagsinuse 1116.819230 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226046216 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4981 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45381.693636 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.196292 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545506 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545506 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 76 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 453134709 # Number of tag accesses -system.cpu.icache.tags.data_accesses 453134709 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226559871 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226559871 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226559871 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226559871 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 226559871 # number of overall hits -system.cpu.icache.overall_hits::total 226559871 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4989 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4989 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26221285500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26403324000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265073 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265073 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.535578 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.535578 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.096910 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.096910 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68179.213483 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69564.106203 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69554.365436 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 1766410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2633253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 252293 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778137 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778137 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4989 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761421 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614578 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7627716 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312278528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312597824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 346924 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5430093 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1766182 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2633081 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 252234 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778160 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778160 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761201 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7613987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7627102 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 318784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312254912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312573696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 346897 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5429657 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.063889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.244555 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.244556 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5083169 93.61% 93.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 346924 6.39% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5082760 93.61% 93.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 346897 6.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5430093 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4881378500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5429657 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4881002000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7483500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7471500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3809337000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3809041500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 173371 # Transaction distribution +system.membus.trans_dist::ReadResp 173346 # Transaction distribution system.membus.trans_dist::Writeback 293459 # Transaction distribution -system.membus.trans_dist::CleanEvict 51814 # Transaction distribution -system.membus.trans_dist::ReadExReq 206263 # Transaction distribution -system.membus.trans_dist::ReadExResp 206263 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 173371 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1104541 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43077952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43077952 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 51785 # Transaction distribution +system.membus.trans_dist::ReadExReq 206261 # Transaction distribution +system.membus.trans_dist::ReadExResp 206261 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 173346 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1104458 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1104458 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43076224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43076224 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 724907 # Request fanout histogram +system.membus.snoop_fanout::samples 724851 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 724907 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 724851 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 724907 # Request fanout histogram -system.membus.reqLayer0.occupancy 2020096000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 724851 # Request fanout histogram +system.membus.reqLayer0.occupancy 2020156500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2009057000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2008875000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini index 482664dec..a401ada34 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -759,9 +759,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout index 83790a04a..984c172ad 100755 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 03:04:52 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x3275620 info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: ************************************************* @@ -68,4 +70,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 366358475500 because target called exit() +Exiting @ tick 363605295500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 9049068c3..0b95ee278 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365934 # Number of seconds simulated -sim_ticks 365934171500 # Number of ticks simulated -final_tick 365934171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.363605 # Number of seconds simulated +sim_ticks 363605295500 # Number of ticks simulated +final_tick 363605295500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236242 # Simulator instruction rate (inst/s) -host_op_rate 255881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 170651382 # Simulator tick rate (ticks/s) -host_mem_usage 317968 # Number of bytes of host memory used -host_seconds 2144.34 # Real time elapsed on the host +host_inst_rate 163495 # Simulator instruction rate (inst/s) +host_op_rate 177087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 117350463 # Simulator tick rate (ticks/s) +host_mem_usage 312624 # Number of bytes of host memory used +host_seconds 3098.46 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 218560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8996480 # Number of bytes read from this memory -system.physmem.bytes_read::total 9215040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6186432 # Number of bytes written to this memory -system.physmem.bytes_written::total 6186432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3415 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140570 # Number of read requests responded to by this memory -system.physmem.num_reads::total 143985 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96663 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96663 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 597266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24584968 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25182234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 597266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16905860 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16905860 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16905860 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 597266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24584968 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42088095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 143985 # Number of read requests accepted -system.physmem.writeReqs 96663 # Number of write requests accepted -system.physmem.readBursts 143985 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96663 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9208192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 6184704 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9215040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6186432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 219264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9004480 # Number of bytes read from this memory +system.physmem.bytes_read::total 9223744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6189056 # Number of bytes written to this memory +system.physmem.bytes_written::total 6189056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140695 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144121 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96704 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96704 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 603028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24764436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25367463 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 603028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 603028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 17021358 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 17021358 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 17021358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 603028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24764436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42388822 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144121 # Number of read requests accepted +system.physmem.writeReqs 96704 # Number of write requests accepted +system.physmem.readBursts 144121 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96704 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9217792 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue +system.physmem.bytesWritten 6187328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9223744 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6189056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9335 # Per bank write bursts -system.physmem.perBankRdBursts::1 8992 # Per bank write bursts -system.physmem.perBankRdBursts::2 8932 # Per bank write bursts -system.physmem.perBankRdBursts::3 8655 # Per bank write bursts +system.physmem.perBankRdBursts::0 9327 # Per bank write bursts +system.physmem.perBankRdBursts::1 8969 # Per bank write bursts +system.physmem.perBankRdBursts::2 9002 # Per bank write bursts +system.physmem.perBankRdBursts::3 8675 # Per bank write bursts system.physmem.perBankRdBursts::4 9455 # Per bank write bursts -system.physmem.perBankRdBursts::5 9355 # Per bank write bursts -system.physmem.perBankRdBursts::6 8940 # Per bank write bursts -system.physmem.perBankRdBursts::7 8097 # Per bank write bursts -system.physmem.perBankRdBursts::8 8569 # Per bank write bursts -system.physmem.perBankRdBursts::9 8673 # Per bank write bursts -system.physmem.perBankRdBursts::10 8766 # Per bank write bursts -system.physmem.perBankRdBursts::11 9474 # Per bank write bursts -system.physmem.perBankRdBursts::12 9347 # Per bank write bursts -system.physmem.perBankRdBursts::13 9510 # Per bank write bursts -system.physmem.perBankRdBursts::14 8717 # Per bank write bursts -system.physmem.perBankRdBursts::15 9061 # Per bank write bursts -system.physmem.perBankWrBursts::0 6192 # Per bank write bursts -system.physmem.perBankWrBursts::1 6097 # Per bank write bursts -system.physmem.perBankWrBursts::2 6005 # Per bank write bursts -system.physmem.perBankWrBursts::3 5812 # Per bank write bursts -system.physmem.perBankWrBursts::4 6185 # Per bank write bursts -system.physmem.perBankWrBursts::5 6187 # Per bank write bursts -system.physmem.perBankWrBursts::6 6017 # Per bank write bursts -system.physmem.perBankWrBursts::7 5496 # Per bank write bursts -system.physmem.perBankWrBursts::8 5731 # Per bank write bursts +system.physmem.perBankRdBursts::5 9352 # Per bank write bursts +system.physmem.perBankRdBursts::6 8946 # Per bank write bursts +system.physmem.perBankRdBursts::7 8102 # Per bank write bursts +system.physmem.perBankRdBursts::8 8582 # Per bank write bursts +system.physmem.perBankRdBursts::9 8671 # Per bank write bursts +system.physmem.perBankRdBursts::10 8765 # Per bank write bursts +system.physmem.perBankRdBursts::11 9475 # Per bank write bursts +system.physmem.perBankRdBursts::12 9349 # Per bank write bursts +system.physmem.perBankRdBursts::13 9515 # Per bank write bursts +system.physmem.perBankRdBursts::14 8723 # Per bank write bursts +system.physmem.perBankRdBursts::15 9120 # Per bank write bursts +system.physmem.perBankWrBursts::0 6189 # Per bank write bursts +system.physmem.perBankWrBursts::1 6094 # Per bank write bursts +system.physmem.perBankWrBursts::2 6010 # Per bank write bursts +system.physmem.perBankWrBursts::3 5821 # Per bank write bursts +system.physmem.perBankWrBursts::4 6183 # Per bank write bursts +system.physmem.perBankWrBursts::5 6186 # Per bank write bursts +system.physmem.perBankWrBursts::6 6015 # Per bank write bursts +system.physmem.perBankWrBursts::7 5498 # Per bank write bursts +system.physmem.perBankWrBursts::8 5738 # Per bank write bursts system.physmem.perBankWrBursts::9 5829 # Per bank write bursts system.physmem.perBankWrBursts::10 5965 # Per bank write bursts -system.physmem.perBankWrBursts::11 6464 # Per bank write bursts +system.physmem.perBankWrBursts::11 6463 # Per bank write bursts system.physmem.perBankWrBursts::12 6313 # Per bank write bursts -system.physmem.perBankWrBursts::13 6284 # Per bank write bursts -system.physmem.perBankWrBursts::14 6001 # Per bank write bursts -system.physmem.perBankWrBursts::15 6058 # Per bank write bursts +system.physmem.perBankWrBursts::13 6285 # Per bank write bursts +system.physmem.perBankWrBursts::14 6005 # Per bank write bursts +system.physmem.perBankWrBursts::15 6083 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 365934145500 # Total gap between requests +system.physmem.totGap 363605269500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 143985 # Read request sizes (log2) +system.physmem.readPktSize::6 144121 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96663 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96704 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143663 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,41 +144,41 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3097 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see @@ -193,107 +193,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.897316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.545884 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.443874 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24707 37.87% 37.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18339 28.11% 65.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7015 10.75% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7835 12.01% 88.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2110 3.23% 91.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1145 1.75% 93.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 725 1.11% 94.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 601 0.92% 95.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2772 4.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65249 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.778176 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 381.924168 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5576 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 4 0.07% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65251 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.074482 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.620272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.651300 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24697 37.85% 37.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18374 28.16% 66.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6917 10.60% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7938 12.17% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2038 3.12% 91.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1147 1.76% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 769 1.18% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 621 0.95% 95.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2750 4.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65251 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5585 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.786571 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 381.841879 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5581 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 3 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5581 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5581 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.315176 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.217549 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.442698 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2634 47.20% 47.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2799 50.15% 97.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 58 1.04% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 19 0.34% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 10 0.18% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 9 0.16% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 9 0.16% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 3 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 4 0.07% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 4 0.07% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-73 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::74-75 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-93 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5581 # Writes before turning the bus around for reads -system.physmem.totQLat 1559327000 # Total ticks spent queuing -system.physmem.totMemAccLat 4257039500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 719390000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10837.84 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5585 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5585 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.310116 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.217866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.213646 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2534 45.37% 45.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 92 1.65% 47.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2660 47.63% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 156 2.79% 97.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 36 0.64% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 18 0.32% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 16 0.29% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 9 0.16% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 7 0.13% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 10 0.18% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.07% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.07% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.07% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.11% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.07% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 4 0.07% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 2 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::53 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::61 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5585 # Writes before turning the bus around for reads +system.physmem.totQLat 1541292750 # Total ticks spent queuing +system.physmem.totMemAccLat 4241817750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10701.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29587.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.91 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29451.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.35 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.48 # Average write queue length when enqueuing -system.physmem.readRowHits 110804 # Number of row buffer hits during reads -system.physmem.writeRowHits 64456 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.68 # Row buffer hit rate for writes -system.physmem.avgGap 1520619.93 # Average gap between requests -system.physmem.pageHitRate 72.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 248300640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135481500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 559572000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310819680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47511748935 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177881418000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250548135075 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.687479 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295615195000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12219220000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 19.51 # Average write queue length when enqueuing +system.physmem.readRowHits 110876 # Number of row buffer hits during reads +system.physmem.writeRowHits 64571 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.77 # Row buffer hit rate for writes +system.physmem.avgGap 1509831.91 # Average gap between requests +system.physmem.pageHitRate 72.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248028480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135333000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560164800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310884480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47382783300 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 176597692500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 248983621440 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.768610 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 293478926000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12141480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 58096250000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 57982170250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244785240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133563375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 562356600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315174240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23900794320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46698412230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178594871250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250449957255 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.419183 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296806540250 # Time in different power states -system.physmem_1.memoryStateTime::REF 12219220000 # Time in different power states +system.physmem_1.actEnergy 245080080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133724250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 563004000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315375120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23748734880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46983341835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 176948079750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 248937339915 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.641324 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 294063578500 # Time in different power states +system.physmem_1.memoryStateTime::REF 12141480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 56906569250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57397836750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132492243 # Number of BP lookups -system.cpu.branchPred.condPredicted 98438822 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6555205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68897926 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64816869 # Number of BTB hits +system.cpu.branchPred.lookups 131896308 # Number of BP lookups +system.cpu.branchPred.condPredicted 98031712 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6139352 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68410049 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64397752 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.076662 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10008233 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17907 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.134930 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9981293 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 18014 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,98 +427,98 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 731868343 # number of cpu cycles simulated +system.cpu.numCycles 727210591 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582156 # Number of instructions committed system.cpu.committedOps 548695379 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13915585 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13199856 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.444718 # CPI: cycles per instruction -system.cpu.ipc 0.692177 # IPC: instructions per cycle -system.cpu.tickCycles 695013398 # Number of cycles that the object actually ticked -system.cpu.idleCycles 36854945 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139741 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.950270 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171285752 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143837 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.746644 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4896340500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.950270 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993884 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993884 # Average percentage of cache occupancy +system.cpu.cpi 1.435524 # CPI: cycles per instruction +system.cpu.ipc 0.696610 # IPC: instructions per cycle +system.cpu.tickCycles 690727435 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36483156 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139971 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.789837 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171168979 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1144067 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.614471 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.789837 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993845 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3503 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3500 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346825855 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346825855 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114767186 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114767186 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538711 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538711 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2773 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2773 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346593001 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346593001 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114650515 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114650515 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538628 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2754 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2754 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168305897 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168305897 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168308670 # number of overall hits -system.cpu.dcache.overall_hits::total 168308670 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854648 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854648 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700595 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700595 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 14 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 14 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1555243 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555243 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555257 # number of overall misses -system.cpu.dcache.overall_misses::total 1555257 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14022869000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14022869000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21909880500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21909880500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35932749500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35932749500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35932749500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35932749500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115621834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115621834 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168189143 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168189143 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168191897 # number of overall hits +system.cpu.dcache.overall_hits::total 168191897 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854793 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854793 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700678 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 17 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 17 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1555471 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555471 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555488 # number of overall misses +system.cpu.dcache.overall_misses::total 1555488 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024452000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14024452000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21892214000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21892214000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35916666000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35916666000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35916666000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35916666000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115505308 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115505308 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2787 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2787 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2771 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2771 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169861140 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169861140 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169863927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169863927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007392 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.007392 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012917 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005023 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005023 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009156 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009156 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009156 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009156 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16407.771387 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16407.771387 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31273.247026 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31273.247026 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23104.266986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23104.266986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23104.059008 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23104.059008 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 169744614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169744614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169747385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169747385 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007400 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.007400 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012918 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.012918 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.006135 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.006135 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009164 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009164 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009164 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009164 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.840019 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.840019 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31244.329064 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31244.329064 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23090.540422 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23090.540422 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23090.288064 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23090.288064 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,111 +527,111 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068492 # number of writebacks -system.cpu.dcache.writebacks::total 1068492 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66944 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66944 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344474 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344474 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1068574 # number of writebacks +system.cpu.dcache.writebacks::total 1068574 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66907 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66907 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344511 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344511 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 411418 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 411418 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 411418 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 411418 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787704 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787704 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356121 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356121 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1143825 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143825 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1143837 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143837 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12336256500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12336256500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11129164500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11129164500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1374500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1374500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23465421000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23465421000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23466795500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23466795500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004306 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004306 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15661.030666 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15661.030666 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31251.076179 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31251.076179 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 114541.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 114541.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20514.869845 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20514.869845 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20515.856280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20515.856280 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787886 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787886 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356167 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356167 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 14 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 14 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1144053 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1144053 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1144067 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1144067 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12337562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12337562000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11120015500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11120015500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1028000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1028000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23457577500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23457577500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23458605500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23458605500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006821 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006821 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006567 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005052 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005052 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006740 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006740 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006740 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15659.069967 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15659.069967 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31221.352624 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31221.352624 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73428.571429 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73428.571429 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20503.925517 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20503.925517 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20504.573159 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20504.573159 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17695 # number of replacements -system.cpu.icache.tags.tagsinuse 1189.845505 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200793682 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19567 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10261.853222 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17719 # number of replacements +system.cpu.icache.tags.tagsinuse 1188.326281 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199317838 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19591 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10173.949160 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1189.845505 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.580979 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.580979 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1188.326281 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.580237 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.580237 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1411 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1407 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 401646065 # Number of tag accesses -system.cpu.icache.tags.data_accesses 401646065 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200793682 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200793682 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200793682 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200793682 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200793682 # number of overall hits -system.cpu.icache.overall_hits::total 200793682 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19567 # 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average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69351.430239 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72393.731501 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72393.731501 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69351.430239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69528.490707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69524.281680 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 807030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1165155 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98658 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356374 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356374 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 19567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 787463 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56593 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3422797 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3479390 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142841344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 111231 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2432071 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.045735 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.208910 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 807241 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1165278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 19591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 787650 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423421 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3480085 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141609024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142862848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 111367 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2432715 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.045779 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.209005 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2320840 95.43% 95.43% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 111231 4.57% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2321348 95.42% 95.42% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 111367 4.58% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2432071 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2228912000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2432715 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2229248000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 29351498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 29387997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1715762985 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1716107486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 43172 # Transaction distribution -system.membus.trans_dist::Writeback 96663 # Transaction distribution -system.membus.trans_dist::CleanEvict 13165 # Transaction distribution -system.membus.trans_dist::ReadExReq 100813 # Transaction distribution -system.membus.trans_dist::ReadExResp 100813 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43172 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397798 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 397798 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15401472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15401472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 43292 # Transaction distribution +system.membus.trans_dist::Writeback 96704 # Transaction distribution +system.membus.trans_dist::CleanEvict 13244 # Transaction distribution +system.membus.trans_dist::ReadExReq 100829 # Transaction distribution +system.membus.trans_dist::ReadExResp 100829 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43292 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398190 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15412800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15412800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 253813 # Request fanout histogram +system.membus.snoop_fanout::samples 254069 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253813 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 254069 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253813 # Request fanout histogram -system.membus.reqLayer0.occupancy 683218000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 254069 # Request fanout histogram +system.membus.reqLayer0.occupancy 683631500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 764295250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765040250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 8909daba1..2ccb6f3ec 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -688,9 +688,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser gid=100 -input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index 0b92236c6..bc3661e7a 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -156,7 +156,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -266,7 +266,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 0db544c43..0416dfaa7 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -156,7 +156,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -513,7 +513,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -579,7 +579,7 @@ system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -642,9 +642,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser gid=100 -input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in +input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in kvmInSE=false max_stack_size=67108864 output=cout diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 67a40aa52..bfd9de2ec 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -3,17 +3,18 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 5 2015 17:24:59 -gem5 started Jul 5 2015 17:25:16 +gem5 compiled Sep 14 2015 22:13:36 +gem5 started Sep 14 2015 22:14:29 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... - Reading the dictionary files: *********info: Increasing stack size by one page. + Reading the dictionary files: **info: Increasing stack size by one page. +*******info: Increasing stack size by one page. +******************************info: Increasing stack size by one page. info: Increasing stack size by one page. -**********************************info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -24,8 +25,7 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -info: Increasing stack size by one page. -****** +********** 58924 words stored in 3784810 bytes @@ -37,6 +37,10 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success +* do you know where John 's +* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +* how fast the program is it +* I am wondering whether to invite to the party info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -45,10 +49,6 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party * I gave him for his birthday it * I thought terrible after our discussion * I wonder how much money have you earned @@ -91,4 +91,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 417250627500 because target called exit() +Exiting @ tick 403706643500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 0dda4ffb8..c2ca7f71b 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.417316 # Number of seconds simulated -sim_ticks 417315805000 # Number of ticks simulated -final_tick 417315805000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403707 # Number of seconds simulated +sim_ticks 403706643500 # Number of ticks simulated +final_tick 403706643500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92447 # Simulator instruction rate (inst/s) -host_op_rate 170945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46657066 # Simulator tick rate (ticks/s) -host_mem_usage 432180 # Number of bytes of host memory used -host_seconds 8944.32 # Real time elapsed on the host +host_inst_rate 76271 # Simulator instruction rate (inst/s) +host_op_rate 141034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37237827 # Simulator tick rate (ticks/s) +host_mem_usage 423672 # Number of bytes of host memory used +host_seconds 10841.31 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 223744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24530944 # Number of bytes read from this memory -system.physmem.bytes_read::total 24754688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 223744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 223744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18881856 # Number of bytes written to this memory -system.physmem.bytes_written::total 18881856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3496 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383296 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386792 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295029 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 536150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58782686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59318836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 536150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 536150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45245964 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45245964 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45245964 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 536150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58782686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104564801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386792 # Number of read requests accepted -system.physmem.writeReqs 295029 # Number of write requests accepted -system.physmem.readBursts 386792 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295029 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24733440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue -system.physmem.bytesWritten 18880128 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24754688 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18881856 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 216320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24497408 # Number of bytes read from this memory +system.physmem.bytes_read::total 24713728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18869312 # Number of bytes written to this memory +system.physmem.bytes_written::total 18869312 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3380 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382772 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386152 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 294833 # Number of write requests responded to by this memory +system.physmem.num_writes::total 294833 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 535835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60681211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61217046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 535835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 535835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46740157 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46740157 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46740157 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 535835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60681211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107957203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386152 # Number of read requests accepted +system.physmem.writeReqs 294833 # Number of write requests accepted +system.physmem.readBursts 386152 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 294833 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24695616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18112 # Total number of bytes read from write queue +system.physmem.bytesWritten 18867776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24713728 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18869312 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 283 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 179000 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24059 # Per bank write bursts -system.physmem.perBankRdBursts::1 26401 # Per bank write bursts -system.physmem.perBankRdBursts::2 24741 # Per bank write bursts -system.physmem.perBankRdBursts::3 24611 # Per bank write bursts -system.physmem.perBankRdBursts::4 23500 # Per bank write bursts -system.physmem.perBankRdBursts::5 23770 # Per bank write bursts -system.physmem.perBankRdBursts::6 24546 # Per bank write bursts -system.physmem.perBankRdBursts::7 24382 # Per bank write bursts -system.physmem.perBankRdBursts::8 23722 # Per bank write bursts -system.physmem.perBankRdBursts::9 23975 # Per bank write bursts -system.physmem.perBankRdBursts::10 24786 # Per bank write bursts -system.physmem.perBankRdBursts::11 24066 # Per bank write bursts -system.physmem.perBankRdBursts::12 23221 # Per bank write bursts -system.physmem.perBankRdBursts::13 22949 # Per bank write bursts -system.physmem.perBankRdBursts::14 23843 # Per bank write bursts -system.physmem.perBankRdBursts::15 23888 # Per bank write bursts -system.physmem.perBankWrBursts::0 18612 # Per bank write bursts -system.physmem.perBankWrBursts::1 19924 # Per bank write bursts -system.physmem.perBankWrBursts::2 18985 # Per bank write bursts -system.physmem.perBankWrBursts::3 19009 # Per bank write bursts -system.physmem.perBankWrBursts::4 18161 # Per bank write bursts -system.physmem.perBankWrBursts::5 18506 # Per bank write bursts -system.physmem.perBankWrBursts::6 19135 # Per bank write bursts -system.physmem.perBankWrBursts::7 19090 # Per bank write bursts -system.physmem.perBankWrBursts::8 18676 # Per bank write bursts -system.physmem.perBankWrBursts::9 18214 # Per bank write bursts -system.physmem.perBankWrBursts::10 18884 # Per bank write bursts -system.physmem.perBankWrBursts::11 17768 # Per bank write bursts -system.physmem.perBankWrBursts::12 17389 # Per bank write bursts -system.physmem.perBankWrBursts::13 16996 # Per bank write bursts -system.physmem.perBankWrBursts::14 17798 # Per bank write bursts -system.physmem.perBankWrBursts::15 17855 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 195189 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24028 # Per bank write bursts +system.physmem.perBankRdBursts::1 26400 # Per bank write bursts +system.physmem.perBankRdBursts::2 24980 # Per bank write bursts +system.physmem.perBankRdBursts::3 24600 # Per bank write bursts +system.physmem.perBankRdBursts::4 23395 # Per bank write bursts +system.physmem.perBankRdBursts::5 23728 # Per bank write bursts +system.physmem.perBankRdBursts::6 24595 # Per bank write bursts +system.physmem.perBankRdBursts::7 24357 # Per bank write bursts +system.physmem.perBankRdBursts::8 23707 # Per bank write bursts +system.physmem.perBankRdBursts::9 23543 # Per bank write bursts +system.physmem.perBankRdBursts::10 24760 # Per bank write bursts +system.physmem.perBankRdBursts::11 23969 # Per bank write bursts +system.physmem.perBankRdBursts::12 23156 # Per bank write bursts +system.physmem.perBankRdBursts::13 22899 # Per bank write bursts +system.physmem.perBankRdBursts::14 23872 # Per bank write bursts +system.physmem.perBankRdBursts::15 23880 # Per bank write bursts +system.physmem.perBankWrBursts::0 18605 # Per bank write bursts +system.physmem.perBankWrBursts::1 19929 # Per bank write bursts +system.physmem.perBankWrBursts::2 19196 # Per bank write bursts +system.physmem.perBankWrBursts::3 18982 # Per bank write bursts +system.physmem.perBankWrBursts::4 18144 # Per bank write bursts +system.physmem.perBankWrBursts::5 18488 # Per bank write bursts +system.physmem.perBankWrBursts::6 19136 # Per bank write bursts +system.physmem.perBankWrBursts::7 19077 # Per bank write bursts +system.physmem.perBankWrBursts::8 18672 # Per bank write bursts +system.physmem.perBankWrBursts::9 17940 # Per bank write bursts +system.physmem.perBankWrBursts::10 18886 # Per bank write bursts +system.physmem.perBankWrBursts::11 17736 # Per bank write bursts +system.physmem.perBankWrBursts::12 17372 # Per bank write bursts +system.physmem.perBankWrBursts::13 16987 # Per bank write bursts +system.physmem.perBankWrBursts::14 17811 # Per bank write bursts +system.physmem.perBankWrBursts::15 17848 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 417315698500 # Total gap between requests +system.physmem.totGap 403706602500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386792 # Read request sizes (log2) +system.physmem.readPktSize::6 386152 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295029 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381444 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4617 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 294833 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380965 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -144,46 +144,46 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -193,347 +193,345 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.684816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.392327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.222401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54844 37.18% 37.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40100 27.19% 64.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13710 9.30% 73.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7409 5.02% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5412 3.67% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3888 2.64% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3038 2.06% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2781 1.89% 88.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16313 11.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147495 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17511 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.068928 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 218.794243 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17500 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 6 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146765 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.814963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.408246 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.979648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54126 36.88% 36.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39824 27.13% 64.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13787 9.39% 73.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7512 5.12% 78.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5608 3.82% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3872 2.64% 84.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3087 2.10% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2794 1.90% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16155 11.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146765 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17509 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.037923 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 218.270562 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17499 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17511 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17511 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.846668 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.775279 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.561224 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17315 98.88% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 151 0.86% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 21 0.12% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 5 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17511 # Writes before turning the bus around for reads -system.physmem.totQLat 4302860250 # Total ticks spent queuing -system.physmem.totMemAccLat 11548985250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11134.04 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17509 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17509 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.837569 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.769084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.527211 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17319 98.91% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 139 0.79% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 19 0.11% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 11 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 2 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17509 # Writes before turning the bus around for reads +system.physmem.totQLat 4289653250 # Total ticks spent queuing +system.physmem.totMemAccLat 11524697000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1929345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11116.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29884.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.25 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29866.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.74 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.22 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.82 # Data bus utilization in percentage -system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.40 # Average write queue length when enqueuing -system.physmem.readRowHits 318003 # Number of row buffer hits during reads -system.physmem.writeRowHits 215951 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.20 # Row buffer hit rate for writes -system.physmem.avgGap 612060.49 # Average gap between requests -system.physmem.pageHitRate 78.35 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 569562840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310773375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1528737600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 980981280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27256781760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63486572355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 194697293250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 288830702460 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.121537 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 323337240250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13934960000 # Time in different power states +system.physmem.busUtil 0.84 # Data bus utilization in percentage +system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.93 # Average write queue length when enqueuing +system.physmem.readRowHits 317973 # Number of row buffer hits during reads +system.physmem.writeRowHits 215927 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.24 # Row buffer hit rate for writes +system.physmem.avgGap 592827.45 # Average gap between requests +system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 569094120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310517625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1529307000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 981933840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62417540205 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187468813500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279645025170 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.702062 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311319479750 # Time in different power states +system.physmem_0.memoryStateTime::REF 13480480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80039955000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78902125750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 545136480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 297445500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1485127800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 930216960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 27256781760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61714779795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 196251513750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 288481002045 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.283509 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 325936894250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13934960000 # Time in different power states +system.physmem_1.actEnergy 540041040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 294665250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1479816000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 928013760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26367818880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60324869565 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189304489500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279239713995 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.698075 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314381404750 # Time in different power states +system.physmem_1.memoryStateTime::REF 13480480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77440301000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75839865250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 230117471 # Number of BP lookups -system.cpu.branchPred.condPredicted 230117471 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9743461 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131565165 # Number of BTB lookups -system.cpu.branchPred.BTBHits 128785895 # Number of BTB hits +system.cpu.branchPred.lookups 219316547 # Number of BP lookups +system.cpu.branchPred.condPredicted 219316547 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8533340 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 124021938 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121820147 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.887534 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27740805 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1463511 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.224676 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27066490 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1406992 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 834631611 # number of cpu cycles simulated +system.cpu.numCycles 807413288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 185091560 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1269611575 # Number of instructions fetch has processed -system.cpu.fetch.Branches 230117471 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 156526700 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638324625 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20217139 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 543 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 96744 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 810626 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1773 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 179459083 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2721482 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 834434550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.830059 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.382636 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175921222 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208610344 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219316547 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148886637 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 621541997 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17781141 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 241 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 95442 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 760366 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1422 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170776115 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2324492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 807211301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.786075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367353 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 426827210 51.15% 51.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33688698 4.04% 55.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 32854559 3.94% 59.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33384869 4.00% 63.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27147041 3.25% 66.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27739461 3.32% 69.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37019184 4.44% 74.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33642570 4.03% 78.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 182130958 21.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 417064653 51.67% 51.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32628603 4.04% 55.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31895320 3.95% 59.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32734486 4.06% 63.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26590994 3.29% 67.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26897855 3.33% 70.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35141039 4.35% 74.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31437377 3.89% 78.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172820974 21.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 834434550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.275711 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.521164 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127499737 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 374953474 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240627559 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81245211 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10108569 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2225588633 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10108569 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159647168 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 159927889 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39744 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285634401 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219076779 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2175363345 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 166678 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 136608012 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24443504 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 48002145 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2279615876 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5501425511 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3499355021 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 55759 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 807211301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271629 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.496892 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120518152 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370503139 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225214950 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82084490 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8890570 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132165876 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8890570 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152539883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150620560 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 39985 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271567858 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223552445 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088589695 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 134600 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138169190 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24839349 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50537004 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190785289 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5278493147 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3357262511 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 59407 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 665575022 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3123 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2916 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 415832299 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 528432376 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 209864891 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 239237917 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72205880 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2101284212 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24336 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1827034633 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 401491 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 572319847 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 974276898 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23784 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 834434550 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.189548 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.072515 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576744435 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3185 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2908 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 421985771 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507135954 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200817604 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 229019753 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68232285 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023164418 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22990 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1789038207 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 420221 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494198707 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 833041498 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 22438 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 807211301 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.216320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.070566 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 254639697 30.52% 30.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 125724347 15.07% 45.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119353828 14.30% 59.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 111074898 13.31% 73.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 92504387 11.09% 84.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61470741 7.37% 91.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43061930 5.16% 96.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19202673 2.30% 99.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7402049 0.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238530872 29.55% 29.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123621910 15.31% 44.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 118898033 14.73% 59.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107819129 13.36% 72.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89545218 11.09% 84.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60296093 7.47% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42279085 5.24% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18940691 2.35% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7280270 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 834434550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 807211301 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11320186 42.67% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12172571 45.88% 88.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3037482 11.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11520759 42.69% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12368193 45.83% 88.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3098262 11.48% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2711288 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1211298887 66.30% 66.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 388808 0.02% 66.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 134 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 33 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 403 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435055867 23.81% 90.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173698155 9.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2718353 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183132640 66.13% 66.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 368609 0.02% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881115 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 64 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 344 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428541213 23.95% 90.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170395732 9.52% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1827034633 # Type of FU issued -system.cpu.iq.rate 2.189031 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26530239 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014521 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4515402541 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2673889112 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1796964967 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 33005 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 70700 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7229 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1850838268 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 15316 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185431148 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1789038207 # Type of FU issued +system.cpu.iq.rate 2.215765 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26987214 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015085 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412665624 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517635859 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762385104 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 29526 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 68682 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5548 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813294148 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12920 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 186084957 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 144332039 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 211913 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 385225 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 60704705 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123036250 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 211434 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 371907 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51657418 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19195 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1040 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 23176 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1099 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10108569 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 107095351 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6179627 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2101308548 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 404076 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 528434196 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 209864891 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6959 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1875437 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3414890 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 385225 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5746544 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4564008 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10310552 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1805625643 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 428837620 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21408990 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8890570 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97719419 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6134161 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023187408 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 375929 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507138407 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200817604 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7250 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1817237 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3413935 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 371907 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4848104 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4143061 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8991165 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1770021029 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423153321 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19017178 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 599025712 # number of memory reference insts executed -system.cpu.iew.exec_branches 171773578 # Number of branches executed -system.cpu.iew.exec_stores 170188092 # Number of stores executed -system.cpu.iew.exec_rate 2.163380 # Inst execution rate -system.cpu.iew.wb_sent 1802216227 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1796972196 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1368071729 # num instructions producing a value -system.cpu.iew.wb_consumers 2090120765 # num instructions consuming a value +system.cpu.iew.exec_refs 590346194 # number of memory reference insts executed +system.cpu.iew.exec_branches 168990321 # Number of branches executed +system.cpu.iew.exec_stores 167192873 # Number of stores executed +system.cpu.iew.exec_rate 2.192212 # Inst execution rate +system.cpu.iew.wb_sent 1766892997 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762390652 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339756908 # num instructions producing a value +system.cpu.iew.wb_consumers 2049972766 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.153012 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654542 # average fanout of values written-back +system.cpu.iew.wb_rate 2.182762 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653549 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 572398548 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 494260386 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9828987 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 756729949 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.020521 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.547401 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8618895 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 739988037 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.066234 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.575521 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 287871292 38.04% 38.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 175370720 23.17% 61.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57379665 7.58% 68.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86292739 11.40% 80.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27182541 3.59% 83.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27109377 3.58% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9779675 1.29% 88.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8926185 1.18% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 76817755 10.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 275878158 37.28% 37.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172126899 23.26% 60.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 55937459 7.56% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86300571 11.66% 79.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25876597 3.50% 83.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26568843 3.59% 86.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9870767 1.33% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8919978 1.21% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78508765 10.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 756729949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 739988037 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -579,344 +577,344 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 76817755 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2781299443 # The number of ROB reads -system.cpu.rob.rob_writes 4280666670 # The number of ROB writes -system.cpu.timesIdled 2296 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 197061 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78508765 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2684728359 # The number of ROB reads +system.cpu.rob.rob_writes 4113896609 # The number of ROB writes +system.cpu.timesIdled 2328 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 201987 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.009378 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.009378 # CPI: Total CPI of All Threads -system.cpu.ipc 0.990709 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.990709 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2762055581 # number of integer regfile reads -system.cpu.int_regfile_writes 1465119637 # number of integer regfile writes -system.cpu.fp_regfile_reads 7518 # number of floating regfile reads -system.cpu.fp_regfile_writes 448 # number of floating regfile writes -system.cpu.cc_regfile_reads 600894138 # number of cc regfile reads -system.cpu.cc_regfile_writes 409652534 # number of cc regfile writes -system.cpu.misc_regfile_reads 990211728 # number of misc regfile reads +system.cpu.cpi 0.976461 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.976461 # CPI: Total CPI of All Threads +system.cpu.ipc 1.024106 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024106 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722667059 # number of integer regfile reads +system.cpu.int_regfile_writes 1435857659 # number of integer regfile writes +system.cpu.fp_regfile_reads 5817 # number of floating regfile reads +system.cpu.fp_regfile_writes 496 # number of floating regfile writes +system.cpu.cc_regfile_reads 596670071 # number of cc regfile reads +system.cpu.cc_regfile_writes 405476387 # number of cc regfile writes +system.cpu.misc_regfile_reads 971632449 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534268 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.022618 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 387933013 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538364 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 152.827968 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1679458500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.022618 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2530789 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.813367 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381875640 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534885 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.648112 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.813367 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 875 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3172 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 784997698 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 784997698 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 239283827 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 239283827 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148189705 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148189705 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 387473532 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 387473532 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 387473532 # number of overall hits -system.cpu.dcache.overall_hits::total 387473532 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2785638 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2785638 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 970497 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 970497 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3756135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3756135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3756135 # number of overall misses -system.cpu.dcache.overall_misses::total 3756135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59461217500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59461217500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 30522057998 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 30522057998 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89983275498 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89983275498 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89983275498 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89983275498 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 242069465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 242069465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 772839713 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 772839713 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233227342 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233227342 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148173773 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148173773 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381401115 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381401115 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381401115 # number of overall hits +system.cpu.dcache.overall_hits::total 381401115 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2764870 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2764870 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 986429 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 986429 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3751299 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3751299 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3751299 # number of overall misses +system.cpu.dcache.overall_misses::total 3751299 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58802289500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58802289500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31059853996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31059853996 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89862143496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89862143496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89862143496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89862143496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 235992212 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 235992212 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 391229667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 391229667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 391229667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 391229667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011508 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011508 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006506 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006506 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009601 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009601 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009601 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009601 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21345.636978 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21345.636978 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31449.925139 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31449.925139 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23956.347548 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23956.347548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.347548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23956.347548 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 11065 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 19 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1184 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.345439 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 9.500000 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385152414 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385152414 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385152414 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385152414 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011716 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011716 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006613 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009740 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009740 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009740 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009740 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21267.650739 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21267.650739 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31487.166330 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31487.166330 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23954.940274 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23954.940274 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23954.940274 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9795 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1045 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.373206 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2332624 # number of writebacks -system.cpu.dcache.writebacks::total 2332624 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017670 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1017670 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19246 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19246 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1036916 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1036916 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1036916 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1036916 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767968 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767968 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 951251 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 951251 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2719219 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2719219 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2719219 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2719219 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33611924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33611924000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29320675500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 29320675500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62932599500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62932599500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62932599500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62932599500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006377 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006377 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006950 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006950 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006950 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006950 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19011.613332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19011.613332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30823.279555 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30823.279555 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23143.630395 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23143.630395 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23143.630395 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23143.630395 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330774 # number of writebacks +system.cpu.dcache.writebacks::total 2330774 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1000095 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1000095 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19339 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19339 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1019434 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1019434 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1019434 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29840523997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29840523997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63382041997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63382041997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63382041997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63382041997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007478 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007478 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006484 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006484 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23201.015422 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23201.015422 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6980 # number of replacements -system.cpu.icache.tags.tagsinuse 1050.498551 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 179263698 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8570 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20917.584364 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 6640 # number of replacements +system.cpu.icache.tags.tagsinuse 1037.923261 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 170565267 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8248 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20679.591052 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1050.498551 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.512939 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.512939 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1590 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 300 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1165 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.776367 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 359107751 # Number of tag accesses -system.cpu.icache.tags.data_accesses 359107751 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 179266886 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 179266886 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 179266886 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 179266886 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 179266886 # number of overall hits -system.cpu.icache.overall_hits::total 179266886 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 192197 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 192197 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 192197 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 192197 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 192197 # 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number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 179459083 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 179459083 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6515.817094 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6515.817094 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6515.817094 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6515.817094 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6515.817094 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6515.817094 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1416 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.923261 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506798 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506798 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341757570 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341757570 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170568161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170568161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170568161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170568161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170568161 # number of overall hits +system.cpu.icache.overall_hits::total 170568161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 207953 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 207953 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 207953 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 207953 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 207953 # number of overall misses +system.cpu.icache.overall_misses::total 207953 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1300977000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1300977000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1300977000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1300977000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1300977000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1300977000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 170776114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 170776114 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 170776114 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 170776114 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 170776114 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 170776114 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001218 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001218 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001218 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001218 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001218 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001218 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6256.110756 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6256.110756 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6256.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6256.110756 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6256.110756 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 718 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67.428571 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 59.833333 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 189586 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 189586 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 189586 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 945150498 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 945150498 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 945150498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 945150498 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 945150498 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 945150498 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001056 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001056 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001056 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4985.339097 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4985.339097 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4985.339097 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 4985.339097 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4985.339097 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 4985.339097 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2609 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2609 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2609 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2609 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2609 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2609 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205344 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 205344 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 205344 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 205344 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 205344 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 205344 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 976991000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 976991000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 976991000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 976991000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 976991000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 976991000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001202 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001202 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001202 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001202 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4757.825892 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4757.825892 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4757.825892 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4757.825892 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 354113 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29616.739115 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3899842 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 386474 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.090826 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 197713230000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 20951.203852 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.356614 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8414.178648 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.639380 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007671 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.256780 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.903831 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32361 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13363 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18669 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987579 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43221136 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43221136 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 2332624 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2332624 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1893 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1893 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564122 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564122 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5120 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 5120 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1590908 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1590908 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5120 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2155030 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2160150 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5120 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2155030 # number of overall hits -system.cpu.l2cache.overall_hits::total 2160150 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26726414500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26968420500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989533 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989533 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268119 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268119 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.405779 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099951 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099951 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151016 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151878 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.405779 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151016 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151878 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21037.656419 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21037.656419 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69266.841509 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69266.841509 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71408.921933 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71408.921933 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70469.652803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70469.652803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71408.921933 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69821.196398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69835.549633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71408.921933 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69821.196398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69835.549633 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990664 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990664 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268078 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268078 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.410515 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099902 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099902 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151861 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.410515 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151861 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 21050.320300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 21050.320300 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69272.367032 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69272.367032 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71578.231293 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71578.231293 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70450.344652 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70450.344652 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71578.231293 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.754492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69830.192905 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 1957165 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2627653 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 256317 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 180855 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 180855 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770784 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770784 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 189586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1767580 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 204722 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7961776 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8166498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 551488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311743232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312294720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 535081 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5804166 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.061010 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.239349 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1969728 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2625607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 254220 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 196981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 196981 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770499 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770499 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 205344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764386 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 219812 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7983854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8203666 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 526976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311402176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311929152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 550579 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5828110 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.060649 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.238686 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5450053 93.90% 93.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 354113 6.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5474639 93.94% 93.94% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 353471 6.06% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5804166 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5083850495 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 284382490 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5828110 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5096523027 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 308017990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3897973573 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 180168 # Transaction distribution -system.membus.trans_dist::Writeback 295029 # Transaction distribution -system.membus.trans_dist::CleanEvict 57519 # Transaction distribution -system.membus.trans_dist::UpgradeReq 179000 # Transaction distribution -system.membus.trans_dist::UpgradeResp 179000 # Transaction distribution -system.membus.trans_dist::ReadExReq 206624 # Transaction distribution -system.membus.trans_dist::ReadExResp 206624 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180168 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1484132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1484132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1484132 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43636544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43636544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43636544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.respLayer1.occupancy 3900818077 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 179644 # Transaction distribution +system.membus.trans_dist::Writeback 294833 # Transaction distribution +system.membus.trans_dist::CleanEvict 57066 # Transaction distribution +system.membus.trans_dist::UpgradeReq 195189 # Transaction distribution +system.membus.trans_dist::UpgradeResp 195189 # Transaction distribution +system.membus.trans_dist::ReadExReq 206507 # Transaction distribution +system.membus.trans_dist::ReadExResp 206507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179645 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1514580 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1514580 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1514580 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43582976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43582976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43582976 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 918340 # Request fanout histogram +system.membus.snoop_fanout::samples 933240 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 918340 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 933240 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 918340 # Request fanout histogram -system.membus.reqLayer0.occupancy 2219848930 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2404009566 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 933240 # Request fanout histogram +system.membus.reqLayer0.occupancy 2243803396 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2433027599 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index de26fb04a..bab78d9da 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -84,7 +84,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -134,7 +134,7 @@ system=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -200,7 +200,7 @@ system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini index 607fa4fde..00495eb93 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini @@ -125,7 +125,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -548,7 +548,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -597,7 +597,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr index 664365742..3b53ebc6c 100644..100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout index 2951870e8..d34e3637b 100644..100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout @@ -3,14 +3,15 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:41:53 -gem5 started May 7 2014 10:42:15 -gem5 executing on cz3212c2d7 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 21:15:11 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.216667 -Exiting @ tick 220685290500 because target called exit() +Exiting @ tick 225710988500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 1a7177e69..988455083 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226045 # Number of seconds simulated -sim_ticks 226044973500 # Number of ticks simulated -final_tick 226044973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225711 # Number of seconds simulated +sim_ticks 225710988500 # Number of ticks simulated +final_tick 225710988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 304016 # Simulator instruction rate (inst/s) -host_op_rate 304016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172378586 # Simulator tick rate (ticks/s) -host_mem_usage 302856 # Number of bytes of host memory used -host_seconds 1311.33 # Real time elapsed on the host +host_inst_rate 225638 # Simulator instruction rate (inst/s) +host_op_rate 225638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 127748919 # Simulator tick rate (ticks/s) +host_mem_usage 297512 # Number of bytes of host memory used +host_seconds 1766.83 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 249344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 249088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory -system.physmem.bytes_read::total 503936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 249344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 249344 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3896 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 503680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 249088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 249088 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3892 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7874 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1103073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1126289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2229362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1103073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1103073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1103073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1126289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2229362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7874 # Number of read requests accepted +system.physmem.num_reads::total 7870 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1103571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1127956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2231526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1103571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1103571 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1103571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1127956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2231526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7870 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7874 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7870 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 503936 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 503680 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 503936 # Total read bytes from the system interface side +system.physmem.bytesReadSys 503680 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 551 # Per bank write bursts +system.physmem.perBankRdBursts::0 549 # Per bank write bursts system.physmem.perBankRdBursts::1 676 # Per bank write bursts system.physmem.perBankRdBursts::2 471 # Per bank write bursts system.physmem.perBankRdBursts::3 633 # Per bank write bursts -system.physmem.perBankRdBursts::4 475 # Per bank write bursts -system.physmem.perBankRdBursts::5 478 # Per bank write bursts +system.physmem.perBankRdBursts::4 474 # Per bank write bursts +system.physmem.perBankRdBursts::5 477 # Per bank write bursts system.physmem.perBankRdBursts::6 563 # Per bank write bursts system.physmem.perBankRdBursts::7 560 # Per bank write bursts system.physmem.perBankRdBursts::8 470 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226044886000 # Total gap between requests +system.physmem.totGap 225710901000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7874 # Read request sizes (log2) +system.physmem.readPktSize::6 7870 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 969 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1551 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.878788 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.961760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.450478 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 540 34.82% 34.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 341 21.99% 56.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 198 12.77% 69.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 105 6.77% 76.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 68 4.38% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 2.77% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.13% 85.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.32% 87.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 187 12.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1551 # Bytes accessed per row activation -system.physmem.totQLat 53691750 # Total ticks spent queuing -system.physmem.totMemAccLat 201329250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 39370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6818.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 324.680906 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 194.047178 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.516800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 535 34.63% 34.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 349 22.59% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 192 12.43% 69.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 105 6.80% 76.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 65 4.21% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 2.52% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.14% 85.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 33 2.14% 87.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 194 12.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1545 # Bytes accessed per row activation +system.physmem.totQLat 52849750 # Total ticks spent queuing +system.physmem.totMemAccLat 200412250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 39350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6715.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25568.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25465.34 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6316 # Number of row buffer hits during reads +system.physmem.readRowHits 6317 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.21 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28707757.94 # Average gap between requests -system.physmem.pageHitRate 80.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6811560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3716625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 34210800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28679911.18 # Average gap between requests +system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6743520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3679500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 34132800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5854324365 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130490358000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151153426710 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.693587 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217080502500 # Time in different power states -system.physmem_0.memoryStateTime::REF 7548060000 # Time in different power states +system.physmem_0.refreshEnergy 14742137280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5830950375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130309976250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 150927619725 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.685069 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 216780859000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7536880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1414335000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1390733500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4914000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2681250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 27011400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4936680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2693625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 27003600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14764005360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5569701705 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 130740027000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151108340715 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.494129 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 217498306250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7548060000 # Time in different power states +system.physmem_1.refreshEnergy 14742137280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5568136200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 130540515000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 150885422385 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.498114 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 217165940000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7536880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 997097750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1005282000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46270920 # Number of BP lookups -system.cpu.branchPred.condPredicted 26727376 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1017825 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25620092 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21360645 # Number of BTB hits +system.cpu.branchPred.lookups 46155674 # Number of BP lookups +system.cpu.branchPred.condPredicted 26673496 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 964868 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25433927 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21299796 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.374584 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341957 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 83.745605 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8306241 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 322 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95612152 # DTB read hits -system.cpu.dtb.read_misses 116 # DTB read misses +system.cpu.dtb.read_hits 95501420 # DTB read hits +system.cpu.dtb.read_misses 115 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95612268 # DTB read accesses -system.cpu.dtb.write_hits 73605970 # DTB write hits -system.cpu.dtb.write_misses 858 # DTB write misses +system.cpu.dtb.read_accesses 95501535 # DTB read accesses +system.cpu.dtb.write_hits 73594615 # DTB write hits +system.cpu.dtb.write_misses 852 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73606828 # DTB write accesses -system.cpu.dtb.data_hits 169218122 # DTB hits -system.cpu.dtb.data_misses 974 # DTB misses +system.cpu.dtb.write_accesses 73595467 # DTB write accesses +system.cpu.dtb.data_hits 169096035 # DTB hits +system.cpu.dtb.data_misses 967 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 169219096 # DTB accesses -system.cpu.itb.fetch_hits 98739640 # ITB hits -system.cpu.itb.fetch_misses 1232 # ITB misses +system.cpu.dtb.data_accesses 169097002 # DTB accesses +system.cpu.itb.fetch_hits 98403660 # ITB hits +system.cpu.itb.fetch_misses 1242 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98740872 # ITB accesses +system.cpu.itb.fetch_accesses 98404902 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,83 +293,83 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 452089947 # number of cpu cycles simulated +system.cpu.numCycles 451421977 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4488161 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4268732 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.134011 # CPI: cycles per instruction -system.cpu.ipc 0.881826 # IPC: instructions per cycle -system.cpu.tickCycles 448265885 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3824062 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.132335 # CPI: cycles per instruction +system.cpu.ipc 0.883131 # IPC: instructions per cycle +system.cpu.tickCycles 447606238 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3815739 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.715048 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168032888 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.720604 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 167948311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40344.030732 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40323.724130 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.715048 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803641 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803641 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.720604 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803643 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803643 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336084171 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336084171 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94518093 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94518093 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514795 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514795 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168032888 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168032888 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168032888 # number of overall hits -system.cpu.dcache.overall_hits::total 168032888 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5935 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5935 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 335915017 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 335915017 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94433513 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94433513 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 167948311 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 167948311 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 167948311 # number of overall hits +system.cpu.dcache.overall_hits::total 167948311 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1183 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1183 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 7115 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 7115 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 7115 # number of overall misses system.cpu.dcache.overall_misses::total 7115 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87916000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87916000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 428863500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 428863500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 516779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 516779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 516779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 516779500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94519273 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94519273 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 87406500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 87406500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 430164000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 430164000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 517570500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 517570500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 517570500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 517570500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94434696 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94434696 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168040003 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168040003 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168040003 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168040003 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000012 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167955426 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167955426 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167955426 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167955426 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000013 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000013 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 74505.084746 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 74505.084746 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72260.067397 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72260.067397 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72632.396346 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72632.396346 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72632.396346 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73885.460693 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73885.460693 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72515.846258 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72515.846258 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72743.569923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72743.569923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72743.569923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72743.569923 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,10 +380,10 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 654 # number of writebacks system.cpu.dcache.writebacks::total 654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2739 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2739 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 214 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 214 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 2950 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 2950 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 2950 # number of overall MSHR hits @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4165 system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 71088500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 71088500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 239432500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 239432500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310521000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 310521000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310521000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 310521000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70744000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 70744000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240380000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 240380000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 311124000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 311124000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 311124000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 311124000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73362.745098 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73362.745098 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74916.301627 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74916.301627 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74554.861945 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74554.861945 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73007.223942 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73007.223942 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75212.765957 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75212.765957 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74699.639856 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74699.639856 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74699.639856 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74699.639856 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3197 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.682192 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98734465 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5175 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19079.123671 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3187 # number of replacements +system.cpu.icache.tags.tagsinuse 1919.659270 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98398495 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5165 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19051.015489 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.682192 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936857 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936857 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1919.659270 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.937334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.937334 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197484455 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197484455 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98734465 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98734465 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98734465 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98734465 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98734465 # number of overall hits -system.cpu.icache.overall_hits::total 98734465 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5175 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5175 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5175 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5175 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5175 # number of overall misses -system.cpu.icache.overall_misses::total 5175 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 319209000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 319209000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 319209000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 319209000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 319209000 # 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number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98398495 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98398495 # number of overall hits +system.cpu.icache.overall_hits::total 98398495 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5165 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5165 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5165 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5165 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5165 # number of overall misses +system.cpu.icache.overall_misses::total 5165 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 317382500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 317382500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 317382500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 317382500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 317382500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 317382500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98403660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98403660 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98403660 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98403660 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98403660 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98403660 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61682.898551 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61682.898551 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61682.898551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61682.898551 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61682.898551 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.693127 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61448.693127 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 253881000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 262496000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 516377000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 7870 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 203693000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 203693000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252182500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252182500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59406500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59406500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252182500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 263099500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 515282000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252182500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 263099500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 515282000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.752850 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753533 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843041 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752850 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.843516 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753533 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843041 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64630.379343 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64630.379343 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65164.527721 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65164.527721 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71046.967895 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71046.967895 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65164.527721 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65986.928105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65580.010160 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.843516 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64932.419509 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64932.419509 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64795.092497 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64795.092497 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.931034 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64795.092497 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64795.092497 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66138.637506 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65474.205845 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 6142 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 6132 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3304 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5165 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13547 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13517 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 331200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330560 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 639616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 638976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13308 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 13288 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 13288 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13308 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7308000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 13288 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7298000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7762500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7747500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6247999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 4737 # Transaction distribution +system.membus.trans_dist::ReadResp 4733 # Transaction distribution system.membus.trans_dist::ReadExReq 3137 # Transaction distribution system.membus.trans_dist::ReadExResp 3137 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4737 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15748 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15748 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 503936 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15740 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 503680 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7874 # Request fanout histogram +system.membus.snoop_fanout::samples 7870 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7874 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7870 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7874 # Request fanout histogram -system.membus.reqLayer0.occupancy 9183500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7870 # Request fanout histogram +system.membus.reqLayer0.occupancy 9171000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41813250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41782250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index b0756d2d6..fda724fd7 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -150,7 +150,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -497,7 +497,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -546,7 +546,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -609,7 +609,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index c9fcb56b0..d6aa6688c 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:19:59 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 20:55:00 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -12,4 +14,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.066667 -Exiting @ tick 69793219500 because target called exit() +Exiting @ tick 67874346000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index be9d713b1..49a2168d9 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.069809 # Number of seconds simulated -sim_ticks 69809049000 # Number of ticks simulated -final_tick 69809049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.067874 # Number of seconds simulated +sim_ticks 67874346000 # Number of ticks simulated +final_tick 67874346000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246384 # Simulator instruction rate (inst/s) -host_op_rate 246384 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45796096 # Simulator tick rate (ticks/s) -host_mem_usage 304152 # Number of bytes of host memory used -host_seconds 1524.35 # Real time elapsed on the host +host_inst_rate 172313 # Simulator instruction rate (inst/s) +host_op_rate 172313 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31140671 # Simulator tick rate (ticks/s) +host_mem_usage 298536 # Number of bytes of host memory used +host_seconds 2179.60 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255680 # Number of bytes read from this memory -system.physmem.bytes_read::total 477184 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221504 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3461 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3995 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7456 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3172998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3662562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6835561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3172998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3172998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3172998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3662562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6835561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7456 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 220544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory +system.physmem.bytes_read::total 475840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220544 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7435 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3249298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3761303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7010602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3249298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3249298 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3249298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3761303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7010602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7435 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7456 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7435 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 477184 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 475840 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 477184 # Total read bytes from the system interface side +system.physmem.bytesReadSys 475840 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 527 # Per bank write bursts -system.physmem.perBankRdBursts::1 655 # Per bank write bursts -system.physmem.perBankRdBursts::2 454 # Per bank write bursts +system.physmem.perBankRdBursts::0 524 # Per bank write bursts +system.physmem.perBankRdBursts::1 653 # Per bank write bursts +system.physmem.perBankRdBursts::2 449 # Per bank write bursts system.physmem.perBankRdBursts::3 600 # Per bank write bursts system.physmem.perBankRdBursts::4 446 # Per bank write bursts -system.physmem.perBankRdBursts::5 455 # Per bank write bursts -system.physmem.perBankRdBursts::6 515 # Per bank write bursts -system.physmem.perBankRdBursts::7 525 # Per bank write bursts -system.physmem.perBankRdBursts::8 439 # Per bank write bursts +system.physmem.perBankRdBursts::5 454 # Per bank write bursts +system.physmem.perBankRdBursts::6 513 # Per bank write bursts +system.physmem.perBankRdBursts::7 523 # Per bank write bursts +system.physmem.perBankRdBursts::8 435 # Per bank write bursts system.physmem.perBankRdBursts::9 407 # Per bank write bursts system.physmem.perBankRdBursts::10 338 # Per bank write bursts system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 542 # Per bank write bursts -system.physmem.perBankRdBursts::14 455 # Per bank write bursts +system.physmem.perBankRdBursts::14 453 # Per bank write bursts system.physmem.perBankRdBursts::15 379 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 69808953500 # Total gap between requests +system.physmem.totGap 67874250500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7456 # Read request sizes (log2) +system.physmem.readPktSize::6 7435 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1892 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1860 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 349.142435 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.457712 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.186854 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 436 32.18% 32.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 321 23.69% 55.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 135 9.96% 65.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 103 7.60% 73.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 56 4.13% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 42 3.10% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.73% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 28 2.07% 85.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 197 14.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1355 # Bytes accessed per row activation -system.physmem.totQLat 63176250 # Total ticks spent queuing -system.physmem.totMemAccLat 202976250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37280000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8473.21 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1352 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 350.437870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.390396 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.239962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 445 32.91% 32.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 293 21.67% 54.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 153 11.32% 65.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 95 7.03% 72.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 4.66% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 2.88% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.96% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 2.22% 85.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 194 14.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1352 # Bytes accessed per row activation +system.physmem.totQLat 65565000 # Total ticks spent queuing +system.physmem.totMemAccLat 204971250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37175000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8818.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27223.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27568.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 7.01 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.84 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 7.01 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6090 # Number of row buffer hits during reads +system.physmem.readRowHits 6075 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.68 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9362788.83 # Average gap between requests -system.physmem.pageHitRate 81.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5828760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3180375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32370000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9129018.22 # Average gap between requests +system.physmem.pageHitRate 81.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5866560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3201000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32260800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4559240400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2097349200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 40042614750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 46740583485 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.597578 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 66614495250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2330900000 # Time in different power states +system.physmem_0.refreshEnergy 4433117520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2086073460 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 38893911750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 45454431090 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.698264 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 64700624500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2266420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 861488750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 905970500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4399920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2400750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25256400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4354560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2376000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25482600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4559240400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1988059680 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 40138482750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 46717839900 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.271757 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 66771998750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2330900000 # Time in different power states +system.physmem_1.refreshEnergy 4433117520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1937209410 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 39024494250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 45427034340 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.294616 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 64919021500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2266420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 701106250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 687756000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 51296431 # Number of BP lookups -system.cpu.branchPred.condPredicted 29722668 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1234399 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 27069453 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23684308 # Number of BTB hits +system.cpu.branchPred.lookups 50012521 # Number of BP lookups +system.cpu.branchPred.condPredicted 28997086 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 979524 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24735831 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22942844 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.494594 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9353372 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 312 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.751458 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9100143 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 303 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103786850 # DTB read hits -system.cpu.dtb.read_misses 91978 # DTB read misses -system.cpu.dtb.read_acv 49358 # DTB read access violations -system.cpu.dtb.read_accesses 103878828 # DTB read accesses -system.cpu.dtb.write_hits 79421845 # DTB write hits -system.cpu.dtb.write_misses 1562 # DTB write misses +system.cpu.dtb.read_hits 102391599 # DTB read hits +system.cpu.dtb.read_misses 62990 # DTB read misses +system.cpu.dtb.read_acv 49453 # DTB read access violations +system.cpu.dtb.read_accesses 102454589 # DTB read accesses +system.cpu.dtb.write_hits 78819200 # DTB write hits +system.cpu.dtb.write_misses 1456 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79423407 # DTB write accesses -system.cpu.dtb.data_hits 183208695 # DTB hits -system.cpu.dtb.data_misses 93540 # DTB misses -system.cpu.dtb.data_acv 49360 # DTB access violations -system.cpu.dtb.data_accesses 183302235 # DTB accesses -system.cpu.itb.fetch_hits 51432488 # ITB hits -system.cpu.itb.fetch_misses 372 # ITB misses +system.cpu.dtb.write_accesses 78820656 # DTB write accesses +system.cpu.dtb.data_hits 181210799 # DTB hits +system.cpu.dtb.data_misses 64446 # DTB misses +system.cpu.dtb.data_acv 49455 # DTB access violations +system.cpu.dtb.data_accesses 181275245 # DTB accesses +system.cpu.itb.fetch_hits 49841893 # ITB hits +system.cpu.itb.fetch_misses 342 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51432860 # ITB accesses +system.cpu.itb.fetch_accesses 49842235 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,239 +293,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 139618100 # number of cpu cycles simulated +system.cpu.numCycles 135748695 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52215637 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 458041697 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51296431 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33037680 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85803922 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2575582 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 50498280 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448284151 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50012521 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32042987 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 83907127 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2061462 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 177 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13927 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51432488 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 569689 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139321507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287660 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.344182 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13448 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 46 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 49841893 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 439921 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 135449808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.309596 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.352335 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58400173 41.92% 41.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4522566 3.25% 45.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7306043 5.24% 50.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5576459 4.00% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12017776 8.63% 63.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8032548 5.77% 68.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5948759 4.27% 73.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1886194 1.35% 74.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35630989 25.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 56539159 41.74% 41.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4401809 3.25% 44.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7053804 5.21% 50.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5366390 3.96% 54.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11526105 8.51% 62.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7792927 5.75% 68.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5844960 4.32% 72.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1860483 1.37% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35064171 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139321507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367405 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.280676 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45279858 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16277373 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71952167 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4528520 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1283589 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9590263 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 452242919 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14142 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1283589 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47190225 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5719256 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519758 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74463142 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10145537 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 448534058 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439648 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2541243 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2902301 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3500431 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 292850852 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 590664412 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 420646005 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 170018406 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 135449808 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.368420 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.302309 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 43878250 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15711242 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 70556820 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4276924 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1026572 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9420233 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4199 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 443516613 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 13825 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1026572 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45656178 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5038667 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519602 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72948338 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10260451 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440529832 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 437774 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2529018 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2798103 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3728351 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 287391913 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 579992044 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 412277767 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 167714276 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33318523 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37911 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 320 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 16086321 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106433302 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81699514 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12490023 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9782021 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 415154479 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 307 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 407277518 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 483889 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 39579977 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18549388 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 92 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139321507 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.923293 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.222373 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27859584 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37459 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 301 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 15899092 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104653375 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80643825 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12436283 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9680421 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 409213494 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 295 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 402403006 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 455901 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 33638980 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16018200 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 135449808 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.970864 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.211480 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24043039 17.26% 17.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19688824 14.13% 31.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22672553 16.27% 47.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18939258 13.59% 61.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19545668 14.03% 75.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14219061 10.21% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9684319 6.95% 92.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6188357 4.44% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4340428 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21699625 16.02% 16.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19301136 14.25% 30.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22441860 16.57% 46.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18632936 13.76% 60.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19381094 14.31% 74.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 13936411 10.29% 85.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9566467 7.06% 92.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6208123 4.58% 96.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4282156 3.16% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139321507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 135449808 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 265122 1.33% 1.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 1.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 151057 0.76% 2.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 93335 0.47% 2.55% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3062 0.02% 2.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3506383 17.53% 20.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1668666 8.34% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9341831 46.71% 75.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4968318 24.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 249921 1.26% 1.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 142099 0.71% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 92744 0.47% 2.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 4235 0.02% 2.46% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3484759 17.51% 19.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1673016 8.41% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9313907 46.79% 75.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4943226 24.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153385991 37.66% 37.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128232 0.52% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 151496219 37.65% 37.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128363 0.53% 38.19% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37448194 9.19% 47.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7543709 1.85% 49.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2805732 0.69% 49.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16759263 4.11% 54.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1610357 0.40% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105461195 25.89% 80.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80101264 19.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37051349 9.21% 47.39% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7361129 1.83% 49.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793884 0.69% 49.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16753499 4.16% 54.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1596248 0.40% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.48% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103848617 25.81% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79340117 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 407277518 # Type of FU issued -system.cpu.iq.rate 2.917083 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19997775 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.049101 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 626671270 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 266840013 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237433052 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 347686937 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187970906 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163426789 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246404368 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 180837344 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19931279 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 402403006 # Type of FU issued +system.cpu.iq.rate 2.964323 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19903907 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049463 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 615743047 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 258422157 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234653025 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 344872581 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 184503638 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 162319054 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 242850926 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 179422406 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19947233 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11678815 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 164981 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76480 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8178785 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9898888 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 123887 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 73372 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7123096 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 381276 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3827 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 383831 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3808 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1283589 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4537578 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 127300 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 440164979 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 164208 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106433302 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81699514 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 307 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6586 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 117247 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76480 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1004792 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 416739 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1421531 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403496390 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103928218 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3781128 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1026572 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3903842 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 90265 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 434136051 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 99585 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104653375 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80643825 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 295 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7679 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82299 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 73372 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 826459 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 307772 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1134231 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 399253806 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 102504065 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3149200 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 25010193 # number of nop insts executed -system.cpu.iew.exec_refs 183351660 # number of memory reference insts executed -system.cpu.iew.exec_branches 47000418 # Number of branches executed -system.cpu.iew.exec_stores 79423442 # Number of stores executed -system.cpu.iew.exec_rate 2.890001 # Inst execution rate -system.cpu.iew.wb_sent 401708524 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400859841 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198115569 # num instructions producing a value -system.cpu.iew.wb_consumers 284128842 # num instructions consuming a value +system.cpu.iew.exec_nop 24922262 # number of nop insts executed +system.cpu.iew.exec_refs 181324750 # number of memory reference insts executed +system.cpu.iew.exec_branches 46546315 # Number of branches executed +system.cpu.iew.exec_stores 78820685 # Number of stores executed +system.cpu.iew.exec_rate 2.941124 # Inst execution rate +system.cpu.iew.wb_sent 397727618 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 396972079 # cumulative count of insts written-back +system.cpu.iew.wb_producers 196558282 # num instructions producing a value +system.cpu.iew.wb_consumers 281889088 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.871117 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.697274 # average fanout of values written-back +system.cpu.iew.wb_rate 2.924316 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697289 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 41501718 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35472304 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1230197 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133512631 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.985969 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.212275 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 975365 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130528765 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 3.054228 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.231390 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48674660 36.46% 36.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18127731 13.58% 50.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9648746 7.23% 57.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8719124 6.53% 63.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6443109 4.83% 68.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4416607 3.31% 71.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5004547 3.75% 75.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2625621 1.97% 77.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29852486 22.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 46472448 35.60% 35.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 17656165 13.53% 49.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9417491 7.21% 56.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8632138 6.61% 62.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6273043 4.81% 67.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4304526 3.30% 71.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 4966466 3.80% 74.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2588480 1.98% 76.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 30218008 23.15% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133512631 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 130528765 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,333 +571,333 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29852486 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 543823469 # The number of ROB reads -system.cpu.rob.rob_writes 886153369 # The number of ROB writes -system.cpu.timesIdled 3159 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 296593 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 30218008 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 534444667 # The number of ROB reads +system.cpu.rob.rob_writes 873208037 # The number of ROB writes +system.cpu.timesIdled 3160 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 298887 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.371745 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.371745 # CPI: Total CPI of All Threads -system.cpu.ipc 2.690015 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.690015 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403553331 # number of integer regfile reads -system.cpu.int_regfile_writes 172072539 # number of integer regfile writes -system.cpu.fp_regfile_reads 158043337 # number of floating regfile reads -system.cpu.fp_regfile_writes 105673333 # number of floating regfile writes +system.cpu.cpi 0.361442 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.361442 # CPI: Total CPI of All Threads +system.cpu.ipc 2.766692 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.766692 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 399091287 # number of integer regfile reads +system.cpu.int_regfile_writes 169885620 # number of integer regfile writes +system.cpu.fp_regfile_reads 156870882 # number of floating regfile reads +system.cpu.fp_regfile_writes 104904950 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 795 # number of replacements -system.cpu.dcache.tags.tagsinuse 3296.035456 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156970312 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37400.598523 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 777 # number of replacements +system.cpu.dcache.tags.tagsinuse 3293.050932 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 155556653 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4177 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37241.238449 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3296.035456 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804696 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804696 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3402 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 3293.050932 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830566 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313987939 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313987939 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83469338 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83469338 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500964 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500964 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156970302 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156970302 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156970302 # number of overall hits -system.cpu.dcache.overall_hits::total 156970302 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1794 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1794 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19765 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19765 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21559 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21559 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21559 # number of overall misses -system.cpu.dcache.overall_misses::total 21559 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128871000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128871000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1185279954 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1185279954 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1314150954 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1314150954 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1314150954 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1314150954 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83471132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83471132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 311160441 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 311160441 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82055589 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82055589 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501058 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501058 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 155556647 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 155556647 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 155556647 # number of overall hits +system.cpu.dcache.overall_hits::total 155556647 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1808 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19671 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19671 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21479 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21479 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21479 # number of overall misses +system.cpu.dcache.overall_misses::total 21479 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 128709000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 128709000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1198982453 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1198982453 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1327691453 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1327691453 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1327691453 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1327691453 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82057397 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82057397 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156991861 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156991861 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156991861 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156991861 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71834.448161 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71834.448161 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59968.629092 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59968.629092 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60956.025511 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60956.025511 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60956.025511 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60956.025511 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 49421 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 88 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 747 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 155578126 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 155578126 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 155578126 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 155578126 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71188.606195 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71188.606195 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60951.779421 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60951.779421 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61813.466782 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61813.466782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61813.466782 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61813.466782 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 49798 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 86 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 748 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.159304 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 88 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.574866 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 86 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 671 # number of writebacks -system.cpu.dcache.writebacks::total 671 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 799 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 799 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16563 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16563 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17362 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17362 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65049.579954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65049.579954 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65049.579954 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 650 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68.250000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92.857143 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # 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mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67398.016405 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67398.016405 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67398.016405 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67398.016405 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67398.016405 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67398.016405 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1543 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1543 # 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number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 209892500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 209892500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227966000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227966000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 64994500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 64994500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227966000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274887000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 502853000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227966000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274887000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 502853000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977826 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977826 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.847453 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.868342 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.868342 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951870 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900374 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.847453 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951870 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900374 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67036.889173 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67036.889173 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65867.090436 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65867.090436 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75225.115741 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75225.115741 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65867.090436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68807.759700 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67442.730687 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65867.090436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68807.759700 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67442.730687 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3129 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3129 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3446 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3446 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 860 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 860 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7435 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3446 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 213568000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 213568000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226720500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226720500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63683000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63683000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226720500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 277251000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 503971500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226720500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 277251000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 503971500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981185 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.850025 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.850025 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870445 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870445 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.850025 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.954992 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.903292 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.850025 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.954992 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.903292 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68254.394375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68254.394375 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65792.367963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65792.367963 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74050 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74050 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65792.367963 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69503.885686 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67783.658373 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65792.367963 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69503.885686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67783.658373 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 5079 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 671 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4084 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 995 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9189 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19514 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 572928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 5042 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3189 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3189 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4054 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 988 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10234 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9131 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 19365 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 259456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 568768 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 11233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 11134 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11233 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11134 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11233 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 6287500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11134 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 6223000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6126000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6081000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6295500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6265500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 4325 # Transaction distribution -system.membus.trans_dist::ReadExReq 3131 # Transaction distribution -system.membus.trans_dist::ReadExResp 3131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4325 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14912 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477184 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 4306 # Transaction distribution +system.membus.trans_dist::ReadExReq 3129 # Transaction distribution +system.membus.trans_dist::ReadExResp 3129 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4306 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14870 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14870 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 475840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 475840 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7456 # Request fanout histogram +system.membus.snoop_fanout::samples 7435 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7456 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7435 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7456 # Request fanout histogram -system.membus.reqLayer0.occupancy 9215500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7435 # Request fanout histogram +system.membus.reqLayer0.occupancy 9180000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39331250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39204250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index ca6ea576a..427c7c717 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -118,7 +118,7 @@ eventq_index=0 size=64 [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -167,7 +167,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini index e8259a3e5..c0afc2364 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -759,7 +759,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout index 3857083f4..8d785cb1f 100755 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:25:17 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x3ccd9b0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 @@ -14,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.210000 -Exiting @ tick 216864820000 because target called exit() +Exiting @ tick 215505832500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 454441ad4..333ae52c9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,60 +1,60 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216071 # Number of seconds simulated -sim_ticks 216071083000 # Number of ticks simulated -final_tick 216071083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.215506 # Number of seconds simulated +sim_ticks 215505832500 # Number of ticks simulated +final_tick 215505832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173126 # Simulator instruction rate (inst/s) -host_op_rate 207857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137004908 # Simulator tick rate (ticks/s) -host_mem_usage 323124 # Number of bytes of host memory used -host_seconds 1577.10 # Real time elapsed on the host +host_inst_rate 114925 # Simulator instruction rate (inst/s) +host_op_rate 137980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90709005 # Simulator tick rate (ticks/s) +host_mem_usage 317788 # Number of bytes of host memory used +host_seconds 2375.79 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 218880 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 218880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 218880 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3420 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1013889 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1232779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2246668 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1013889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1013889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1013889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1232779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2246668 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7585 # Number of read requests accepted +system.physmem.num_reads::total 7582 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1015657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1236013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2251670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1015657 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1015657 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1015657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1236013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2251670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7582 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7582 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485248 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485248 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 630 # Per bank write bursts -system.physmem.perBankRdBursts::1 843 # Per bank write bursts +system.physmem.perBankRdBursts::1 844 # Per bank write bursts system.physmem.perBankRdBursts::2 628 # Per bank write bursts system.physmem.perBankRdBursts::3 541 # Per bank write bursts system.physmem.perBankRdBursts::4 466 # Per bank write bursts system.physmem.perBankRdBursts::5 349 # Per bank write bursts -system.physmem.perBankRdBursts::6 173 # Per bank write bursts +system.physmem.perBankRdBursts::6 171 # Per bank write bursts system.physmem.perBankRdBursts::7 228 # Per bank write bursts system.physmem.perBankRdBursts::8 209 # Per bank write bursts -system.physmem.perBankRdBursts::9 311 # Per bank write bursts +system.physmem.perBankRdBursts::9 310 # Per bank write bursts system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts system.physmem.perBankRdBursts::12 553 # Per bank write bursts -system.physmem.perBankRdBursts::13 706 # Per bank write bursts +system.physmem.perBankRdBursts::13 705 # Per bank write bursts system.physmem.perBankRdBursts::14 638 # Per bank write bursts system.physmem.perBankRdBursts::15 540 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216070847500 # Total gap between requests +system.physmem.totGap 215505593500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7585 # Read request sizes (log2) +system.physmem.readPktSize::6 7582 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6627 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 892 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.445847 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.975712 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.801659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 552 36.68% 36.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 337 22.39% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 156 10.37% 69.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 81 5.38% 74.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 75 4.98% 79.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 59 3.92% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 41 2.72% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 29 1.93% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 175 11.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation -system.physmem.totQLat 52368250 # Total ticks spent queuing -system.physmem.totMemAccLat 194587000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6904.19 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1519 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 318.272548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.961816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.159233 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 550 36.21% 36.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 342 22.51% 58.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 179 11.78% 70.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 82 5.40% 75.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 73 4.81% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 43 2.83% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.44% 85.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 1.97% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 183 12.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1519 # Bytes accessed per row activation +system.physmem.totQLat 52046750 # Total ticks spent queuing +system.physmem.totMemAccLat 194209250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6864.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25654.19 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25614.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.25 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6074 # Number of row buffer hits during reads +system.physmem.readRowHits 6056 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28486598.22 # Average gap between requests -system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5050080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2755500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29959800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28423317.53 # Average gap between requests +system.physmem.pageHitRate 79.87 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4997160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2726625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14112540000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5672899350 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 124664991000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144488195730 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.714152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 207389955000 # Time in different power states -system.physmem_0.memoryStateTime::REF 7215000000 # Time in different power states +system.physmem_0.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5632744275 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 124359177000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 144104965380 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.699601 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 206882994500 # Time in different power states +system.physmem_0.memoryStateTime::REF 7196020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1464485500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1423707500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6320160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3448500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28992600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6463800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3526875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28977000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14112540000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5762856465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 124586081250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 144500238975 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.769890 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 207255387750 # Time in different power states -system.physmem_1.memoryStateTime::REF 7215000000 # Time in different power states +system.physmem_1.refreshEnergy 14075415120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5808881115 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 124204671000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 144127934910 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.806188 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 206624169250 # Time in different power states +system.physmem_1.memoryStateTime::REF 7196020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1598323500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1683261250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33111389 # Number of BP lookups -system.cpu.branchPred.condPredicted 17094855 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1552605 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17374125 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15590921 # Number of BTB hits +system.cpu.branchPred.lookups 32816945 # Number of BP lookups +system.cpu.branchPred.condPredicted 16892744 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1463888 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17497063 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15468368 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.736439 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6603992 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 88.405511 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6575577 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 432142166 # number of cpu cycles simulated +system.cpu.numCycles 431011665 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037857 # Number of instructions committed system.cpu.committedOps 327812214 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4177938 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 3889170 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.582719 # CPI: cycles per instruction -system.cpu.ipc 0.631824 # IPC: instructions per cycle -system.cpu.tickCycles 428506724 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3635442 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.578578 # CPI: cycles per instruction +system.cpu.ipc 0.633481 # IPC: instructions per cycle +system.cpu.tickCycles 427409330 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3602335 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.759854 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168767138 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.814933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168714880 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37412.356019 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37400.771448 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.759854 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753359 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753359 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.814933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753373 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753373 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id @@ -404,72 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337553367 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337553367 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86634356 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86634356 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047452 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047452 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 337448855 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337448855 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86582107 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86582107 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047449 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047449 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63534 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63534 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168681808 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168681808 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168745348 # number of overall hits -system.cpu.dcache.overall_hits::total 168745348 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168629556 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168629556 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168693090 # number of overall hits +system.cpu.dcache.overall_hits::total 168693090 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5225 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5225 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 7284 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7284 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses -system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 134727000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 134727000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 395694000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 395694000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 530421000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 530421000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 530421000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 530421000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86636415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86636415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 5228 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5228 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 5 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 5 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 7287 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7287 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7292 # number of overall misses +system.cpu.dcache.overall_misses::total 7292 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 135542000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 135542000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 392317500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 392317500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 527859500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 527859500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 527859500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 527859500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86584166 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86584166 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63539 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63539 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168689092 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168689092 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168752638 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168752638 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168636843 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168636843 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168700382 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168700382 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000094 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000094 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000079 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000079 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65433.220010 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 65433.220010 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75730.909091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75730.909091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72820.016474 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72820.016474 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72760.082305 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72760.082305 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65829.043225 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65829.043225 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75041.602907 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75041.602907 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72438.520653 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72438.520653 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72388.850795 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72388.850795 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,109 +480,109 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2355 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2355 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2777 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2777 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2777 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2777 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 421 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 421 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2358 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2358 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1638 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1638 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4507 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4508 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4508 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108637000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 108637000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220584500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 220584500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 322000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 322000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329221500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 329221500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329543500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 329543500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109498500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109498500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 218637500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 218637500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 238000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 238000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 328136000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 328136000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 328374000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 328374000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000063 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000047 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000047 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66363.469762 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66363.469762 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76858.710801 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76858.710801 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80500 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73046.705125 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73046.705125 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73053.314121 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73053.314121 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66848.901099 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66848.901099 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76180.313589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76180.313589 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79333.333333 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72789.707187 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 72789.707187 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72794.058967 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 72794.058967 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36911 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.852805 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73041980 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38848 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1880.199238 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36873 # number of replacements +system.cpu.icache.tags.tagsinuse 1923.841153 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 72548906 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38809 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1869.383545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852805 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1923.841153 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939376 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939376 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 274 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1488 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146200506 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146200506 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73041980 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73041980 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73041980 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73041980 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73041980 # number of overall hits -system.cpu.icache.overall_hits::total 73041980 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38849 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38849 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38849 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38849 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38849 # number of overall misses -system.cpu.icache.overall_misses::total 38849 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 726693000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 726693000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 726693000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 726693000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 726693000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 726693000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73080829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73080829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73080829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73080829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73080829 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73080829 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000532 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000532 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000532 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000532 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000532 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000532 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18705.578007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18705.578007 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18705.578007 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18705.578007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18705.578007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18705.578007 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::3 276 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1485 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 145214241 # Number of tag accesses +system.cpu.icache.tags.data_accesses 145214241 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 72548906 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 72548906 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 72548906 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 72548906 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 72548906 # number of overall hits +system.cpu.icache.overall_hits::total 72548906 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38810 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38810 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38810 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38810 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38810 # number of overall misses +system.cpu.icache.overall_misses::total 38810 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 726866500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 726866500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 726866500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 726866500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 726866500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 726866500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 72587716 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 72587716 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 72587716 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 72587716 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 72587716 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 72587716 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000535 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000535 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000535 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000535 # 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miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75028.030834 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75028.030834 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75475.014611 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75475.014611 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77177.037037 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77177.037037 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75609.034881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75475.014611 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75718.125595 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75609.034881 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -734,106 +734,106 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 42 system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3423 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3423 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3420 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3420 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1308 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1308 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3420 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7582 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 187536500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 187536500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223262000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223262000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 87309500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 87309500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223262000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 274846000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 498108000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223262000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 274846000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 498108000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 7582 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 185590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 185590000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 223941000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 223941000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 88101000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 88101000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 223941000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 273691000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 497632000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 223941000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 273691000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 497632000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088110 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088122 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797075 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174931 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088110 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.175019 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088122 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174931 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65710.056062 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65710.056062 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65224.072451 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65224.072451 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66750.382263 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66750.382263 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65224.072451 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66037.001442 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65670.138431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65224.072451 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66037.001442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65670.138431 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.175019 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65028.030834 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65028.030834 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65479.824561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65479.824561 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67355.504587 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67355.504587 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65479.824561 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65759.490630 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65633.342126 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 40489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40450 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 22221 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 22200 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 38849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 38810 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99591 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 109950 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2486272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 109851 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2483776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2839616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2837120 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 81625 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 81548 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 81625 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 81548 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 81625 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 41822500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 81548 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 41784000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58272998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58214498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6787458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 4731 # Transaction distribution +system.membus.trans_dist::ReadResp 4728 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4731 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4728 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7585 # Request fanout histogram +system.membus.snoop_fanout::samples 7582 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7582 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7585 # Request fanout histogram -system.membus.reqLayer0.occupancy 8844500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7582 # Request fanout histogram +system.membus.reqLayer0.occupancy 8861000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40248250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40238250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index e201ba957..be385b04e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -688,7 +688,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/eon +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 88cf501ca..cbd037166 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,13 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 10:58:25 -gem5 started Apr 22 2015 11:46:25 -gem5 executing on phenom -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:15:27 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x2c9dca0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 @@ -15,4 +16,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.110000 -Exiting @ tick 112553814500 because target called exit() +Exiting @ tick 112687034500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 563fc0af8..a48a8bb5c 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,17 +1,19 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:27:26 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 00:56:31 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x56d96c0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.210000 -Exiting @ tick 212344043000 because target called exit() +OO-style eon Time= 0.200000 +Exiting @ tick 201717314000 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index b055586ab..892e458ed 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -156,7 +156,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -266,7 +266,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 9d7fb2434..d5cd58d2c 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,17 +1,19 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 17:29:04 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 03:56:42 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x4c37d00 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. -OO-style eon Time= 0.520000 -Exiting @ tick 525834342000 because target called exit() +OO-style eon Time= 0.510000 +Exiting @ tick 517235407500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini index 7c811432f..cd33c8a8d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini @@ -125,7 +125,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -548,7 +548,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -597,7 +597,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr index cf5d2b5cc..41d370561 100644..100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout index fadc32183..0aa9c6519 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 3 2015 14:54:12 -gem5 started Jul 3 2015 15:19:41 +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 21:30:12 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing @@ -650,4 +650,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 560939897000 because target called exit() +Exiting @ tick 560939659000 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index f751a40d2..0cd2c8d2d 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.560940 # Number of seconds simulated -sim_ticks 560939897000 # Number of ticks simulated -final_tick 560939897000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 560939659000 # Number of ticks simulated +final_tick 560939659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 309766 # Simulator instruction rate (inst/s) -host_op_rate 309766 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187082277 # Simulator tick rate (ticks/s) -host_mem_usage 305868 # Number of bytes of host memory used -host_seconds 2998.36 # Real time elapsed on the host +host_inst_rate 234960 # Simulator instruction rate (inst/s) +host_op_rate 234960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 141903449 # Simulator tick rate (ticks/s) +host_mem_usage 300504 # Number of bytes of host memory used +host_seconds 3952.97 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 186880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18514240 # Number of bytes read from this memory -system.physmem.bytes_read::total 18701120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 186880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 186880 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 186816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18514112 # Number of bytes read from this memory +system.physmem.bytes_read::total 18700928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 186816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 186816 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2920 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289285 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289283 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292202 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 333155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33005746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33338902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333155 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333155 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7608145 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7608145 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7608145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 333155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33005746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40947046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292205 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 333041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33005532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33338573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 333041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 333041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7608148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7608148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7608148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 333041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33005532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40946722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292202 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292205 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292202 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18680832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20288 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18701120 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18682112 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18816 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18700928 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 294 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18030 # Per bank write bursts -system.physmem.perBankRdBursts::1 18359 # Per bank write bursts -system.physmem.perBankRdBursts::2 18394 # Per bank write bursts -system.physmem.perBankRdBursts::3 18343 # Per bank write bursts -system.physmem.perBankRdBursts::4 18248 # Per bank write bursts -system.physmem.perBankRdBursts::5 18243 # Per bank write bursts -system.physmem.perBankRdBursts::6 18313 # Per bank write bursts -system.physmem.perBankRdBursts::7 18291 # Per bank write bursts -system.physmem.perBankRdBursts::8 18223 # Per bank write bursts -system.physmem.perBankRdBursts::9 18225 # Per bank write bursts -system.physmem.perBankRdBursts::10 18213 # Per bank write bursts -system.physmem.perBankRdBursts::11 18377 # Per bank write bursts -system.physmem.perBankRdBursts::12 18256 # Per bank write bursts -system.physmem.perBankRdBursts::13 18128 # Per bank write bursts -system.physmem.perBankRdBursts::14 18060 # Per bank write bursts -system.physmem.perBankRdBursts::15 18185 # Per bank write bursts +system.physmem.perBankRdBursts::0 18035 # Per bank write bursts +system.physmem.perBankRdBursts::1 18362 # Per bank write bursts +system.physmem.perBankRdBursts::2 18392 # Per bank write bursts +system.physmem.perBankRdBursts::3 18337 # Per bank write bursts +system.physmem.perBankRdBursts::4 18250 # Per bank write bursts +system.physmem.perBankRdBursts::5 18249 # Per bank write bursts +system.physmem.perBankRdBursts::6 18316 # Per bank write bursts +system.physmem.perBankRdBursts::7 18295 # Per bank write bursts +system.physmem.perBankRdBursts::8 18230 # Per bank write bursts +system.physmem.perBankRdBursts::9 18228 # Per bank write bursts +system.physmem.perBankRdBursts::10 18207 # Per bank write bursts +system.physmem.perBankRdBursts::11 18382 # Per bank write bursts +system.physmem.perBankRdBursts::12 18252 # Per bank write bursts +system.physmem.perBankRdBursts::13 18131 # Per bank write bursts +system.physmem.perBankRdBursts::14 18059 # Per bank write bursts +system.physmem.perBankRdBursts::15 18183 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4185 # Per bank write bursts +system.physmem.perBankWrBursts::9 4186 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 560939815000 # Total gap between requests +system.physmem.totGap 560939577000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292205 # Read request sizes (log2) +system.physmem.readPktSize::6 292202 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 291402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,20 +144,20 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4047 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4049 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4050 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4049 # What write queue length does an incoming req see @@ -193,46 +193,44 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 220.682651 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.922946 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 267.989820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 38271 36.81% 36.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43979 42.30% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8888 8.55% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 756 0.73% 88.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1408 1.35% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1167 1.12% 90.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 628 0.60% 91.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 577 0.55% 92.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8303 7.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 104019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 220.607081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.832345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 268.107277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 38319 36.84% 36.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43999 42.30% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8903 8.56% 87.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 723 0.70% 88.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1372 1.32% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1141 1.10% 90.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 666 0.64% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 599 0.58% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8297 7.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104019 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.413929 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.545155 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 755.096124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 70.696468 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.574169 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 760.359503 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4041 99.80% 99.80% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 3 0.07% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 3 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4049 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.463571 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.442765 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.845366 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3112 76.86% 76.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 934 23.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.463818 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.443063 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.844207 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3110 76.81% 76.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 939 23.19% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4049 # Writes before turning the bus around for reads -system.physmem.totQLat 2918754250 # Total ticks spent queuing -system.physmem.totMemAccLat 8391654250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9999.57 # Average queueing delay per DRAM burst +system.physmem.totQLat 2923147000 # Total ticks spent queuing +system.physmem.totMemAccLat 8396422000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1459540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10013.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28749.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28763.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 7.61 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 33.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 7.61 # Average system write bandwidth in MiByte/s @@ -241,71 +239,71 @@ system.physmem.busUtil 0.32 # Da system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.25 # Average write queue length when enqueuing -system.physmem.readRowHits 202534 # Number of row buffer hits during reads -system.physmem.writeRowHits 52030 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes -system.physmem.avgGap 1562994.07 # Average gap between requests -system.physmem.pageHitRate 70.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 391812120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 213786375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1140274200 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.30 # Average write queue length when enqueuing +system.physmem.readRowHits 202517 # Number of row buffer hits during reads +system.physmem.writeRowHits 52027 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.02 # Row buffer hit rate for writes +system.physmem.avgGap 1563006.47 # Average gap between requests +system.physmem.pageHitRate 70.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 392311080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 214058625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1140422400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 109227211875 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240749028000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 388576230570 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.726692 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 399826633250 # Time in different power states +system.physmem_0.actBackEnergy 109190821365 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240780947250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 388572678720 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.720364 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 399879041250 # Time in different power states system.physmem_0.memoryStateTime::REF 18730920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 142379745750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 142327335000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 394193520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 215085750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1136148000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215524800 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 394019640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 214990875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1136187000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215531280 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 36637679520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 109501586505 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240508346250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 388608564345 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.784339 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399420466000 # Time in different power states +system.physmem_1.actBackEnergy 109681250220 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 240350746500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 388630405035 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.823275 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 399158044000 # Time in different power states system.physmem_1.memoryStateTime::REF 18730920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 142786637000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 143048821000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125749081 # Number of BP lookups -system.cpu.branchPred.condPredicted 81144339 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157133 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103971313 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83513402 # Number of BTB hits +system.cpu.branchPred.lookups 125747730 # Number of BP lookups +system.cpu.branchPred.condPredicted 81143399 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12156451 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103980487 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83512673 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.323504 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691072 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9449 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.315716 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691015 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237538494 # DTB read hits -system.cpu.dtb.read_misses 198467 # DTB read misses +system.cpu.dtb.read_hits 237537770 # DTB read hits +system.cpu.dtb.read_misses 198464 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736961 # DTB read accesses -system.cpu.dtb.write_hits 98305022 # DTB write hits -system.cpu.dtb.write_misses 7216 # DTB write misses +system.cpu.dtb.read_accesses 237736234 # DTB read accesses +system.cpu.dtb.write_hits 98304947 # DTB write hits +system.cpu.dtb.write_misses 7177 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312238 # DTB write accesses -system.cpu.dtb.data_hits 335843516 # DTB hits -system.cpu.dtb.data_misses 205683 # DTB misses +system.cpu.dtb.write_accesses 98312124 # DTB write accesses +system.cpu.dtb.data_hits 335842717 # DTB hits +system.cpu.dtb.data_misses 205641 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336049199 # DTB accesses -system.cpu.itb.fetch_hits 316987000 # ITB hits +system.cpu.dtb.data_accesses 336048358 # DTB accesses +system.cpu.itb.fetch_hits 316984864 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 316987120 # ITB accesses +system.cpu.itb.fetch_accesses 316984984 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -319,67 +317,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1121879794 # number of cpu cycles simulated +system.cpu.numCycles 1121879318 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 30863449 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 30861365 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 1.207895 # CPI: cycles per instruction system.cpu.ipc 0.827887 # IPC: instructions per cycle -system.cpu.tickCycles 1059714780 # Number of cycles that the object actually ticked -system.cpu.idleCycles 62165014 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.723334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 322867251 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 413.599373 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 899878500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.723334 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999200 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999200 # Average percentage of cache occupancy +system.cpu.tickCycles 1059707231 # Number of cycles that the object actually ticked +system.cpu.idleCycles 62172087 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 776530 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.727909 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 322866545 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780626 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 413.599528 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 898816500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.727909 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999201 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999201 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 951 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1242 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1642 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 648213288 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 648213288 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 224703201 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 224703201 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164050 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164050 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 322867251 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322867251 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322867251 # number of overall hits -system.cpu.dcache.overall_hits::total 322867251 # number of overall hits +system.cpu.dcache.tags.tag_accesses 648211884 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 648211884 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 224702500 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 224702500 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164045 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164045 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 322866545 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 322866545 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 322866545 # number of overall hits +system.cpu.dcache.overall_hits::total 322866545 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137150 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137150 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849079 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849079 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849079 # number of overall misses -system.cpu.dcache.overall_misses::total 849079 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24888612000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24888612000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9943107500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9943107500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34831719500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34831719500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34831719500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34831719500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 225415130 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 225415130 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137155 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137155 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849084 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849084 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849084 # number of overall misses +system.cpu.dcache.overall_misses::total 849084 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24888766500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24888766500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9955853000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9955853000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34844619500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34844619500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34844619500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34844619500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 225414429 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 225414429 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 323716330 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 323716330 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323716330 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323716330 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 323715629 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 323715629 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 323715629 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 323715629 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003158 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -388,14 +386,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002623 system.cpu.dcache.demand_miss_rate::total 0.002623 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002623 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002623 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.401850 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.401850 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72498.049581 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72498.049581 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41022.943095 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41022.943095 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41022.943095 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41022.943095 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34959.618866 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34959.618866 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72588.334366 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72588.334366 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41037.894366 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41037.894366 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41037.894366 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41037.894366 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -404,32 +402,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88848 # number of writebacks -system.cpu.dcache.writebacks::total 88848 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68139 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68139 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68451 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68451 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68451 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68451 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 88852 # number of writebacks +system.cpu.dcache.writebacks::total 88852 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 314 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68144 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68144 # 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number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24170012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24170012500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4987370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4987370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29157382500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29157382500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29157382500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29157382500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 780626 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780626 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780626 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780626 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24170053000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24170053000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4993475000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4993475000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29163528000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29163528000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29163528000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29163528000 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37359.155345 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37359.155345 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10610 # number of replacements -system.cpu.icache.tags.tagsinuse 1686.330189 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 316974647 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12352 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25661.807562 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10565 # number of replacements +system.cpu.icache.tags.tagsinuse 1685.376392 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 316972557 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12306 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25757.561921 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1686.330189 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823403 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823403 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1742 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1685.376392 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.822938 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.822938 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1741 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1572 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.850586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 633986352 # Number of tag accesses -system.cpu.icache.tags.data_accesses 633986352 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 316974647 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 316974647 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 316974647 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 316974647 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 316974647 # number of overall hits -system.cpu.icache.overall_hits::total 316974647 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 316987000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 316987000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 316987000 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 316987000 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 316987000 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 316987000 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1571 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.850098 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 633982034 # Number of tag accesses +system.cpu.icache.tags.data_accesses 633982034 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 316972557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 316972557 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28472.739092 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28472.739092 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28472.739092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28472.739092 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28472.739092 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,129 +507,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12353 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12353 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12353 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12353 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12353 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12353 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339934000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 339934000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339934000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 339934000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339934000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 339934000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12307 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12307 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12307 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12307 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12307 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12307 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 338108000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 338108000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 338108000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 338108000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 338108000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 338108000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27518.335627 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27518.335627 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27518.335627 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27518.335627 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27518.335627 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27518.335627 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27472.820346 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27472.820346 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27472.820346 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27472.820346 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27472.820346 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27472.820346 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 259426 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32593.023927 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1218366 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292162 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.170173 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259423 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32592.990901 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1218275 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292159 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.169904 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2589.520333 # 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mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236461 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370580 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368491 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62908.440243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62908.440243 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66131.461828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66131.461828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70705.693047 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70705.693047 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66131.461828 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68909.374838 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68881.605785 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66131.461828 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68909.374838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68881.605785 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.237263 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.237263 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312863 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312863 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.237263 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370578 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.368509 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.237263 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370578 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.368509 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63000.045015 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63000.045015 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65717.636986 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65717.636986 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70706.606689 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70706.606689 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65717.636986 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65717.636986 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68931.169478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68899.056478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 723969 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155531 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 891037 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155535 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 890983 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711617 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35315 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337788 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373103 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55646464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56436992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259426 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1839549 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.141027 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.348049 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12307 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 711615 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35178 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337782 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2372960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 787584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55646592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56434176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259423 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1839451 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.141033 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.348056 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1580123 85.90% 85.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 259426 14.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1580028 85.90% 85.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 259423 14.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1839549 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 878909500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1839451 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 878866000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18528000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18459000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170942000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1170939000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225560 # Transaction distribution +system.membus.trans_dist::ReadResp 225557 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191116 # Transaction distribution +system.membus.trans_dist::CleanEvict 191114 # Transaction distribution system.membus.trans_dist::ReadExReq 66645 # Transaction distribution system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225560 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842209 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22968832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22968832 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225557 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842201 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 842201 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22968640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22968640 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 550004 # Request fanout histogram +system.membus.snoop_fanout::samples 549999 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 550004 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 549999 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 550004 # Request fanout histogram -system.membus.reqLayer0.occupancy 918579000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 549999 # Request fanout histogram +system.membus.reqLayer0.occupancy 918564500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1556120750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1556125250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 3af7f6d2b..0cac95bfa 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -150,7 +150,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -497,7 +497,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -546,7 +546,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -609,7 +609,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 408e44e03..c3e095b5a 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:48:44 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 20:54:31 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -648,4 +650,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 279668927000 because target called exit() +Exiting @ tick 276406029500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 7d418bd2e..4ab8a79d0 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.279557 # Number of seconds simulated -sim_ticks 279556845500 # Number of ticks simulated -final_tick 279556845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.276406 # Number of seconds simulated +sim_ticks 276406029500 # Number of ticks simulated +final_tick 276406029500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180071 # Simulator instruction rate (inst/s) -host_op_rate 180071 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59759118 # Simulator tick rate (ticks/s) -host_mem_usage 307148 # Number of bytes of host memory used -host_seconds 4678.06 # Real time elapsed on the host +host_inst_rate 130885 # Simulator instruction rate (inst/s) +host_op_rate 130885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42946592 # Simulator tick rate (ticks/s) +host_mem_usage 301528 # Number of bytes of host memory used +host_seconds 6436.04 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 176320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520448 # Number of bytes read from this memory -system.physmem.bytes_read::total 18696768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 176320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 176320 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18519360 # Number of bytes read from this memory +system.physmem.bytes_read::total 18693312 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2755 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289382 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292137 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 289365 # Number of read requests responded to by this memory +system.physmem.num_reads::total 292083 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 630713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66249310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 66880022 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 630713 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 630713 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15265990 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15265990 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15265990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 630713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66249310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82146012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292137 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 629335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 67000564 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 67629900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 629335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 629335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15440011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15440011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15440011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 629335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 67000564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 83069910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 292083 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292137 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 292083 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18678144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18624 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265920 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18696768 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18672064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue +system.physmem.bytesWritten 4266752 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18693312 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 291 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18015 # Per bank write bursts -system.physmem.perBankRdBursts::1 18332 # Per bank write bursts -system.physmem.perBankRdBursts::2 18407 # Per bank write bursts -system.physmem.perBankRdBursts::3 18336 # Per bank write bursts -system.physmem.perBankRdBursts::4 18249 # Per bank write bursts -system.physmem.perBankRdBursts::5 18230 # Per bank write bursts -system.physmem.perBankRdBursts::6 18323 # Per bank write bursts -system.physmem.perBankRdBursts::7 18299 # Per bank write bursts +system.physmem.perBankRdBursts::0 18010 # Per bank write bursts +system.physmem.perBankRdBursts::1 18319 # Per bank write bursts +system.physmem.perBankRdBursts::2 18376 # Per bank write bursts +system.physmem.perBankRdBursts::3 18330 # Per bank write bursts +system.physmem.perBankRdBursts::4 18231 # Per bank write bursts +system.physmem.perBankRdBursts::5 18221 # Per bank write bursts +system.physmem.perBankRdBursts::6 18322 # Per bank write bursts +system.physmem.perBankRdBursts::7 18297 # Per bank write bursts system.physmem.perBankRdBursts::8 18226 # Per bank write bursts -system.physmem.perBankRdBursts::9 18222 # Per bank write bursts -system.physmem.perBankRdBursts::10 18209 # Per bank write bursts -system.physmem.perBankRdBursts::11 18393 # Per bank write bursts -system.physmem.perBankRdBursts::12 18246 # Per bank write bursts -system.physmem.perBankRdBursts::13 18127 # Per bank write bursts -system.physmem.perBankRdBursts::14 18048 # Per bank write bursts -system.physmem.perBankRdBursts::15 18184 # Per bank write bursts +system.physmem.perBankRdBursts::9 18218 # Per bank write bursts +system.physmem.perBankRdBursts::10 18207 # Per bank write bursts +system.physmem.perBankRdBursts::11 18389 # Per bank write bursts +system.physmem.perBankRdBursts::12 18249 # Per bank write bursts +system.physmem.perBankRdBursts::13 18121 # Per bank write bursts +system.physmem.perBankRdBursts::14 18052 # Per bank write bursts +system.physmem.perBankRdBursts::15 18183 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,8 +73,8 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4180 # Per bank write bursts -system.physmem.perBankWrBursts::10 4149 # Per bank write bursts +system.physmem.perBankWrBursts::9 4192 # Per bank write bursts +system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4100 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 279556756000 # Total gap between requests +system.physmem.totGap 276405940000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292137 # Read request sizes (log2) +system.physmem.readPktSize::6 292083 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 215113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 216501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 907 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4062 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -193,120 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 99332 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 230.959771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 149.026626 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.596004 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 34426 34.66% 34.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42079 42.36% 77.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10100 10.17% 87.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 831 0.84% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1119 1.13% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 640 0.64% 89.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 198 0.20% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1366 1.38% 91.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8573 8.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 99332 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4052 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.011846 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.507282 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 732.804018 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4044 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 99437 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 230.668262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 148.414135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 279.665008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 34391 34.59% 34.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42842 43.08% 77.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10220 10.28% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 417 0.42% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 400 0.40% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 621 0.62% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 466 0.47% 89.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1450 1.46% 91.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8630 8.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 99437 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4053 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.663212 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.607328 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 761.755251 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4044 99.78% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 4 0.10% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-16383 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4052 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4052 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.449901 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.429330 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.841533 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3145 77.62% 77.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 903 22.29% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4052 # Writes before turning the bus around for reads -system.physmem.totQLat 3589265250 # Total ticks spent queuing -system.physmem.totMemAccLat 9061377750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12298.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4053 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4053 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.449050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.428679 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.836709 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3145 77.60% 77.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 905 22.33% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4053 # Writes before turning the bus around for reads +system.physmem.totQLat 3647206250 # Total ticks spent queuing +system.physmem.totMemAccLat 9117537500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1458755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12501.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31048.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 66.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 66.88 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 15.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31251.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 67.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.44 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 67.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 15.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.64 # Data bus utilization in percentage -system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.65 # Data bus utilization in percentage +system.physmem.busUtilRead 0.53 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.19 # Average write queue length when enqueuing -system.physmem.readRowHits 207190 # Number of row buffer hits during reads -system.physmem.writeRowHits 51966 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.93 # Row buffer hit rate for writes -system.physmem.avgGap 779100.26 # Average gap between requests -system.physmem.pageHitRate 72.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 374756760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204480375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1139564400 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.13 # Average write queue length when enqueuing +system.physmem.readRowHits 206989 # Number of row buffer hits during reads +system.physmem.writeRowHits 51984 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes +system.physmem.avgGap 770435.16 # Average gap between requests +system.physmem.pageHitRate 72.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 373947840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204039000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1139408400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18258829680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80335161315 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 97260556500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 197789787510 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.529215 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 161282435500 # Time in different power states -system.physmem_0.memoryStateTime::REF 9334780000 # Time in different power states +system.physmem_0.refreshEnergy 18053371440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80174383695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 95514202500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 195675791355 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.933114 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158383013500 # Time in different power states +system.physmem_0.memoryStateTime::REF 9229740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108932951500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108791696000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 375943680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 205128000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1135750200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215485920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18258829680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80056140615 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 97505311500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 197752589595 # Total energy per rank (pJ) -system.physmem_1.averagePower 707.396151 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 161684152500 # Time in different power states -system.physmem_1.memoryStateTime::REF 9334780000 # Time in different power states +system.physmem_1.actEnergy 377742960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 206109750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1135890600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 215570160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18053371440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80329865445 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 95377815000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 195696365355 # Total energy per rank (pJ) +system.physmem_1.averagePower 708.007549 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 158148138750 # Time in different power states +system.physmem_1.memoryStateTime::REF 9229740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108531075000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 109026483750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192642813 # Number of BP lookups -system.cpu.branchPred.condPredicted 125666016 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11886398 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 146763457 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126951211 # Number of BTB hits +system.cpu.branchPred.lookups 192576076 # Number of BP lookups +system.cpu.branchPred.condPredicted 126054565 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11561227 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 137875170 # Number of BTB lookups +system.cpu.branchPred.BTBHits 126274438 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 86.500559 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 29013974 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 143 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.586062 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28678363 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 136 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244534581 # DTB read hits -system.cpu.dtb.read_misses 309538 # DTB read misses +system.cpu.dtb.read_hits 242441387 # DTB read hits +system.cpu.dtb.read_misses 312131 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244844119 # DTB read accesses -system.cpu.dtb.write_hits 135677576 # DTB write hits -system.cpu.dtb.write_misses 31395 # DTB write misses +system.cpu.dtb.read_accesses 242753518 # DTB read accesses +system.cpu.dtb.write_hits 135445935 # DTB write hits +system.cpu.dtb.write_misses 31631 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135708971 # DTB write accesses -system.cpu.dtb.data_hits 380212157 # DTB hits -system.cpu.dtb.data_misses 340933 # DTB misses +system.cpu.dtb.write_accesses 135477566 # DTB write accesses +system.cpu.dtb.data_hits 377887322 # DTB hits +system.cpu.dtb.data_misses 343762 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380553090 # DTB accesses -system.cpu.itb.fetch_hits 197116758 # ITB hits -system.cpu.itb.fetch_misses 277 # ITB misses +system.cpu.dtb.data_accesses 378231084 # DTB accesses +system.cpu.itb.fetch_hits 194828154 # ITB hits +system.cpu.itb.fetch_misses 242 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 197117035 # ITB accesses +system.cpu.itb.fetch_accesses 194828396 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -320,238 +321,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 559113692 # number of cpu cycles simulated +system.cpu.numCycles 552812060 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202267120 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648589560 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192642813 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155965185 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 344477338 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24241354 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 146 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6562 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 197116758 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 7079440 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 558871871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.949852 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.174628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 198850471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1637321626 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192576076 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 154952801 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 341917067 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 23591046 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6993 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 194828154 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7885913 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 552570202 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.963102 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176487 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 239606568 42.87% 42.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30232310 5.41% 48.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22062681 3.95% 52.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36416175 6.52% 58.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 68096392 12.18% 70.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21641580 3.87% 74.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19299985 3.45% 78.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3539455 0.63% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 117976725 21.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 236054473 42.72% 42.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29638362 5.36% 48.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21702458 3.93% 52.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 35773228 6.47% 58.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 67707960 12.25% 70.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21595876 3.91% 74.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19328628 3.50% 78.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3978060 0.72% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 116791157 21.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 558871871 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.344550 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.948577 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168941255 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 91534254 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273571884 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12710570 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12113908 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15306458 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 6991 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1583914254 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25227 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12113908 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176800339 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61738556 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14140 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278402636 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29802292 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1538072104 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9577 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2573672 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 20322038 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7208635 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1027250775 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1768837330 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1729119220 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39718109 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 552570202 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.348357 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.961805 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 166802287 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 90542864 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 271199395 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12236841 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 11788815 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15468328 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 6932 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1567838176 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 24969 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 11788815 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 173688859 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 60716441 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13717 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276533617 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29828753 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1529250735 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8190 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2401406 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 20516503 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7198838 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1021411513 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1760089033 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1720202399 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39886633 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 388283617 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1370 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9395851 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372336921 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175495034 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40680070 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11286315 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1304559063 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1015639240 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8789930 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462177116 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 427685030 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 558871871 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.817302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.903889 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 382444355 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1364 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 84 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9081858 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 369185264 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 173801333 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40211283 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11128775 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1296786218 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 72 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1011356527 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8787388 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 454404260 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 422537101 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 35 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 552570202 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.830277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.913640 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 199951896 35.78% 35.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 92994240 16.64% 52.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 91399550 16.35% 68.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59708328 10.68% 79.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56828177 10.17% 89.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29755879 5.32% 94.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17031836 3.05% 98.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7177923 1.28% 99.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4024042 0.72% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 197270443 35.70% 35.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 90785192 16.43% 52.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 90547416 16.39% 68.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 58763251 10.63% 79.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 57064914 10.33% 89.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29634790 5.36% 94.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 16885134 3.06% 97.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7510156 1.36% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4108906 0.74% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 558871871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 552570202 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2464205 10.45% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15633751 66.29% 76.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5485030 23.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2519726 10.56% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15983640 67.00% 77.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5352814 22.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579358124 57.04% 57.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7924 0.00% 57.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13180764 1.30% 58.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339800 0.33% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 276992447 27.27% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138932359 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 577739239 57.13% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7929 0.00% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13232477 1.31% 58.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339799 0.33% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 274563645 27.15% 86.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138645616 13.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1015639240 # Type of FU issued -system.cpu.iq.rate 1.816516 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23582986 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023220 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2551718253 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1725674688 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 939925074 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70805014 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41106869 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34423614 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1002860612 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36360338 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50469534 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1011356527 # Type of FU issued +system.cpu.iq.rate 1.829476 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23856180 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023588 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2536915249 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1709850818 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 936642710 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 71011575 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41384719 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34526976 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 998747828 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36463603 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 49725855 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 134826324 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1160001 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45767 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77193834 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 131674667 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1209013 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45363 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 75500133 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2684 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4171 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2715 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4018 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12113908 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60768232 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 187260 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1479124792 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 20793 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372336921 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175495034 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 81 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15841 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 182755 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45767 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11880363 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16467 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11896830 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976089984 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244844291 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39549256 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 11788815 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 59738270 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 197040 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1470367053 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17961 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 369185264 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 173801333 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 72 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 15881 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 192528 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45363 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11555967 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 14465 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11570432 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 973002630 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 242753693 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 38353897 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174565646 # number of nop insts executed -system.cpu.iew.exec_refs 380553668 # number of memory reference insts executed -system.cpu.iew.exec_branches 129052167 # Number of branches executed -system.cpu.iew.exec_stores 135709377 # Number of stores executed -system.cpu.iew.exec_rate 1.745781 # Inst execution rate -system.cpu.iew.wb_sent 974867255 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974348688 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556190036 # num instructions producing a value -system.cpu.iew.wb_consumers 832343662 # num instructions consuming a value +system.cpu.iew.exec_nop 173580763 # number of nop insts executed +system.cpu.iew.exec_refs 378231547 # number of memory reference insts executed +system.cpu.iew.exec_branches 128483828 # Number of branches executed +system.cpu.iew.exec_stores 135477854 # Number of stores executed +system.cpu.iew.exec_rate 1.760097 # Inst execution rate +system.cpu.iew.wb_sent 971735885 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 971169686 # cumulative count of insts written-back +system.cpu.iew.wb_producers 554962956 # num instructions producing a value +system.cpu.iew.wb_consumers 830927766 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.742666 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668222 # average fanout of values written-back +system.cpu.iew.wb_rate 1.756781 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.667884 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543293982 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 534548617 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11879630 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 486147412 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.910095 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.597279 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11554520 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 481206030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.929709 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.612045 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 208054375 42.80% 42.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102342395 21.05% 63.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51700065 10.63% 74.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25702081 5.29% 79.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21547094 4.43% 84.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9129205 1.88% 86.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10401484 2.14% 88.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6670149 1.37% 89.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50600564 10.41% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 204042568 42.40% 42.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 101511322 21.10% 63.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 52351761 10.88% 74.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25424969 5.28% 79.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 20905527 4.34% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 8991227 1.87% 85.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10032438 2.08% 87.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6244738 1.30% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 51701480 10.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 486147412 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 481206030 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -597,335 +598,345 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50600564 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1904807320 # The number of ROB reads -system.cpu.rob.rob_writes 3016488956 # The number of ROB writes -system.cpu.timesIdled 3196 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 241821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 51701480 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1890019657 # The number of ROB reads +system.cpu.rob.rob_writes 2997637733 # The number of ROB writes +system.cpu.timesIdled 3185 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 241858 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.663729 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.663729 # CPI: Total CPI of All Threads -system.cpu.ipc 1.506638 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.506638 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237184723 # number of integer regfile reads -system.cpu.int_regfile_writes 705784215 # number of integer regfile writes -system.cpu.fp_regfile_reads 36689750 # number of floating regfile reads -system.cpu.fp_regfile_writes 24410793 # number of floating regfile writes +system.cpu.cpi 0.656249 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.656249 # CPI: Total CPI of All Threads +system.cpu.ipc 1.523813 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.523813 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1234257247 # number of integer regfile reads +system.cpu.int_regfile_writes 703449538 # number of integer regfile writes +system.cpu.fp_regfile_reads 36844878 # number of floating regfile reads +system.cpu.fp_regfile_writes 24462480 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777216 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.910211 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 289913128 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781312 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 371.059357 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 371553500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.910211 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999246 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999246 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777154 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.899235 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 288564425 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781250 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 369.362464 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 369553500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.899235 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999243 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999243 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2498 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 253 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2490 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 256 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585500596 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585500596 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192503314 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192503314 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97409790 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97409790 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 24 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 24 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289913104 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289913104 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289913104 # number of overall hits -system.cpu.dcache.overall_hits::total 289913104 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1555104 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1555104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 891410 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 891410 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2446514 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2446514 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2446514 # number of overall misses -system.cpu.dcache.overall_misses::total 2446514 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83796204000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83796204000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 61715896841 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 61715896841 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145512100841 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145512100841 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145512100841 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145512100841 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194058418 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194058418 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 582801760 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 582801760 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 191156368 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 191156368 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97408043 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97408043 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 14 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 14 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 288564411 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 288564411 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 288564411 # number of overall hits +system.cpu.dcache.overall_hits::total 288564411 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1552672 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1552672 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 893157 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 893157 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2445829 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2445829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2445829 # number of overall misses +system.cpu.dcache.overall_misses::total 2445829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 83271101000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 83271101000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62352545333 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62352545333 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 82500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 82500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145623646333 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145623646333 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145623646333 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145623646333 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 192709040 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 192709040 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292359618 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292359618 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292359618 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292359618 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008014 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009068 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009068 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008368 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008368 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008368 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008368 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53884.630224 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53884.630224 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69234.018960 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69234.018960 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59477.321953 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59477.321953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59477.321953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59477.321953 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 67906 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 347 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 515 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.164265 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 131.856311 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 291010240 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 291010240 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 291010240 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 291010240 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008057 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008057 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009086 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009086 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.066667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.066667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008405 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008405 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53630.838323 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53630.838323 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69811.405311 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69811.405311 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 82500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 82500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59539.586101 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59539.586101 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59539.586101 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59539.586101 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 22515 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 72899 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 341 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 517 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 66.026393 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 141.003868 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88850 # number of writebacks -system.cpu.dcache.writebacks::total 88850 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 842619 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 842619 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 822583 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 822583 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1665202 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1665202 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1665202 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1665202 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712485 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712485 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68827 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781312 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781312 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781312 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781312 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24145312000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24145312000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5651970498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5651970498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29797282498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29797282498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29797282498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29797282498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 88880 # number of writebacks +system.cpu.dcache.writebacks::total 88880 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840227 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 840227 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824352 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 824352 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1664579 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1664579 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1664579 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1664579 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712445 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712445 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68805 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68805 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781250 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781250 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781250 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781250 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24193547500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24193547500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5688085497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5688085497 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29881632997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29881632997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29881632997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29881632997 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003697 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003697 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33888.870643 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33888.870643 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82118.507243 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82118.507243 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38137.495006 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 38137.495006 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38137.495006 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 38137.495006 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002685 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002685 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002685 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002685 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33958.477497 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33958.477497 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82669.653325 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82669.653325 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38248.490236 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 38248.490236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38248.490236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 38248.490236 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4695 # number of replacements -system.cpu.icache.tags.tagsinuse 1651.888032 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 197108400 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6404 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30778.950656 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 4598 # number of replacements +system.cpu.icache.tags.tagsinuse 1641.391736 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 194819915 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6300 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 30923.796032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1651.888032 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.806586 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.806586 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1641.391736 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801461 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801461 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1702 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1553 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 394239920 # Number of tag accesses -system.cpu.icache.tags.data_accesses 394239920 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 197108400 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 197108400 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 197108400 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 197108400 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 197108400 # number of overall hits -system.cpu.icache.overall_hits::total 197108400 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8358 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8358 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8358 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8358 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8358 # number of overall misses -system.cpu.icache.overall_misses::total 8358 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 354830499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 354830499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 354830499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 354830499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 354830499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 354830499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 197116758 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 197116758 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 197116758 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 197116758 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 197116758 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 197116758 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.831055 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 389662608 # Number of tag accesses +system.cpu.icache.tags.data_accesses 389662608 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 194819915 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 194819915 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 194819915 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 194819915 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 194819915 # number of overall hits +system.cpu.icache.overall_hits::total 194819915 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8239 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8239 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8239 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8239 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8239 # number of overall misses +system.cpu.icache.overall_misses::total 8239 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 351244499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 351244499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 351244499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 351244499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 351244499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 351244499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 194828154 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 194828154 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 194828154 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 194828154 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 194828154 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 194828154 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42453.996052 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42453.996052 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42453.996052 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42453.996052 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42453.996052 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42453.996052 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 620 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42631.933366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42631.933366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42631.933366 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42631.933366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42631.933366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42631.933366 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 510 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.363636 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 46.363636 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1953 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1953 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1953 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1953 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1953 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1953 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6405 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6405 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6405 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6405 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6405 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6405 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268250499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 268250499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268250499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 268250499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268250499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 268250499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1938 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1938 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1938 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1938 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1938 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1938 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6301 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 6301 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 6301 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 6301 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 6301 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 6301 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 261165999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 261165999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 261165999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 261165999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 261165999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 261165999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41881.420609 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41881.420609 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41881.420609 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41881.420609 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41881.420609 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41881.420609 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41448.341374 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41448.341374 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41448.341374 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41448.341374 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41448.341374 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41448.341374 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 259359 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32631.025486 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1208176 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292097 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.136215 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 259305 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32630.134515 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1207948 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 292043 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.136199 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2513.776004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 69.329948 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30047.919535 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.076714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002116 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.916990 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995820 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2512.609153 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 65.430826 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 30052.094536 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.076679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001997 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.917117 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995793 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32738 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 531 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 533 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5296 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26549 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26539 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999084 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12917948 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12917948 # Number of data accesses -system.cpu.l2cache.Writeback_hits::writebacks 88850 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 88850 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2199 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2199 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3649 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3649 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489731 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 489731 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3649 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491930 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495579 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3649 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491930 # number of overall hits -system.cpu.l2cache.overall_hits::total 495579 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66628 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66628 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2756 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2756 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222754 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222754 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2756 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289382 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292138 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2756 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289382 # number of overall misses -system.cpu.l2cache.overall_misses::total 292138 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5525354500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5525354500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 220303000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 220303000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17928202500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17928202500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 220303000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 23453557000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23673860000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 220303000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 23453557000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23673860000 # number of overall miss cycles -system.cpu.l2cache.Writeback_accesses::writebacks 88850 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 88850 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 68827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 68827 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6405 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6405 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712485 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712485 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6405 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 781312 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 787717 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6405 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 781312 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 787717 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.968050 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.968050 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.430289 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.430289 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312644 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312644 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430289 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370380 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370867 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430289 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370380 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370867 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82928.415981 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82928.415981 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79935.776488 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79935.776488 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80484.312291 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80484.312291 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79935.776488 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81047.048538 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81036.564911 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79935.776488 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81047.048538 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81036.564911 # average overall miss latency +system.cpu.l2cache.tags.tag_accesses 12915272 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12915272 # Number of data accesses +system.cpu.l2cache.Writeback_hits::writebacks 88880 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 88880 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73475.963198 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68739.058477 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68739.058477 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70711.831838 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70711.831838 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68739.058477 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68739.058477 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71348.279854 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71323.990701 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 718889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 885737 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68827 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6405 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712485 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339840 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2357344 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 409856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55690368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56100224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259359 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1828987 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 718745 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 885494 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68805 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68805 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 6301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 712445 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2339654 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2356853 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 403200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55688320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56091520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 259305 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1828608 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.141805 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.348850 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1569628 85.82% 85.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 259359 14.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1569303 85.82% 85.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 259305 14.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1828987 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 873664000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1828608 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 873531500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9606000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 9450000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171968000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1171875499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225509 # Transaction distribution +system.membus.trans_dist::ReadResp 225456 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191067 # Transaction distribution -system.membus.trans_dist::ReadExReq 66628 # Transaction distribution -system.membus.trans_dist::ReadExResp 66628 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225509 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842024 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842024 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22964480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22964480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 191030 # Transaction distribution +system.membus.trans_dist::ReadExReq 66627 # Transaction distribution +system.membus.trans_dist::ReadExResp 66627 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 225456 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 841879 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 841879 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22961024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22961024 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 549887 # Request fanout histogram +system.membus.snoop_fanout::samples 549796 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 549887 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 549796 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 549887 # Request fanout histogram -system.membus.reqLayer0.occupancy 853984000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 549796 # Request fanout histogram +system.membus.reqLayer0.occupancy 880960000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551628500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1551840500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index 588b633d1..82e107e36 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -118,7 +118,7 @@ eventq_index=0 size=64 [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -167,7 +167,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini index c3a686fba..bd7f67190 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -759,7 +759,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout index b094041b5..d77f0dbd5 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 03:24:21 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x2ccb000 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. @@ -648,4 +650,4 @@ info: Increasing stack size by one page. 2000: 2845746745 1000: 2068042552 0: 290958364 -Exiting @ tick 545056655500 because target called exit() +Exiting @ tick 542257602500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index cc0a8b561..53f1e9393 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541068 # Number of seconds simulated -sim_ticks 541067717500 # Number of ticks simulated -final_tick 541067717500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.542258 # Number of seconds simulated +sim_ticks 542257602500 # Number of ticks simulated +final_tick 542257602500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180313 # Simulator instruction rate (inst/s) -host_op_rate 221989 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152283805 # Simulator tick rate (ticks/s) -host_mem_usage 322972 # Number of bytes of host memory used -host_seconds 3553.02 # Real time elapsed on the host +host_inst_rate 121737 # Simulator instruction rate (inst/s) +host_op_rate 149875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 103039759 # Simulator tick rate (ticks/s) +host_mem_usage 317376 # Number of bytes of host memory used +host_seconds 5262.61 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18470272 # Number of bytes read from this memory -system.physmem.bytes_read::total 18635008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164736 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18470528 # Number of bytes read from this memory +system.physmem.bytes_read::total 18635200 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2574 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288598 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288602 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291175 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 304465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34136710 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34441175 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 304465 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 304465 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7818378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7818378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7818378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 304465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34136710 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42259553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291172 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 303679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34062276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34365954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7801222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7801222 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7801222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 303679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34062276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42167176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291175 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291172 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291175 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18613824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21184 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18635008 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18614208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20992 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18635200 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 328 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18282 # Per bank write bursts -system.physmem.perBankRdBursts::1 18127 # Per bank write bursts -system.physmem.perBankRdBursts::2 18214 # Per bank write bursts -system.physmem.perBankRdBursts::3 18173 # Per bank write bursts -system.physmem.perBankRdBursts::4 18274 # Per bank write bursts -system.physmem.perBankRdBursts::5 18402 # Per bank write bursts -system.physmem.perBankRdBursts::6 18180 # Per bank write bursts -system.physmem.perBankRdBursts::7 17989 # Per bank write bursts -system.physmem.perBankRdBursts::8 18022 # Per bank write bursts -system.physmem.perBankRdBursts::9 18061 # Per bank write bursts -system.physmem.perBankRdBursts::10 18102 # Per bank write bursts -system.physmem.perBankRdBursts::11 18198 # Per bank write bursts +system.physmem.perBankRdBursts::1 18134 # Per bank write bursts +system.physmem.perBankRdBursts::2 18219 # Per bank write bursts +system.physmem.perBankRdBursts::3 18172 # Per bank write bursts +system.physmem.perBankRdBursts::4 18271 # Per bank write bursts +system.physmem.perBankRdBursts::5 18399 # Per bank write bursts +system.physmem.perBankRdBursts::6 18176 # Per bank write bursts +system.physmem.perBankRdBursts::7 17991 # Per bank write bursts +system.physmem.perBankRdBursts::8 18028 # Per bank write bursts +system.physmem.perBankRdBursts::9 18057 # Per bank write bursts +system.physmem.perBankRdBursts::10 18104 # Per bank write bursts +system.physmem.perBankRdBursts::11 18195 # Per bank write bursts system.physmem.perBankRdBursts::12 18215 # Per bank write bursts -system.physmem.perBankRdBursts::13 18265 # Per bank write bursts +system.physmem.perBankRdBursts::13 18268 # Per bank write bursts system.physmem.perBankRdBursts::14 18078 # Per bank write bursts -system.physmem.perBankRdBursts::15 18259 # Per bank write bursts +system.physmem.perBankRdBursts::15 18258 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts system.physmem.perBankWrBursts::1 4098 # Per bank write bursts system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4223 # Per bank write bursts -system.physmem.perBankWrBursts::5 4224 # Per bank write bursts +system.physmem.perBankWrBursts::5 4222 # Per bank write bursts system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::7 4092 # Per bank write bursts -system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4096 # Per bank write bursts -system.physmem.perBankWrBursts::12 4095 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::12 4097 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 541067624000 # Total gap between requests +system.physmem.totGap 542257509000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291172 # Read request sizes (log2) +system.physmem.readPktSize::6 291175 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,9 +144,9 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4018 # What write queue length does an incoming req see @@ -158,9 +158,9 @@ system.physmem.wrQLenPdf::25 4018 # Wh system.physmem.wrQLenPdf::26 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4017 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 4017 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see @@ -193,94 +193,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 110882 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 205.996862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.129754 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.860056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45611 41.13% 41.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43911 39.60% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9208 8.30% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1504 1.36% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 772 0.70% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 428 0.39% 91.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 846 0.76% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 594 0.54% 92.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8008 7.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 110882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 111041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 205.695554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.912944 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 256.637901 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 45880 41.32% 41.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43577 39.24% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9434 8.50% 89.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1633 1.47% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 691 0.62% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 667 0.60% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 515 0.46% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 550 0.50% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8094 7.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 111041 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.509335 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.234035 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.719748 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.509833 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.246439 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.588678 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-1023 4015 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4017 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4017 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.446602 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.426400 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.833021 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3120 77.67% 77.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 897 22.33% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.447598 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.427351 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.833980 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3118 77.62% 77.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 0.02% 77.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 897 22.33% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4017 # Writes before turning the bus around for reads -system.physmem.totQLat 3065169000 # Total ticks spent queuing -system.physmem.totMemAccLat 8518437750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10538.99 # Average queueing delay per DRAM burst +system.physmem.totQLat 2871354000 # Total ticks spent queuing +system.physmem.totMemAccLat 8324735250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454235000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9872.39 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29288.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.44 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28622.39 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.33 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 28.63 # Average write queue length when enqueuing -system.physmem.readRowHits 194425 # Number of row buffer hits during reads -system.physmem.writeRowHits 51597 # Number of row buffer hits during writes -system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes -system.physmem.avgGap 1514450.20 # Average gap between requests -system.physmem.pageHitRate 68.93 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 420041160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 229189125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1135976400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215531280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35339834400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 108869403780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 229140586500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375350562645 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.723181 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 380482098250 # Time in different power states -system.physmem_0.memoryStateTime::REF 18067400000 # Time in different power states +system.physmem.avgWrQLen 26.15 # Average write queue length when enqueuing +system.physmem.readRowHits 194229 # Number of row buffer hits during reads +system.physmem.writeRowHits 51633 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.78 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.12 # Row buffer hit rate for writes +system.physmem.avgGap 1517767.95 # Average gap between requests +system.physmem.pageHitRate 68.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 420124320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 229234500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1135836000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215518320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 107502461415 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 231049769250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 375970079325 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.351550 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 383670371250 # Time in different power states +system.physmem_0.memoryStateTime::REF 18106920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 142518050750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 140473012000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 418226760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 228199125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1132497600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212576400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35339834400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 107776907010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 230098917000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 375207158295 # Total energy per rank (pJ) -system.physmem_1.averagePower 693.458141 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 382081982750 # Time in different power states -system.physmem_1.memoryStateTime::REF 18067400000 # Time in different power states +system.physmem_1.actEnergy 419247360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 228756000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1132271400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212615280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35417135520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 108055650690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 230564511000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 376030187250 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.462409 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 382864555750 # Time in different power states +system.physmem_1.memoryStateTime::REF 18106920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 140917403500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 141281958750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 157565509 # Number of BP lookups -system.cpu.branchPred.condPredicted 107229273 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12892751 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 98103751 # Number of BTB lookups -system.cpu.branchPred.BTBHits 81778311 # Number of BTB hits +system.cpu.branchPred.lookups 154805772 # Number of BP lookups +system.cpu.branchPred.condPredicted 105138293 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12875884 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90693369 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83089320 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.359005 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19318729 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1315 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.615651 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19277594 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -399,99 +401,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1082135435 # number of cpu cycles simulated +system.cpu.numCycles 1084515205 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 23942424 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 23906785 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.689108 # CPI: cycles per instruction -system.cpu.ipc 0.592029 # IPC: instructions per cycle -system.cpu.tickCycles 1024380125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57755310 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778330 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.458630 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378454621 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782426 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.693820 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 795587500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.458630 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999135 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999135 # Average percentage of cache occupancy +system.cpu.cpi 1.692822 # CPI: cycles per instruction +system.cpu.ipc 0.590729 # IPC: instructions per cycle +system.cpu.tickCycles 1025899032 # Number of cycles that the object actually ticked +system.cpu.idleCycles 58616173 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778339 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.484062 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378456435 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782435 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.690575 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 792553500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.484062 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999142 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999142 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1346 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1586 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1585 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759395078 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759395078 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249625893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249625893 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 759398763 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759398763 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249627706 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249627706 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3485 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3486 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3486 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378439658 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378439658 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378443143 # number of overall hits -system.cpu.dcache.overall_hits::total 378443143 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713852 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713852 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 378441471 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378441471 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378444957 # number of overall hits +system.cpu.dcache.overall_hits::total 378444957 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713876 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713876 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 851564 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851564 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851705 # number of overall misses -system.cpu.dcache.overall_misses::total 851705 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24973506500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24973506500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10064105500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10064105500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35037612000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35037612000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35037612000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35037612000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250339745 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250339745 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 851588 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851588 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851729 # number of overall misses +system.cpu.dcache.overall_misses::total 851729 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24762813000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24762813000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10105718500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10105718500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34868531500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34868531500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34868531500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34868531500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250341582 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250341582 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3626 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3627 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3627 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379291222 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379291222 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379294848 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379294848 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379293059 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379293059 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379296686 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379296686 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002852 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002852 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038886 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.038886 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038875 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.038875 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34984.151477 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34984.151477 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73080.817213 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73080.817213 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41145.013176 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41145.013176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41138.201607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41138.201607 # average overall miss latency +system.cpu.dcache.overall_miss_rate::cpu.data 0.002246 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002246 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34687.835142 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34687.835142 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73382.991315 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73382.991315 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40945.306298 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40945.306298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40938.527982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40938.527982 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,109 +502,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 88940 # number of writebacks -system.cpu.dcache.writebacks::total 88940 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 887 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 887 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 88920 # number of writebacks +system.cpu.dcache.writebacks::total 88920 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 902 # number of ReadReq MSHR hits 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69292 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69292 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712974 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712974 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782287 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782287 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782426 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782426 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24245308500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24245308500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5047418500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5047418500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29292727000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29292727000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29294515000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29294515000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 782296 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782296 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782435 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782435 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24034165000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24034165000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5067912500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5067912500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1855000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1855000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29102077500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29102077500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29103932500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29103932500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038334 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038334 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038324 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038324 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34006.309566 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34006.309566 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72811.207120 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72811.207120 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37444.987581 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37444.987581 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37440.620583 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37440.620583 # average overall mshr miss latency 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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 37196.613776 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 23593 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.048816 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 288484492 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25344 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11382.752999 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23591 # number of replacements +system.cpu.icache.tags.tagsinuse 1713.095623 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 291576498 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25342 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11505.662458 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.048816 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835961 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1713.095623 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836472 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836472 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1603 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 577045018 # Number of tag accesses -system.cpu.icache.tags.data_accesses 577045018 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 288484492 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 288484492 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 288484492 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 288484492 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 288484492 # number of overall hits -system.cpu.icache.overall_hits::total 288484492 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25345 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25345 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25345 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25345 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25345 # number of overall misses -system.cpu.icache.overall_misses::total 25345 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 499936000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 499936000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 499936000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 499936000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 499936000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 499936000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 288509837 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 288509837 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 288509837 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 288509837 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 288509837 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 288509837 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000088 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000088 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000088 # miss rate for demand accesses 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291601841 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19654.263505 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19654.263505 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19654.263505 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19654.263505 # average overall miss latency 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(read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 25345 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 25345 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 25345 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 474592000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 474592000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 474592000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 474592000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 474592000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 474592000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000088 # mshr miss rate for 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system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 369 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 369 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 376 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 376 # number of CleanEvict MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2575 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2575 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222507 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222507 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2575 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288598 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2575 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288598 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4248598000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4248598000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 171535500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 171535500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15799227000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15799227000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171535500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20047825000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20219360500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171535500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20047825000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20219360500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2574 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2574 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222511 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222511 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288602 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288602 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291176 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4269091500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4269091500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169723000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169723000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15588307500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15588307500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169723000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19857399000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20027122000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169723000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19857399000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20027122000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101598 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312026 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312026 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368850 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101567 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312028 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312028 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.360465 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101598 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368850 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101567 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368851 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.360465 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64284.062883 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64284.062883 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66615.728155 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66615.728155 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71005.527916 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71005.527916 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66615.728155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69466.264492 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69441.055661 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66615.728155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69466.264492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69441.055661 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64594.142924 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64594.142924 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65937.451437 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65937.451437 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70056.345529 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70056.345529 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65937.451437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68805.479519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68780.126109 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 738448 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 155038 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 901935 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 155018 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 901956 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 25345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 713104 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72953 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2414122 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55767424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57389440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258392 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1868086 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 25343 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 713113 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2414134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55766720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57388608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258395 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1868103 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1.138319 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.345235 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1609694 86.17% 86.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 258392 13.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1609708 86.17% 86.17% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 258395 13.83% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1868086 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 893787000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1868103 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 893774000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38017996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38014996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1173652972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1173666472 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 225081 # Transaction distribution +system.membus.trans_dist::ReadResp 225084 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190637 # Transaction distribution +system.membus.trans_dist::CleanEvict 190644 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225081 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839079 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839079 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22865280 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22865280 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225084 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839092 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839092 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22865472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22865472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 547907 # Request fanout histogram +system.membus.snoop_fanout::samples 547917 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 547907 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 547917 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 547907 # Request fanout histogram -system.membus.reqLayer0.occupancy 916769500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 547917 # Request fanout histogram +system.membus.reqLayer0.occupancy 917948500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1554235250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1554418250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 2898b2e51..d3d29952c 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -688,7 +688,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/perlbmk +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index fc759c123..261f6c290 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -156,7 +156,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -266,7 +266,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini index 75824f793..a6321b5a0 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini @@ -125,7 +125,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -548,7 +548,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -597,7 +597,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr index de77515a1..f0a9a7c93 100644..100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout index bfc5e794b..9dd4d1ffb 100644..100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout @@ -3,11 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:41:53 -gem5 started May 7 2014 11:01:25 -gem5 executing on cz3212c2d7 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 21:22:43 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 58222132000 because target called exit() +Exiting @ tick 59549031000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index dfd14c576..c8b76a216 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.059580 # Number of seconds simulated -sim_ticks 59579614000 # Number of ticks simulated -final_tick 59579614000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059549 # Number of seconds simulated +sim_ticks 59549031000 # Number of ticks simulated +final_tick 59549031000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 321432 # Simulator instruction rate (inst/s) -host_op_rate 321432 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216544599 # Simulator tick rate (ticks/s) -host_mem_usage 304972 # Number of bytes of host memory used -host_seconds 275.14 # Real time elapsed on the host +host_inst_rate 231283 # Simulator instruction rate (inst/s) +host_op_rate 231283 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 155732739 # Simulator tick rate (ticks/s) +host_mem_usage 299636 # Number of bytes of host memory used +host_seconds 382.38 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 500672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10147648 # Number of bytes read from this memory -system.physmem.bytes_read::total 10648320 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 500672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 500672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7320576 # Number of bytes written to this memory -system.physmem.bytes_written::total 7320576 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7823 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158557 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166380 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114384 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114384 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8403411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 170320808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 178724219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8403411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8403411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 122870484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 122870484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 122870484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8403411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 170320808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 301594703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166380 # Number of read requests accepted -system.physmem.writeReqs 114384 # Number of write requests accepted -system.physmem.readBursts 166380 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114384 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10648064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 256 # Total number of bytes read from write queue -system.physmem.bytesWritten 7319040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10648320 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7320576 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 4 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 500352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10147264 # Number of bytes read from this memory +system.physmem.bytes_read::total 10647616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 500352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 500352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7320640 # Number of bytes written to this memory +system.physmem.bytes_written::total 7320640 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7818 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158551 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166369 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114385 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114385 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8402353 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 170401832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178804186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8402353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8402353 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122934662 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122934662 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122934662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8402353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 170401832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 301738848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166369 # Number of read requests accepted +system.physmem.writeReqs 114385 # Number of write requests accepted +system.physmem.readBursts 166369 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114385 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10647296 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 7318592 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10647616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7320640 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10451 # Per bank write bursts +system.physmem.perBankRdBursts::0 10447 # Per bank write bursts system.physmem.perBankRdBursts::1 10506 # Per bank write bursts -system.physmem.perBankRdBursts::2 10284 # Per bank write bursts -system.physmem.perBankRdBursts::3 10088 # Per bank write bursts -system.physmem.perBankRdBursts::4 10415 # Per bank write bursts -system.physmem.perBankRdBursts::5 10418 # Per bank write bursts +system.physmem.perBankRdBursts::2 10283 # Per bank write bursts +system.physmem.perBankRdBursts::3 10092 # Per bank write bursts +system.physmem.perBankRdBursts::4 10413 # Per bank write bursts +system.physmem.perBankRdBursts::5 10414 # Per bank write bursts system.physmem.perBankRdBursts::6 9828 # Per bank write bursts -system.physmem.perBankRdBursts::7 10277 # Per bank write bursts +system.physmem.perBankRdBursts::7 10274 # Per bank write bursts system.physmem.perBankRdBursts::8 10580 # Per bank write bursts system.physmem.perBankRdBursts::9 10645 # Per bank write bursts -system.physmem.perBankRdBursts::10 10557 # Per bank write bursts -system.physmem.perBankRdBursts::11 10259 # Per bank write bursts -system.physmem.perBankRdBursts::12 10298 # Per bank write bursts -system.physmem.perBankRdBursts::13 10623 # Per bank write bursts -system.physmem.perBankRdBursts::14 10516 # Per bank write bursts -system.physmem.perBankRdBursts::15 10631 # Per bank write bursts +system.physmem.perBankRdBursts::10 10558 # Per bank write bursts +system.physmem.perBankRdBursts::11 10261 # Per bank write bursts +system.physmem.perBankRdBursts::12 10296 # Per bank write bursts +system.physmem.perBankRdBursts::13 10620 # Per bank write bursts +system.physmem.perBankRdBursts::14 10515 # Per bank write bursts +system.physmem.perBankRdBursts::15 10632 # Per bank write bursts system.physmem.perBankWrBursts::0 7162 # Per bank write bursts -system.physmem.perBankWrBursts::1 7274 # Per bank write bursts +system.physmem.perBankWrBursts::1 7273 # Per bank write bursts system.physmem.perBankWrBursts::2 7295 # Per bank write bursts -system.physmem.perBankWrBursts::3 6999 # Per bank write bursts +system.physmem.perBankWrBursts::3 7000 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7182 # Per bank write bursts -system.physmem.perBankWrBursts::6 6834 # Per bank write bursts -system.physmem.perBankWrBursts::7 7095 # Per bank write bursts -system.physmem.perBankWrBursts::8 7222 # Per bank write bursts +system.physmem.perBankWrBursts::5 7181 # Per bank write bursts +system.physmem.perBankWrBursts::6 6833 # Per bank write bursts +system.physmem.perBankWrBursts::7 7084 # Per bank write bursts +system.physmem.perBankWrBursts::8 7224 # Per bank write bursts system.physmem.perBankWrBursts::9 6994 # Per bank write bursts -system.physmem.perBankWrBursts::10 7111 # Per bank write bursts -system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6990 # Per bank write bursts -system.physmem.perBankWrBursts::13 7296 # Per bank write bursts -system.physmem.perBankWrBursts::14 7306 # Per bank write bursts +system.physmem.perBankWrBursts::10 7113 # Per bank write bursts +system.physmem.perBankWrBursts::11 6992 # Per bank write bursts +system.physmem.perBankWrBursts::12 6991 # Per bank write bursts +system.physmem.perBankWrBursts::13 7295 # Per bank write bursts +system.physmem.perBankWrBursts::14 7307 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 59579590000 # Total gap between requests +system.physmem.totGap 59549007000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166380 # Read request sizes (log2) +system.physmem.readPktSize::6 166369 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114384 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164758 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1592 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114385 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1588 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,26 +144,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -193,122 +193,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.220838 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 195.100573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.685535 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19472 35.57% 35.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11861 21.67% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5645 10.31% 67.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 54768 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.014023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.067660 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.383666 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19491 35.59% 35.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11850 21.64% 57.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5663 10.34% 67.57% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 3680 6.72% 74.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2860 5.22% 79.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2018 3.69% 83.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1694 3.09% 86.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1489 2.72% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6018 10.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54737 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7040 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.631676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.376134 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7037 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::512-639 2902 5.30% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2048 3.74% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1635 2.99% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1469 2.68% 88.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6030 11.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54768 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7038 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.634839 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 336.413145 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7035 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7040 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7040 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.244318 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.229045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.737232 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6278 89.18% 89.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 16 0.23% 89.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 578 8.21% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 145 2.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 15 0.21% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 7038 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7038 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.247940 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.232365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.745442 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6264 89.00% 89.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 17 0.24% 89.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 601 8.54% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 122 1.73% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 23 0.33% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 6 0.09% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7040 # Writes before turning the bus around for reads -system.physmem.totQLat 2004219750 # Total ticks spent queuing -system.physmem.totMemAccLat 5123769750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 831880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12046.33 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7038 # Writes before turning the bus around for reads +system.physmem.totQLat 2001235750 # Total ticks spent queuing +system.physmem.totMemAccLat 5120560750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 831820000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12029.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30796.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 178.72 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 122.84 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 178.72 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 122.87 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30779.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.80 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.36 # Data bus utilization in percentage system.physmem.busUtilRead 1.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.96 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing -system.physmem.readRowHits 144447 # Number of row buffer hits during reads -system.physmem.writeRowHits 81540 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.29 # Row buffer hit rate for writes -system.physmem.avgGap 212205.23 # Average gap between requests -system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199372320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108784500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 641464200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368938800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3890992560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12501731340 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24777284250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 42488567970 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.220229 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 41071172000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1989260000 # Time in different power states +system.physmem.avgWrQLen 24.01 # Average write queue length when enqueuing +system.physmem.readRowHits 144462 # Number of row buffer hits during reads +system.physmem.writeRowHits 81475 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes +system.physmem.avgGap 212103.86 # Average gap between requests +system.physmem.pageHitRate 80.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199614240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108916500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 641355000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 368899920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3888958320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12587581890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24683289750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42478615620 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.426150 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40913813750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1988220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16512675000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16639693750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 214189920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116869500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 655792800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371790000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3890992560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13114227690 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24240006750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 42603869220 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.155695 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40171909250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1989260000 # Time in different power states +system.physmem_1.actEnergy 214137000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116840625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 655777200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371764080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3888958320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13157757450 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24183135750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42588370425 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.269477 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40075806250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1988220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17411703250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17478332750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14668515 # Number of BP lookups -system.cpu.branchPred.condPredicted 9490335 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 391198 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9984003 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6387554 # Number of BTB hits +system.cpu.branchPred.lookups 14666095 # Number of BP lookups +system.cpu.branchPred.condPredicted 9488989 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 386100 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9897774 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6385513 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 63.977885 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1708558 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85259 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 64.514637 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1708089 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 84886 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20570256 # DTB read hits -system.cpu.dtb.read_misses 97321 # DTB read misses +system.cpu.dtb.read_hits 20569916 # DTB read hits +system.cpu.dtb.read_misses 97322 # DTB read misses system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20667577 # DTB read accesses -system.cpu.dtb.write_hits 14665734 # DTB write hits -system.cpu.dtb.write_misses 9406 # DTB write misses +system.cpu.dtb.read_accesses 20667238 # DTB read accesses +system.cpu.dtb.write_hits 14665322 # DTB write hits +system.cpu.dtb.write_misses 9407 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675140 # DTB write accesses -system.cpu.dtb.data_hits 35235990 # DTB hits -system.cpu.dtb.data_misses 106727 # DTB misses +system.cpu.dtb.write_accesses 14674729 # DTB write accesses +system.cpu.dtb.data_hits 35235238 # DTB hits +system.cpu.dtb.data_misses 106729 # DTB misses system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35342717 # DTB accesses -system.cpu.itb.fetch_hits 25623202 # ITB hits -system.cpu.itb.fetch_misses 5252 # ITB misses +system.cpu.dtb.data_accesses 35341967 # DTB accesses +system.cpu.itb.fetch_hits 25606453 # ITB hits +system.cpu.itb.fetch_misses 5227 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25628454 # ITB accesses +system.cpu.itb.fetch_accesses 25611680 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -322,81 +322,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 119159228 # number of cpu cycles simulated +system.cpu.numCycles 119098062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1111760 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1106110 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.347375 # CPI: cycles per instruction -system.cpu.ipc 0.742184 # IPC: instructions per cycle -system.cpu.tickCycles 91522395 # Number of cycles that the object actually ticked -system.cpu.idleCycles 27636833 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200775 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.716592 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616548 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204871 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.967536 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 688117500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.716592 # Average occupied blocks per requestor +system.cpu.cpi 1.346683 # CPI: cycles per instruction +system.cpu.ipc 0.742565 # IPC: instructions per cycle +system.cpu.tickCycles 91473495 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27624567 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200766 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.715334 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34616231 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204862 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.973411 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 687575500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.715334 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993827 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993827 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 687 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 686 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3360 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70177059 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70177059 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20283298 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20283298 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333250 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333250 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616548 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616548 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616548 # number of overall hits -system.cpu.dcache.overall_hits::total 34616548 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89419 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89419 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280127 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280127 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369546 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369546 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369546 # number of overall misses -system.cpu.dcache.overall_misses::total 369546 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4766015000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4766015000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21725113500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21725113500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26491128500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26491128500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26491128500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26491128500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372717 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372717 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70176386 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70176386 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20282965 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20282965 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333266 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333266 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34616231 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34616231 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34616231 # number of overall hits +system.cpu.dcache.overall_hits::total 34616231 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89420 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89420 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280111 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280111 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369531 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369531 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369531 # number of overall misses +system.cpu.dcache.overall_misses::total 369531 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4765724000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4765724000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21723340000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21723340000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26489064000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26489064000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26489064000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26489064000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372385 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372385 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34986094 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34986094 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34986094 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34986094 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34985762 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985762 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34985762 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985762 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004389 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004389 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019169 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019169 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53299.802055 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53299.802055 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77554.514559 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 77554.514559 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71685.604769 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71685.604769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71685.604769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71685.604769 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010562 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010562 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010562 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010562 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53295.951689 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53295.951689 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77552.613071 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77552.613071 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71682.927819 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71682.927819 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71682.927819 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71682.927819 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,32 +405,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168451 # number of writebacks -system.cpu.dcache.writebacks::total 168451 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28112 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28112 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136563 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136563 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164675 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164675 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164675 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164675 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61307 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61307 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143564 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143564 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204871 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204871 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204871 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204871 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2678080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2678080000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10985374000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10985374000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13663454000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13663454000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13663454000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13663454000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168453 # number of writebacks +system.cpu.dcache.writebacks::total 168453 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28115 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28115 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136554 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136554 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1043 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1041 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 798 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51401891 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51401891 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25467714 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25467714 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25467714 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25467714 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25467714 # 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number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -510,129 +510,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155488 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155488 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155488 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155488 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155488 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155488 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2403192500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2403192500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2403192500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2403192500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2403192500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2403192500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006068 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006068 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006068 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006068 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15455.806879 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15455.806879 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15455.806879 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15455.806879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15455.806879 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15455.806879 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 154900 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 154900 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 154900 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 154900 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 154900 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 154900 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2396064000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2396064000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2396064000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2396064000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2396064000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2396064000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006049 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006049 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006049 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006049 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15468.457069 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15468.457069 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15468.457069 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15468.457069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15468.457069 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15468.457069 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132455 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30425.611503 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 404125 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164531 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.456224 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132445 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30425.579826 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 402950 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164521 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.449231 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11280175000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11821288500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911657 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911657 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.050319 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451424 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451424 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773936 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.461709 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.050319 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773936 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.461709 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71270.247246 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71270.247246 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69170.373211 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69170.373211 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70669.629630 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70669.629630 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69170.373211 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71165.413700 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71071.597718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69170.373211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71165.413700 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71071.597718 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.050478 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.451341 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451341 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773941 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.462445 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.050478 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773941 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.462445 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71241.748292 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71241.748292 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69204.949482 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69204.949482 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70689.670751 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70689.670751 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69204.949482 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69204.949482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71145.404318 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71054.207489 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 216793 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 282835 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 203834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143565 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 155488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61306 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1074931 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9951168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23892608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33843776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132455 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 847028 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.156376 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.363212 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 216203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 282838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 203224 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 154900 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61304 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 462650 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1073140 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9913536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23892160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33805696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132445 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 845824 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.156587 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.363411 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 714573 84.36% 84.36% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 132455 15.64% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 713379 84.34% 84.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 132445 15.66% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 847028 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 525737500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 845824 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 525142500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 233232496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 232349997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307309993 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 307296493 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 35498 # Transaction distribution -system.membus.trans_dist::Writeback 114384 # Transaction distribution -system.membus.trans_dist::CleanEvict 16134 # Transaction distribution +system.membus.trans_dist::ReadResp 35487 # Transaction distribution +system.membus.trans_dist::Writeback 114385 # Transaction distribution +system.membus.trans_dist::CleanEvict 16125 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35498 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463278 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 463278 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17968896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17968896 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 35487 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 463248 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17968256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17968256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 296898 # Request fanout histogram +system.membus.snoop_fanout::samples 296879 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 296898 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 296879 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 296898 # Request fanout histogram -system.membus.reqLayer0.occupancy 824886500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 296879 # Request fanout histogram +system.membus.reqLayer0.occupancy 824874000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 878487500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 878418750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 7662c92f8..3a9ebdb7f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -150,7 +150,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -497,7 +497,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -546,7 +546,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -609,7 +609,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 2061356b3..92f71955f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022637 # Number of seconds simulated -sim_ticks 22637068500 # Number of ticks simulated -final_tick 22637068500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022357 # Number of seconds simulated +sim_ticks 22356634500 # Number of ticks simulated +final_tick 22356634500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 222882 # Simulator instruction rate (inst/s) -host_op_rate 222882 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63391012 # Simulator tick rate (ticks/s) -host_mem_usage 306268 # Number of bytes of host memory used -host_seconds 357.10 # Real time elapsed on the host +host_inst_rate 154709 # Simulator instruction rate (inst/s) +host_op_rate 154709 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43456447 # Simulator tick rate (ticks/s) +host_mem_usage 300660 # Number of bytes of host memory used +host_seconds 514.46 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 472384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10153088 # Number of bytes read from this memory -system.physmem.bytes_read::total 10625472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 472384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 472384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7318784 # Number of bytes written to this memory -system.physmem.bytes_written::total 7318784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7381 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158642 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166023 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114356 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114356 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20867720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 448516026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 469383746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20867720 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20867720 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 323309708 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 323309708 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 323309708 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20867720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 448516026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 792693453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166023 # Number of read requests accepted -system.physmem.writeReqs 114356 # Number of write requests accepted -system.physmem.readBursts 166023 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114356 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10625216 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 256 # Total number of bytes read from write queue -system.physmem.bytesWritten 7317504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10625472 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7318784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 4 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 471552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10150720 # Number of bytes read from this memory +system.physmem.bytes_read::total 10622272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 471552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 471552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7318272 # Number of bytes written to this memory +system.physmem.bytes_written::total 7318272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158605 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165973 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114348 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114348 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21092262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 454036139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 475128401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21092262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21092262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 327342293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 327342293 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 327342293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21092262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 454036139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 802470694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165973 # Number of read requests accepted +system.physmem.writeReqs 114348 # Number of write requests accepted +system.physmem.readBursts 165973 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114348 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10621952 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue +system.physmem.bytesWritten 7316672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10622272 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7318272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10427 # Per bank write bursts -system.physmem.perBankRdBursts::1 10469 # Per bank write bursts +system.physmem.perBankRdBursts::0 10420 # Per bank write bursts +system.physmem.perBankRdBursts::1 10451 # Per bank write bursts system.physmem.perBankRdBursts::2 10285 # Per bank write bursts -system.physmem.perBankRdBursts::3 10058 # Per bank write bursts -system.physmem.perBankRdBursts::4 10410 # Per bank write bursts -system.physmem.perBankRdBursts::5 10383 # Per bank write bursts -system.physmem.perBankRdBursts::6 9823 # Per bank write bursts -system.physmem.perBankRdBursts::7 10285 # Per bank write bursts -system.physmem.perBankRdBursts::8 10562 # Per bank write bursts -system.physmem.perBankRdBursts::9 10635 # Per bank write bursts -system.physmem.perBankRdBursts::10 10512 # Per bank write bursts -system.physmem.perBankRdBursts::11 10227 # Per bank write bursts -system.physmem.perBankRdBursts::12 10266 # Per bank write bursts -system.physmem.perBankRdBursts::13 10590 # Per bank write bursts +system.physmem.perBankRdBursts::3 10056 # Per bank write bursts +system.physmem.perBankRdBursts::4 10402 # Per bank write bursts +system.physmem.perBankRdBursts::5 10375 # Per bank write bursts +system.physmem.perBankRdBursts::6 9822 # Per bank write bursts +system.physmem.perBankRdBursts::7 10280 # Per bank write bursts +system.physmem.perBankRdBursts::8 10559 # Per bank write bursts +system.physmem.perBankRdBursts::9 10640 # Per bank write bursts +system.physmem.perBankRdBursts::10 10517 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10263 # Per bank write bursts +system.physmem.perBankRdBursts::13 10582 # Per bank write bursts system.physmem.perBankRdBursts::14 10475 # Per bank write bursts -system.physmem.perBankRdBursts::15 10612 # Per bank write bursts +system.physmem.perBankRdBursts::15 10613 # Per bank write bursts system.physmem.perBankWrBursts::0 7161 # Per bank write bursts -system.physmem.perBankWrBursts::1 7270 # Per bank write bursts +system.physmem.perBankWrBursts::1 7267 # Per bank write bursts system.physmem.perBankWrBursts::2 7294 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 7175 # Per bank write bursts +system.physmem.perBankWrBursts::5 7171 # Per bank write bursts system.physmem.perBankWrBursts::6 6835 # Per bank write bursts system.physmem.perBankWrBursts::7 7095 # Per bank write bursts -system.physmem.perBankWrBursts::8 7221 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts system.physmem.perBankWrBursts::9 6995 # Per bank write bursts -system.physmem.perBankWrBursts::10 7100 # Per bank write bursts -system.physmem.perBankWrBursts::11 6989 # Per bank write bursts -system.physmem.perBankWrBursts::12 6993 # Per bank write bursts -system.physmem.perBankWrBursts::13 7294 # Per bank write bursts +system.physmem.perBankWrBursts::10 7101 # Per bank write bursts +system.physmem.perBankWrBursts::11 6988 # Per bank write bursts +system.physmem.perBankWrBursts::12 6991 # Per bank write bursts +system.physmem.perBankWrBursts::13 7292 # Per bank write bursts system.physmem.perBankWrBursts::14 7307 # Per bank write bursts system.physmem.perBankWrBursts::15 7482 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22637037500 # Total gap between requests +system.physmem.totGap 22356603500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166023 # Read request sizes (log2) +system.physmem.readPktSize::6 165973 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114356 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 52265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 42988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 32235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114348 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 52267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43039 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38487 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 835 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,123 +193,125 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.050573 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.162039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.313279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18282 34.96% 34.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10576 20.22% 55.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5922 11.32% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2988 5.71% 72.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3062 5.85% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1483 2.84% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1989 3.80% 84.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1021 1.95% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6978 13.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52301 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6994 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.736917 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.159441 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6991 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.051408 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.164629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.365120 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18284 34.97% 34.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10551 20.18% 55.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5984 11.44% 66.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2964 5.67% 72.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2982 5.70% 77.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1592 3.04% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1956 3.74% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 963 1.84% 86.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7012 13.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52288 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6989 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.745743 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 338.273336 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6986 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6994 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6994 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.347727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.319415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.025091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6123 87.55% 87.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 26 0.37% 87.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 468 6.69% 94.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 194 2.77% 97.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 92 1.32% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 55 0.79% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 18 0.26% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.14% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.09% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6994 # Writes before turning the bus around for reads -system.physmem.totQLat 5783499750 # Total ticks spent queuing -system.physmem.totMemAccLat 8896356000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 830095000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34836.37 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6989 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6989 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.357562 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.328073 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.050353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6097 87.24% 87.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.43% 87.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 474 6.78% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 201 2.88% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 97 1.39% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 49 0.70% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 24 0.34% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 8 0.11% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6989 # Writes before turning the bus around for reads +system.physmem.totQLat 5746744750 # Total ticks spent queuing +system.physmem.totMemAccLat 8858644750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 829840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34625.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53586.37 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 469.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 323.25 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 469.38 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 323.31 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53375.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 475.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 327.27 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 475.13 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 327.34 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.19 # Data bus utilization in percentage -system.physmem.busUtilRead 3.67 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.53 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 145949 # Number of row buffer hits during reads -system.physmem.writeRowHits 82096 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.91 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes -system.physmem.avgGap 80737.28 # Average gap between requests -system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190852200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 104135625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 640543800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 368925840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1478383920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6748287570 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7661408250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 17192537205 # Total energy per rank (pJ) -system.physmem_0.averagePower 759.557739 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12661521500 # Time in different power states -system.physmem_0.memoryStateTime::REF 755820000 # Time in different power states +system.physmem.busUtil 6.27 # Data bus utilization in percentage +system.physmem.busUtilRead 3.71 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.93 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing +system.physmem.readRowHits 145973 # Number of row buffer hits during reads +system.physmem.writeRowHits 82020 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.73 # Row buffer hit rate for writes +system.physmem.avgGap 79753.58 # Average gap between requests +system.physmem.pageHitRate 81.33 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190882440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 104152125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 640161600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 368899920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6647542920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7581572250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 16993287015 # Total energy per rank (pJ) +system.physmem_0.averagePower 760.170138 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12528806000 # Time in different power states +system.physmem_0.memoryStateTime::REF 746460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9217738000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9079331500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204354360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111502875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654108000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371764080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1478383920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6845140260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7576424250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 17241677745 # Total energy per rank (pJ) -system.physmem_1.averagePower 761.730174 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12521267250 # Time in different power states -system.physmem_1.memoryStateTime::REF 755820000 # Time in different power states +system.physmem_1.actEnergy 204271200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111457500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654100200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371699280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1460075760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6857633520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7397282250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 17056519710 # Total energy per rank (pJ) +system.physmem_1.averagePower 762.998761 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12224344750 # Time in different power states +system.physmem_1.memoryStateTime::REF 746460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9357815250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9383970250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16666171 # Number of BP lookups -system.cpu.branchPred.condPredicted 10777513 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 373740 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11097684 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7405754 # Number of BTB hits +system.cpu.branchPred.lookups 16500558 # Number of BP lookups +system.cpu.branchPred.condPredicted 10689411 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 329507 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9043813 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7288978 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.732428 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1996658 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2898 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.596293 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1974529 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2931 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22620977 # DTB read hits -system.cpu.dtb.read_misses 226849 # DTB read misses -system.cpu.dtb.read_acv 27 # DTB read access violations -system.cpu.dtb.read_accesses 22847826 # DTB read accesses -system.cpu.dtb.write_hits 15870488 # DTB write hits -system.cpu.dtb.write_misses 45057 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 15915545 # DTB write accesses -system.cpu.dtb.data_hits 38491465 # DTB hits -system.cpu.dtb.data_misses 271906 # DTB misses -system.cpu.dtb.data_acv 31 # DTB access violations -system.cpu.dtb.data_accesses 38763371 # DTB accesses -system.cpu.itb.fetch_hits 13971550 # ITB hits -system.cpu.itb.fetch_misses 35700 # ITB misses +system.cpu.dtb.read_hits 22520885 # DTB read hits +system.cpu.dtb.read_misses 225850 # DTB read misses +system.cpu.dtb.read_acv 12 # DTB read access violations +system.cpu.dtb.read_accesses 22746735 # DTB read accesses +system.cpu.dtb.write_hits 15825785 # DTB write hits +system.cpu.dtb.write_misses 44675 # DTB write misses +system.cpu.dtb.write_acv 5 # DTB write access violations +system.cpu.dtb.write_accesses 15870460 # DTB write accesses +system.cpu.dtb.data_hits 38346670 # DTB hits +system.cpu.dtb.data_misses 270525 # DTB misses +system.cpu.dtb.data_acv 17 # DTB access violations +system.cpu.dtb.data_accesses 38617195 # DTB accesses +system.cpu.itb.fetch_hits 13761847 # ITB hits +system.cpu.itb.fetch_misses 29330 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14007250 # ITB accesses +system.cpu.itb.fetch_accesses 13791177 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -323,100 +325,100 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 45274140 # number of cpu cycles simulated +system.cpu.numCycles 44713274 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15840684 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106412182 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16666171 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9402412 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27820247 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 987192 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 787 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5202 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 343767 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13971550 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 209132 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 15584768 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105191572 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16500558 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9263507 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27593237 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 896542 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 162 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 4764 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 325871 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13761847 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 191924 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 44504386 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.391049 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.126296 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 43957183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.393046 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.127676 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24724412 55.56% 55.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1545163 3.47% 59.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1406842 3.16% 62.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1520478 3.42% 65.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4242713 9.53% 75.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1851895 4.16% 79.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 685374 1.54% 80.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070742 2.41% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7456767 16.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24416716 55.55% 55.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1522401 3.46% 59.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1379227 3.14% 62.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1505485 3.42% 65.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4199085 9.55% 75.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1828470 4.16% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 669319 1.52% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1052182 2.39% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7384298 16.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44504386 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.368117 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.350397 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15190182 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9797968 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18517517 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 603822 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 394897 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3753615 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100898 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104278713 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 316536 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 394897 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15562376 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4515044 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 96153 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18732590 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5203326 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103086111 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6702 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 93508 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 341438 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4700364 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 62061981 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124384146 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 124055114 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 329031 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43957183 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369030 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.352580 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14931500 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9767964 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18310970 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 595597 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 351152 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3708003 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 98860 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103215952 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 311866 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 351152 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15279451 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4431592 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96231 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18542963 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5255794 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102192828 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5698 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 95463 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 341437 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4753642 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61435412 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123253139 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 122935807 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 317331 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9515100 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5718 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2349661 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23316234 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16465365 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1246740 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 545757 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91441079 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5553 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89167924 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 83024 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11854875 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4801848 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 970 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44504386 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.003576 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.243462 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 8888531 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5692 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5745 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2361848 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23156457 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16385404 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1258348 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 502815 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90834629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5552 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88691609 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70456 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11248424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4497706 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 969 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43957183 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.017682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.245665 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17850579 40.11% 40.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5788896 13.01% 53.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5155949 11.59% 64.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4393297 9.87% 74.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4359248 9.80% 84.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2645472 5.94% 90.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1941559 4.36% 94.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1381555 3.10% 97.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 987831 2.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17476881 39.76% 39.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5730177 13.04% 52.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5107740 11.62% 64.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4380373 9.97% 74.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4328154 9.85% 84.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2635103 5.99% 90.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1947598 4.43% 94.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1378142 3.14% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 973015 2.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44504386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43957183 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 244058 9.64% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 243362 9.64% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available @@ -445,118 +447,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1174802 46.40% 56.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112961 43.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1165216 46.16% 55.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1115524 44.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49705550 55.74% 55.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44198 0.05% 55.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.79% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121960 0.14% 55.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121539 0.14% 56.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39076 0.04% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23058691 25.86% 81.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16076765 18.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49430492 55.73% 55.73% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43978 0.05% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121147 0.14% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 120628 0.14% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39084 0.04% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22917985 25.84% 81.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16018139 18.06% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89167924 # Type of FU issued -system.cpu.iq.rate 1.969511 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2531821 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028394 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224839378 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102887543 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87218101 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 615701 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 435266 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 300894 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91391726 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 308019 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1669932 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88691609 # Type of FU issued +system.cpu.iq.rate 1.983563 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2524102 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028459 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223325364 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101690449 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86898361 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 609595 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 418176 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 299341 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90910760 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 304951 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1670602 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3039596 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21688 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1851988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2879819 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5660 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20258 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1772027 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3150 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 205518 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3047 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 205936 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 394897 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1352665 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2733681 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100982224 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 167502 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23316234 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16465365 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5553 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3853 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2732159 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21688 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 162395 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 158558 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 320953 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88354535 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22848688 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 813389 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 351152 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1286887 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2706445 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100341607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 125884 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23156457 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16385404 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5552 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3769 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2705021 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20258 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 121859 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 151192 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 273051 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87981340 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22747403 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 710269 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9535592 # number of nop insts executed -system.cpu.iew.exec_refs 38764588 # number of memory reference insts executed -system.cpu.iew.exec_branches 15181336 # Number of branches executed -system.cpu.iew.exec_stores 15915900 # Number of stores executed -system.cpu.iew.exec_rate 1.951545 # Inst execution rate -system.cpu.iew.wb_sent 87941007 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87518995 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33890392 # num instructions producing a value -system.cpu.iew.wb_consumers 44346264 # num instructions consuming a value +system.cpu.iew.exec_nop 9501426 # number of nop insts executed +system.cpu.iew.exec_refs 38618193 # number of memory reference insts executed +system.cpu.iew.exec_branches 15127263 # Number of branches executed +system.cpu.iew.exec_stores 15870790 # Number of stores executed +system.cpu.iew.exec_rate 1.967678 # Inst execution rate +system.cpu.iew.wb_sent 87600358 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87197702 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33849535 # num instructions producing a value +system.cpu.iew.wb_consumers 44277575 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.933090 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764222 # average fanout of values written-back +system.cpu.iew.wb_rate 1.950152 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764485 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9432406 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8791000 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 275041 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43112835 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.049057 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.870632 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 232388 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 42666920 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.070472 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.884283 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21537439 49.96% 49.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6339258 14.70% 64.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2938097 6.81% 71.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1767481 4.10% 75.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1703049 3.95% 79.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1136594 2.64% 82.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1201073 2.79% 84.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 797579 1.85% 86.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5692265 13.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21190783 49.67% 49.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6285871 14.73% 64.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2905995 6.81% 71.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1744112 4.09% 75.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1680276 3.94% 79.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1128586 2.65% 81.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1203447 2.82% 84.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 797041 1.87% 86.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5730809 13.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43112835 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 42666920 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -602,349 +604,333 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5692265 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 133876306 # The number of ROB reads -system.cpu.rob.rob_writes 196941310 # The number of ROB writes -system.cpu.timesIdled 47582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 769754 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 5730809 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 132750441 # The number of ROB reads +system.cpu.rob.rob_writes 195556891 # The number of ROB writes +system.cpu.timesIdled 46372 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 756091 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.568830 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.568830 # CPI: Total CPI of All Threads -system.cpu.ipc 1.757996 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.757996 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116950893 # number of integer regfile reads -system.cpu.int_regfile_writes 57974920 # number of integer regfile writes -system.cpu.fp_regfile_reads 255771 # number of floating regfile reads -system.cpu.fp_regfile_writes 241359 # number of floating regfile writes -system.cpu.misc_regfile_reads 38164 # number of misc regfile reads +system.cpu.cpi 0.561783 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.561783 # CPI: Total CPI of All Threads +system.cpu.ipc 1.780048 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.780048 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116466074 # number of integer regfile reads +system.cpu.int_regfile_writes 57713698 # number of integer regfile writes +system.cpu.fp_regfile_reads 255059 # number of floating regfile reads +system.cpu.fp_regfile_writes 240376 # number of floating regfile writes +system.cpu.misc_regfile_reads 38265 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201397 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.850359 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34098493 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205493 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.935059 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 231077500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.850359 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993860 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993860 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201297 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.745765 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 33997888 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205393 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.526031 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 229746500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.745765 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993834 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993834 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2777 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2788 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1232 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71045365 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71045365 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20537317 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20537317 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13561115 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13561115 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34098432 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34098432 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34098432 # number of overall hits -system.cpu.dcache.overall_hits::total 34098432 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269180 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1052262 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1052262 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1321442 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1321442 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1321442 # number of overall misses -system.cpu.dcache.overall_misses::total 1321442 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17386725500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17386725500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 89260696666 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 89260696666 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 99000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106647422166 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106647422166 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106647422166 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106647422166 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20806497 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20806497 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70843209 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70843209 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20436554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20436554 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561278 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561278 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 56 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 56 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 33997832 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33997832 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33997832 # number of overall hits +system.cpu.dcache.overall_hits::total 33997832 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 268921 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 268921 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1052099 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1052099 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1321020 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1321020 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1321020 # number of overall misses +system.cpu.dcache.overall_misses::total 1321020 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17355062000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17355062000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89131929604 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89131929604 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106486991604 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106486991604 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106486991604 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106486991604 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20705475 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20705475 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 62 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35419874 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35419874 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35419874 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35419874 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012937 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012937 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072007 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072007 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016129 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016129 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037308 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037308 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037308 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037308 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64591.446244 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 64591.446244 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84827.444749 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 84827.444749 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 80705.337174 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 80705.337174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 80705.337174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 80705.337174 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6894813 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 56 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35318852 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35318852 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35318852 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35318852 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012988 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012988 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071996 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071996 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037403 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037403 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037403 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037403 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64535.912034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64535.912034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 84718.196295 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 84718.196295 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80609.674043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80609.674043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80609.674043 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6869550 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 88842 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 88969 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.607584 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.212849 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168840 # number of writebacks -system.cpu.dcache.writebacks::total 168840 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207085 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207085 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908865 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 908865 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1115950 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1115950 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1115950 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1115950 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62095 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62095 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168788 # number of writebacks +system.cpu.dcache.writebacks::total 168788 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206925 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 206925 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908702 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 908702 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115627 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115627 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115627 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115627 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61996 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61996 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143397 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143397 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205492 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205492 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205492 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205492 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3215385000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3215385000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14267732202 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14267732202 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 98000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 98000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483117202 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17483117202 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17483117202 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17483117202 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002984 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002984 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 205393 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205393 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205393 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205393 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3212836500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3212836500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14233206202 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14233206202 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17446042702 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17446042702 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17446042702 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17446042702 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002994 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002994 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.016129 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.016129 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005802 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005802 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005802 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005802 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51781.705451 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51781.705451 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99498.122011 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99498.122011 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85079.308207 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 85079.308207 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85079.308207 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 85079.308207 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005815 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005815 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005815 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51823.286986 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51823.286986 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99257.349889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99257.349889 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84939.811493 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84939.811493 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 93160 # number of replacements -system.cpu.icache.tags.tagsinuse 1916.318628 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13863089 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 95208 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 145.608447 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19085068500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1916.318628 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.935702 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.935702 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 91498 # number of replacements +system.cpu.icache.tags.tagsinuse 1915.935564 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13655300 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 93546 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 145.974173 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18815415500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1915.935564 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935515 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935515 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1486 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 371 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1476 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 380 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 28038306 # Number of tag accesses -system.cpu.icache.tags.data_accesses 28038306 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13863089 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13863089 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13863089 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13863089 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13863089 # number of overall hits -system.cpu.icache.overall_hits::total 13863089 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 108460 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 108460 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 108460 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 108460 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 108460 # number of overall misses -system.cpu.icache.overall_misses::total 108460 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2048888998 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2048888998 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2048888998 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2048888998 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2048888998 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2048888998 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13971549 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13971549 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13971549 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13971549 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13971549 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13971549 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007763 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007763 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007763 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007763 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007763 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007763 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18890.733893 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18890.733893 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18890.733893 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18890.733893 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18890.733893 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18890.733893 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1159 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27617236 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15051639000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15577205500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912020 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912020 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.077535 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.077535 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.448676 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.448676 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71321.278328 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94900.154472 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 93853.287262 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 157304 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 283196 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 143468 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 95209 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62096 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 283577 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612383 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 895960 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6093312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23957312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30050624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 132107 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 727366 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.181624 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.385534 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 155540 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 283136 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 141723 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 93547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 61994 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 278591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612083 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 890674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5986944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23947584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29934528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 132064 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 723799 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.182459 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.386223 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 595259 81.84% 81.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 132107 18.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 591735 81.75% 81.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 132064 18.25% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 727366 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 466469500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 723799 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 464655500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 142819485 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 140327982 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308243991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 308097983 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 35242 # Transaction distribution -system.membus.trans_dist::Writeback 114356 # Transaction distribution -system.membus.trans_dist::CleanEvict 15775 # Transaction distribution -system.membus.trans_dist::ReadExReq 130781 # Transaction distribution -system.membus.trans_dist::ReadExResp 130781 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35242 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462177 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17944256 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17944256 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 35190 # Transaction distribution +system.membus.trans_dist::Writeback 114348 # Transaction distribution +system.membus.trans_dist::CleanEvict 15746 # Transaction distribution +system.membus.trans_dist::ReadExReq 130783 # Transaction distribution +system.membus.trans_dist::ReadExResp 130783 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35190 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462040 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 462040 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17940544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17940544 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 296154 # Request fanout histogram +system.membus.snoop_fanout::samples 296067 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 296154 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 296067 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 296154 # Request fanout histogram -system.membus.reqLayer0.occupancy 778878000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 857917500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 296067 # Request fanout histogram +system.membus.reqLayer0.occupancy 778875000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 857731250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini index 5bde02f67..802d9b780 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -759,7 +759,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout index 0ebe6ca65..f97f5968b 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 03:05:45 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x3b079b0 info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 57738195500 because target called exit() +Exiting @ tick 56986224500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index a8d113a77..227ff6a79 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057054 # Number of seconds simulated -sim_ticks 57053790500 # Number of ticks simulated -final_tick 57053790500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.056986 # Number of seconds simulated +sim_ticks 56986224500 # Number of ticks simulated +final_tick 56986224500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 195523 # Simulator instruction rate (inst/s) -host_op_rate 250045 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 157305109 # Simulator tick rate (ticks/s) -host_mem_usage 323528 # Number of bytes of host memory used -host_seconds 362.70 # Real time elapsed on the host +host_inst_rate 135704 # Simulator instruction rate (inst/s) +host_op_rate 173546 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 109049636 # Simulator tick rate (ticks/s) +host_mem_usage 317176 # Number of bytes of host memory used +host_seconds 522.57 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 319296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7924224 # Number of bytes read from this memory -system.physmem.bytes_read::total 8243520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 319296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 319296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5514240 # Number of bytes written to this memory -system.physmem.bytes_written::total 5514240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123816 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128805 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86160 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86160 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5596403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 138890404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 144486807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5596403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5596403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96649845 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96649845 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96649845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5596403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 138890404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 241136652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128805 # Number of read requests accepted -system.physmem.writeReqs 86160 # Number of write requests accepted -system.physmem.readBursts 128805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 86160 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8243200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5512512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8243520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5514240 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 318720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923904 # Number of bytes read from this memory +system.physmem.bytes_read::total 8242624 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 318720 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 318720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5514048 # Number of bytes written to this memory +system.physmem.bytes_written::total 5514048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123811 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128791 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86157 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86157 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 5592931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 139049464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144642395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5592931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5592931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 96761069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 96761069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 96761069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5592931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 139049464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 241403464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128791 # Number of read requests accepted +system.physmem.writeReqs 86157 # Number of write requests accepted +system.physmem.readBursts 128791 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 86157 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 8242176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue +system.physmem.bytesWritten 5512000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8242624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5514048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 8145 # Per bank write bursts -system.physmem.perBankRdBursts::1 8375 # Per bank write bursts -system.physmem.perBankRdBursts::2 8247 # Per bank write bursts +system.physmem.perBankRdBursts::0 8144 # Per bank write bursts +system.physmem.perBankRdBursts::1 8370 # Per bank write bursts +system.physmem.perBankRdBursts::2 8248 # Per bank write bursts system.physmem.perBankRdBursts::3 8170 # Per bank write bursts -system.physmem.perBankRdBursts::4 8318 # Per bank write bursts -system.physmem.perBankRdBursts::5 8434 # Per bank write bursts +system.physmem.perBankRdBursts::4 8315 # Per bank write bursts +system.physmem.perBankRdBursts::5 8436 # Per bank write bursts system.physmem.perBankRdBursts::6 8084 # Per bank write bursts -system.physmem.perBankRdBursts::7 7957 # Per bank write bursts -system.physmem.perBankRdBursts::8 8058 # Per bank write bursts -system.physmem.perBankRdBursts::9 7633 # Per bank write bursts -system.physmem.perBankRdBursts::10 7816 # Per bank write bursts +system.physmem.perBankRdBursts::7 7955 # Per bank write bursts +system.physmem.perBankRdBursts::8 8060 # Per bank write bursts +system.physmem.perBankRdBursts::9 7629 # Per bank write bursts +system.physmem.perBankRdBursts::10 7815 # Per bank write bursts system.physmem.perBankRdBursts::11 7829 # Per bank write bursts -system.physmem.perBankRdBursts::12 7882 # Per bank write bursts -system.physmem.perBankRdBursts::13 7879 # Per bank write bursts -system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 7996 # Per bank write bursts +system.physmem.perBankRdBursts::12 7881 # Per bank write bursts +system.physmem.perBankRdBursts::13 7878 # Per bank write bursts +system.physmem.perBankRdBursts::14 7975 # Per bank write bursts +system.physmem.perBankRdBursts::15 7995 # Per bank write bursts system.physmem.perBankWrBursts::0 5393 # Per bank write bursts system.physmem.perBankWrBursts::1 5541 # Per bank write bursts system.physmem.perBankWrBursts::2 5463 # Per bank write bursts system.physmem.perBankWrBursts::3 5328 # Per bank write bursts system.physmem.perBankWrBursts::4 5352 # Per bank write bursts -system.physmem.perBankWrBursts::5 5550 # Per bank write bursts -system.physmem.perBankWrBursts::6 5247 # Per bank write bursts +system.physmem.perBankWrBursts::5 5545 # Per bank write bursts +system.physmem.perBankWrBursts::6 5246 # Per bank write bursts system.physmem.perBankWrBursts::7 5180 # Per bank write bursts system.physmem.perBankWrBursts::8 5155 # Per bank write bursts -system.physmem.perBankWrBursts::9 5102 # Per bank write bursts +system.physmem.perBankWrBursts::9 5101 # Per bank write bursts system.physmem.perBankWrBursts::10 5289 # Per bank write bursts system.physmem.perBankWrBursts::11 5270 # Per bank write bursts system.physmem.perBankWrBursts::12 5531 # Per bank write bursts system.physmem.perBankWrBursts::13 5597 # Per bank write bursts system.physmem.perBankWrBursts::14 5703 # Per bank write bursts -system.physmem.perBankWrBursts::15 5432 # Per bank write bursts +system.physmem.perBankWrBursts::15 5431 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57053759500 # Total gap between requests +system.physmem.totGap 56986193500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128805 # Read request sizes (log2) +system.physmem.readPktSize::6 128791 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 86160 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116563 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12216 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 86157 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 116559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4080 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,97 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38707 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 355.314336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.053807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.949103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12175 31.45% 31.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8182 21.14% 52.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4142 10.70% 63.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2786 7.20% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2727 7.05% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1625 4.20% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1301 3.36% 85.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1172 3.03% 88.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4597 11.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38707 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.311061 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 351.967739 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5296 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38656 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 355.735099 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 216.399320 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.915140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12161 31.46% 31.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8166 21.12% 52.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4096 10.60% 63.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2818 7.29% 70.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2687 6.95% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1672 4.33% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1300 3.36% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1153 2.98% 88.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4603 11.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38656 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5291 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.313362 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 352.121472 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5289 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.259581 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.243681 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.749380 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4690 88.54% 88.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 4 0.08% 88.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 472 8.91% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 106 2.00% 99.53% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5291 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5291 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.277641 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.260577 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.779844 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4640 87.70% 87.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.11% 87.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 513 9.70% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 107 2.02% 99.53% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::20 18 0.34% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5297 # Writes before turning the bus around for reads -system.physmem.totQLat 1693807750 # Total ticks spent queuing -system.physmem.totMemAccLat 4108807750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13150.68 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::21 4 0.08% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5291 # Writes before turning the bus around for reads +system.physmem.totQLat 1688662500 # Total ticks spent queuing +system.physmem.totMemAccLat 4103362500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 643920000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13112.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31900.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 144.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.62 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 144.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31862.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 144.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 96.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 144.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.88 # Data bus utilization in percentage +system.physmem.busUtil 1.89 # Data bus utilization in percentage system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.75 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.52 # Average write queue length when enqueuing -system.physmem.readRowHits 112096 # Number of row buffer hits during reads -system.physmem.writeRowHits 64121 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.42 # Row buffer hit rate for writes -system.physmem.avgGap 265409.53 # Average gap between requests -system.physmem.pageHitRate 81.98 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 151956000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82912500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512405400 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 23.57 # Average write queue length when enqueuing +system.physmem.readRowHits 112105 # Number of row buffer hits during reads +system.physmem.writeRowHits 64137 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.44 # Row buffer hit rate for writes +system.physmem.avgGap 265116.18 # Average gap between requests +system.physmem.pageHitRate 82.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512194800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 278951040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3726219120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11612859660 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24043349250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40408652970 # Total energy per rank (pJ) -system.physmem_0.averagePower 708.301006 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 39871864500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1905020000 # Time in different power states +system.physmem_0.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11693696490 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 23930394000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 40371922185 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.527477 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 39682710000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1902680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15273243000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15394661250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 140638680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76737375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 491797800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 279151920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3726219120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11026970910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24557286750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40298802555 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.375499 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 40728832250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1905020000 # Time in different power states +system.physmem_1.actEnergy 140086800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76436250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 491673000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 279138960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3721642080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11090732535 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24459309750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 40259019375 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.546032 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40563908250 # Time in different power states +system.physmem_1.memoryStateTime::REF 1902680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14416275250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14513554250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14816555 # Number of BP lookups -system.cpu.branchPred.condPredicted 9915062 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 392110 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9527196 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6742365 # Number of BTB hits +system.cpu.branchPred.lookups 14800511 # Number of BP lookups +system.cpu.branchPred.condPredicted 9905691 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 381680 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9439152 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6732150 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.769668 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1716488 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 71.321555 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1714112 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -403,97 +404,97 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 114107581 # number of cpu cycles simulated +system.cpu.numCycles 113972449 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915128 # Number of instructions committed system.cpu.committedOps 90690084 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1163698 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1144886 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.609072 # CPI: cycles per instruction -system.cpu.ipc 0.621476 # IPC: instructions per cycle -system.cpu.tickCycles 95702284 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18405297 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156420 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.153595 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42625103 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160516 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.550493 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 823362500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.153595 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992957 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992957 # Average percentage of cache occupancy +system.cpu.cpi 1.607167 # CPI: cycles per instruction +system.cpu.ipc 0.622213 # IPC: instructions per cycle +system.cpu.tickCycles 95596263 # Number of cycles that the object actually ticked +system.cpu.idleCycles 18376186 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156435 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.140403 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42624247 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160531 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.520348 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 822680500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.140403 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992954 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1109 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1113 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2936 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86018450 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86018450 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22867482 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22867482 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642183 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642183 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83600 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83600 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86016733 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86016733 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22866807 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22866807 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642189 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642189 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83413 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83413 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42509665 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42509665 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42593265 # number of overall hits -system.cpu.dcache.overall_hits::total 42593265 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 51591 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 51591 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207718 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207718 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44555 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44555 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 259309 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 259309 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 303864 # number of overall misses -system.cpu.dcache.overall_misses::total 303864 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1486882500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1486882500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 16821632500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 16821632500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18308515000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18308515000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18308515000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18308515000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22919073 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22919073 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42508996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42508996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42592409 # number of overall hits +system.cpu.dcache.overall_hits::total 42592409 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 51550 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 51550 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207712 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207712 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44592 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44592 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 259262 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 259262 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 303854 # number of overall misses +system.cpu.dcache.overall_misses::total 303854 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1489104500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1489104500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16802314000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16802314000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18291418500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18291418500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18291418500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18291418500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22918357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22918357 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128155 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128155 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128005 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128005 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42768974 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42768974 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42897129 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42897129 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002251 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002251 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42768258 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42768258 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42896263 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896263 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002249 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002249 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.347665 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.347665 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006063 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006063 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28820.579171 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28820.579171 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80983.027470 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80983.027470 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70605.011781 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70605.011781 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60252.333281 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60252.333281 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348361 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.348361 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006062 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006062 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007083 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007083 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28886.605238 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28886.605238 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80892.360576 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80892.360576 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70551.868380 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70551.868380 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60198.050709 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60198.050709 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,110 +503,110 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128380 # number of writebacks -system.cpu.dcache.writebacks::total 128380 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22097 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22097 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100690 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100690 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 122787 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 122787 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 122787 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 122787 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29494 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29494 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 128400 # number of writebacks +system.cpu.dcache.writebacks::total 128400 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22032 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22032 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100684 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100684 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 122716 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 122716 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 122716 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 122716 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29518 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29518 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107028 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 107028 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23994 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23994 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136522 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136522 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160516 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160516 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 572555000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 572555000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8494060500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8494060500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1717129000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1717129000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9066615500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9066615500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10783744500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10783744500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23985 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23985 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136546 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 136546 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160531 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160531 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 574723500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 574723500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8485443000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8485443000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719503000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719503000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9060166500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9060166500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10779669500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10779669500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187226 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187226 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187375 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187375 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19412.592392 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19412.592392 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79362.975109 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79362.975109 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71564.932900 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71564.932900 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66411.387908 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66411.387908 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67181.742007 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 67181.742007 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19470.272376 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19470.272376 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79282.458796 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79282.458796 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71690.765061 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71690.765061 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66352.485609 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66352.485609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67150.080047 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67150.080047 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42980 # number of replacements -system.cpu.icache.tags.tagsinuse 1852.974873 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 24976744 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 45022 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 554.767536 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42865 # number of replacements +system.cpu.icache.tags.tagsinuse 1852.538301 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24941041 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44907 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 555.393168 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1852.974873 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.904773 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.904773 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1852.538301 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.904560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.904560 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 914 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1007 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50088556 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50088556 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24976744 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24976744 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24976744 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24976744 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24976744 # number of overall hits -system.cpu.icache.overall_hits::total 24976744 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 45023 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 45023 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 45023 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 45023 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 45023 # number of overall misses -system.cpu.icache.overall_misses::total 45023 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 929482000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 929482000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 929482000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 929482000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 929482000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 929482000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25021767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25021767 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25021767 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25021767 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25021767 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25021767 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001799 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001799 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001799 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001799 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001799 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001799 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20644.603869 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20644.603869 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20644.603869 # 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number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 65 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1376 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1376 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4990 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4990 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 65 # 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number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 346082000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8915110500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9261192500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 346082000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8915110500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9261192500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 4981 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123811 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128792 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 4981 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123811 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128792 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7252200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7252200000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 344388000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 344388000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1658643500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1658643500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 344388000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8910843500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9255231500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 344388000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8910843500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9255231500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955647 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955647 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110832 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110832 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402614 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402614 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110832 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771362 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.626674 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110832 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771362 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.626674 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70988.981336 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70988.981336 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69355.110220 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69355.110220 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76818.504760 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76818.504760 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69355.110220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72002.895425 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71900.319085 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69355.110220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72002.895425 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71900.319085 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955600 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955600 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110916 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402501 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402501 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.626911 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.110916 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771259 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.626911 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70908.130940 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70908.130940 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69140.333266 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69140.333266 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77020.826561 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77020.826561 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69140.333266 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71971.339380 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71861.850891 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 98510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 214540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 72719 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 214557 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 72583 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 45023 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53488 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473213 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 602669 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2881408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18489344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21370752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 95667 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 500606 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.191102 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.393170 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 44908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129101 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473262 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 602363 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2874048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21365632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 95654 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 500393 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.191158 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.393213 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 404939 80.89% 80.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 95667 19.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 404739 80.88% 80.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 95654 19.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 500606 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 330849500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 500393 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 330769500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 67538489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 67366488 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240805936 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240828935 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadResp 26524 # Transaction distribution -system.membus.trans_dist::Writeback 86160 # Transaction distribution -system.membus.trans_dist::CleanEvict 7518 # Transaction distribution -system.membus.trans_dist::ReadExReq 102281 # Transaction distribution -system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26524 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 351288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13757760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13757760 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 26515 # Transaction distribution +system.membus.trans_dist::Writeback 86157 # Transaction distribution +system.membus.trans_dist::CleanEvict 7510 # Transaction distribution +system.membus.trans_dist::ReadExReq 102276 # Transaction distribution +system.membus.trans_dist::ReadExResp 102276 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26515 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 351249 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 351249 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13756672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13756672 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 222483 # Request fanout histogram +system.membus.snoop_fanout::samples 222458 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222483 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222458 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222483 # Request fanout histogram -system.membus.reqLayer0.occupancy 591579500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222458 # Request fanout histogram +system.membus.reqLayer0.occupancy 591536000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 679724750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 679701000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 4695f21d9..af3d3e8bc 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -688,7 +688,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini index e5802151f..dc295a8fa 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini @@ -125,7 +125,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -548,7 +548,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -597,7 +597,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index baff53399..46df80677 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,104 +1,104 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.209315 # Number of seconds simulated -sim_ticks 1209314565500 # Number of ticks simulated -final_tick 1209314565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.208801 # Number of seconds simulated +sim_ticks 1208800797500 # Number of ticks simulated +final_tick 1208800797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 310001 # Simulator instruction rate (inst/s) -host_op_rate 310001 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 205263152 # Simulator tick rate (ticks/s) -host_mem_usage 296916 # Number of bytes of host memory used -host_seconds 5891.53 # Real time elapsed on the host +host_inst_rate 239332 # Simulator instruction rate (inst/s) +host_op_rate 239332 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158403619 # Simulator tick rate (ticks/s) +host_mem_usage 291552 # Number of bytes of host memory used +host_seconds 7631.14 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124968128 # Number of bytes read from this memory -system.physmem.bytes_read::total 125029440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65415808 # Number of bytes written to this memory -system.physmem.bytes_written::total 65415808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 958 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1952627 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1953585 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1022122 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1022122 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 50700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 103337983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103388683 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 50700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 50700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54093294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54093294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54093294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 50700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 103337983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 157481977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1953585 # Number of read requests accepted -system.physmem.writeReqs 1022122 # Number of write requests accepted -system.physmem.readBursts 1953585 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1022122 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 124947328 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82112 # Total number of bytes read from write queue -system.physmem.bytesWritten 65414528 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125029440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65415808 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1283 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124969728 # Number of bytes read from this memory +system.physmem.bytes_read::total 125030976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65417024 # Number of bytes written to this memory +system.physmem.bytes_written::total 65417024 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1952652 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1953609 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1022141 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1022141 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103383228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103433896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50668 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54117291 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54117291 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54117291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103383228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157551187 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1953609 # Number of read requests accepted +system.physmem.writeReqs 1022141 # Number of write requests accepted +system.physmem.readBursts 1953609 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1022141 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 124949504 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81472 # Total number of bytes read from write queue +system.physmem.bytesWritten 65415744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125030976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65417024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1273 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118324 # Per bank write bursts -system.physmem.perBankRdBursts::1 113533 # Per bank write bursts -system.physmem.perBankRdBursts::2 115739 # Per bank write bursts -system.physmem.perBankRdBursts::3 117256 # Per bank write bursts -system.physmem.perBankRdBursts::4 117310 # Per bank write bursts -system.physmem.perBankRdBursts::5 117130 # Per bank write bursts -system.physmem.perBankRdBursts::6 119399 # Per bank write bursts -system.physmem.perBankRdBursts::7 124116 # Per bank write bursts -system.physmem.perBankRdBursts::8 126631 # Per bank write bursts +system.physmem.perBankRdBursts::0 118329 # Per bank write bursts +system.physmem.perBankRdBursts::1 113529 # Per bank write bursts +system.physmem.perBankRdBursts::2 115744 # Per bank write bursts +system.physmem.perBankRdBursts::3 117255 # Per bank write bursts +system.physmem.perBankRdBursts::4 117308 # Per bank write bursts +system.physmem.perBankRdBursts::5 117125 # Per bank write bursts +system.physmem.perBankRdBursts::6 119396 # Per bank write bursts +system.physmem.perBankRdBursts::7 124121 # Per bank write bursts +system.physmem.perBankRdBursts::8 126643 # Per bank write bursts system.physmem.perBankRdBursts::9 129581 # Per bank write bursts -system.physmem.perBankRdBursts::10 128158 # Per bank write bursts -system.physmem.perBankRdBursts::11 129926 # Per bank write bursts -system.physmem.perBankRdBursts::12 125582 # Per bank write bursts -system.physmem.perBankRdBursts::13 124841 # Per bank write bursts -system.physmem.perBankRdBursts::14 122135 # Per bank write bursts -system.physmem.perBankRdBursts::15 122641 # Per bank write bursts +system.physmem.perBankRdBursts::10 128162 # Per bank write bursts +system.physmem.perBankRdBursts::11 129917 # Per bank write bursts +system.physmem.perBankRdBursts::12 125585 # Per bank write bursts +system.physmem.perBankRdBursts::13 124851 # Per bank write bursts +system.physmem.perBankRdBursts::14 122145 # Per bank write bursts +system.physmem.perBankRdBursts::15 122645 # Per bank write bursts system.physmem.perBankWrBursts::0 61422 # Per bank write bursts -system.physmem.perBankWrBursts::1 61664 # Per bank write bursts -system.physmem.perBankWrBursts::2 60721 # Per bank write bursts -system.physmem.perBankWrBursts::3 61393 # Per bank write bursts -system.physmem.perBankWrBursts::4 61822 # Per bank write bursts -system.physmem.perBankWrBursts::5 63305 # Per bank write bursts -system.physmem.perBankWrBursts::6 64352 # Per bank write bursts -system.physmem.perBankWrBursts::7 65861 # Per bank write bursts -system.physmem.perBankWrBursts::8 65572 # Per bank write bursts -system.physmem.perBankWrBursts::9 66032 # Per bank write bursts -system.physmem.perBankWrBursts::10 65638 # Per bank write bursts -system.physmem.perBankWrBursts::11 65947 # Per bank write bursts -system.physmem.perBankWrBursts::12 64508 # Per bank write bursts -system.physmem.perBankWrBursts::13 64525 # Per bank write bursts -system.physmem.perBankWrBursts::14 64898 # Per bank write bursts -system.physmem.perBankWrBursts::15 64442 # Per bank write bursts +system.physmem.perBankWrBursts::1 61663 # Per bank write bursts +system.physmem.perBankWrBursts::2 60725 # Per bank write bursts +system.physmem.perBankWrBursts::3 61394 # Per bank write bursts +system.physmem.perBankWrBursts::4 61815 # Per bank write bursts +system.physmem.perBankWrBursts::5 63308 # Per bank write bursts +system.physmem.perBankWrBursts::6 64356 # Per bank write bursts +system.physmem.perBankWrBursts::7 65855 # Per bank write bursts +system.physmem.perBankWrBursts::8 65579 # Per bank write bursts +system.physmem.perBankWrBursts::9 66031 # Per bank write bursts +system.physmem.perBankWrBursts::10 65643 # Per bank write bursts +system.physmem.perBankWrBursts::11 65948 # Per bank write bursts +system.physmem.perBankWrBursts::12 64510 # Per bank write bursts +system.physmem.perBankWrBursts::13 64527 # Per bank write bursts +system.physmem.perBankWrBursts::14 64896 # Per bank write bursts +system.physmem.perBankWrBursts::15 64449 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1209314463000 # Total gap between requests +system.physmem.totGap 1208800695000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1953585 # Read request sizes (log2) +system.physmem.readPktSize::6 1953609 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1022122 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1829869 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 122416 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1022141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1830062 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 60176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 60147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,29 +193,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1831684 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.926852 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.136404 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.467751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1453241 79.34% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 261868 14.30% 93.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48841 2.67% 96.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20589 1.12% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13172 0.72% 98.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7181 0.39% 98.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5391 0.29% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4514 0.25% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16887 0.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1831684 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.743530 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 149.210927 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59467 99.74% 99.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 109 0.18% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 6 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 6 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1831783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.923052 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.128953 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 130.461416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1453465 79.35% 79.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261783 14.29% 93.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48685 2.66% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20654 1.13% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13128 0.72% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7168 0.39% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5621 0.31% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4509 0.25% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16770 0.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1831783 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59616 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.746846 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 147.774131 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59455 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 113 0.19% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 11 0.02% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 8 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-3583 3 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3584-4095 3 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes @@ -225,104 +225,103 @@ system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # R system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10752-11263 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-13823 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59621 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59621 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.143322 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.107211 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.116873 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27512 46.14% 46.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1216 2.04% 48.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26386 44.26% 92.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3971 6.66% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 453 0.76% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 62 0.10% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 10 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 9 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59621 # Writes before turning the bus around for reads -system.physmem.totQLat 36542895500 # Total ticks spent queuing -system.physmem.totMemAccLat 73148558000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9761510000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18717.85 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59616 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.145079 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.109083 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.114634 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27440 46.03% 46.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1214 2.04% 48.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26474 44.41% 92.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3953 6.63% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 450 0.75% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 71 0.12% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 11 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59616 # Writes before turning the bus around for reads +system.physmem.totQLat 36544132750 # Total ticks spent queuing +system.physmem.totMemAccLat 73150432750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9761680000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18718.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37467.85 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 103.32 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.09 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37468.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 54.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 54.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.77 # Average write queue length when enqueuing -system.physmem.readRowHits 723569 # Number of row buffer hits during reads -system.physmem.writeRowHits 419148 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 723493 # Number of row buffer hits during reads +system.physmem.writeRowHits 419177 # Number of row buffer hits during writes system.physmem.readRowHitRate 37.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate 41.01 # Row buffer hit rate for writes -system.physmem.avgGap 406395.68 # Average gap between requests +system.physmem.avgGap 406217.15 # Average gap between requests system.physmem.pageHitRate 38.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6717619440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3665367750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7353894600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3243499200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 78986487840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 416110602285 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 360579035250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 876656506365 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.920562 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 597088834750 # Time in different power states -system.physmem_0.memoryStateTime::REF 40381640000 # Time in different power states +system.physmem_0.actEnergy 6716750040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3664893375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7353886800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3243486240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 78952922880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 415155955455 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361108109250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 876196004040 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.847786 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 597970225000 # Time in different power states +system.physmem_0.memoryStateTime::REF 40364480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 571843431500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 570465308750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7129911600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3890328750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7873975200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3379721760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 78986487840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 426511213875 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 351455691750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 879227330775 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.046416 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 581836550250 # Time in different power states -system.physmem_1.memoryStateTime::REF 40381640000 # Time in different power states +system.physmem_1.actEnergy 7131529440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3891211500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7874240400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3379857840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 78952922880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 426545221500 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 351117525000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 878892508560 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.078515 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 581276348750 # Time in different power states +system.physmem_1.memoryStateTime::REF 40364480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 587095716000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 587159309750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246216332 # Number of BP lookups -system.cpu.branchPred.condPredicted 186427958 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15694657 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167633562 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165258832 # Number of BTB hits +system.cpu.branchPred.lookups 246104681 # Number of BP lookups +system.cpu.branchPred.condPredicted 186361047 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15590665 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167674402 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165200232 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.583380 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18428300 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104795 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.524420 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18413418 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104179 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452931478 # DTB read hits -system.cpu.dtb.read_misses 4979966 # DTB read misses +system.cpu.dtb.read_hits 452862393 # DTB read hits +system.cpu.dtb.read_misses 4979628 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457911444 # DTB read accesses -system.cpu.dtb.write_hits 161379324 # DTB write hits -system.cpu.dtb.write_misses 1710368 # DTB write misses +system.cpu.dtb.read_accesses 457842021 # DTB read accesses +system.cpu.dtb.write_hits 161378642 # DTB write hits +system.cpu.dtb.write_misses 1709394 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163089692 # DTB write accesses -system.cpu.dtb.data_hits 614310802 # DTB hits -system.cpu.dtb.data_misses 6690334 # DTB misses +system.cpu.dtb.write_accesses 163088036 # DTB write accesses +system.cpu.dtb.data_hits 614241035 # DTB hits +system.cpu.dtb.data_misses 6689022 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 621001136 # DTB accesses -system.cpu.itb.fetch_hits 598312460 # ITB hits +system.cpu.dtb.data_accesses 620930057 # DTB accesses +system.cpu.itb.fetch_hits 597998986 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598312479 # ITB accesses +system.cpu.itb.fetch_accesses 597999005 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -336,82 +335,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2418629131 # number of cpu cycles simulated +system.cpu.numCycles 2417601595 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52090489 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 51825441 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.324276 # CPI: cycles per instruction -system.cpu.ipc 0.755130 # IPC: instructions per cycle -system.cpu.tickCycles 2076311536 # Number of cycles that the object actually ticked -system.cpu.idleCycles 342317595 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121994 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.733344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601608000 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126090 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.921769 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16821289500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.733344 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy +system.cpu.cpi 1.323713 # CPI: cycles per instruction +system.cpu.ipc 0.755451 # IPC: instructions per cycle +system.cpu.tickCycles 2075284528 # Number of cycles that the object actually ticked +system.cpu.idleCycles 342317067 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9121986 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.726688 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601540360 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126082 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.914415 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16821281500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.726688 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996271 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996271 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1558 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2405 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1562 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2407 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231414126 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231414126 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443125970 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443125970 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158482030 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158482030 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601608000 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601608000 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601608000 # number of overall hits -system.cpu.dcache.overall_hits::total 601608000 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289546 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289546 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2246472 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2246472 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9536018 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9536018 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9536018 # number of overall misses -system.cpu.dcache.overall_misses::total 9536018 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 185444020000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 185444020000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108463697500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108463697500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 293907717500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 293907717500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 293907717500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 293907717500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450415516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450415516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231278878 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231278878 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443058336 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443058336 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158482024 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158482024 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601540360 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601540360 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601540360 # number of overall hits +system.cpu.dcache.overall_hits::total 601540360 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289560 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289560 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2246478 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2246478 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9536038 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9536038 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9536038 # number of overall misses +system.cpu.dcache.overall_misses::total 9536038 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 185462944500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 185462944500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108451503000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108451503000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 293914447500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 293914447500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 293914447500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 293914447500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450347896 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450347896 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611144018 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611144018 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611144018 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611144018 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016184 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016184 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 611076398 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611076398 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611076398 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611076398 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016187 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013977 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013977 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015604 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015604 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015604 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015604 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25439.721486 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25439.721486 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48281.793630 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48281.793630 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30820.801460 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30820.801460 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30820.801460 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30820.801460 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015605 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015605 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015605 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015605 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25442.268738 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25442.268738 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48276.236402 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48276.236402 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30821.442563 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30821.442563 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30821.442563 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30821.442563 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -420,100 +419,100 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3686660 # number of writebacks -system.cpu.dcache.writebacks::total 3686660 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50795 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50795 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359133 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 359133 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 409928 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 409928 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 409928 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 409928 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238751 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238751 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887339 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887339 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126090 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126090 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126090 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126090 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176979090000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 176979090000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83292376000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83292376000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260271466000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 260271466000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260271466000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 260271466000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016071 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016071 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 3686591 # number of writebacks +system.cpu.dcache.writebacks::total 3686591 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50801 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50801 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 359155 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 359155 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 409956 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 409956 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 409956 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 409956 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238759 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238759 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887323 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887323 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126082 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126082 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126082 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126082 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 176998396500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 176998396500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83275965000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83275965000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260274361500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 260274361500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260274361500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 260274361500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016074 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016074 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014933 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014933 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014933 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014933 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24448.843454 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24448.843454 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44132.175513 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44132.175513 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.493671 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.493671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.493671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.493671 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014934 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014934 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014934 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24451.483535 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24451.483535 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44123.854263 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44123.854263 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28519.835949 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28519.835949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28519.835949 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28519.835949 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 751.748828 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 598311502 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 958 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 624542.277662 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 749.172343 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 597998029 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 624867.323929 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 751.748828 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.367065 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.367065 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 955 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 875 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.466309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1196625878 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1196625878 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 598311502 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 598311502 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 598311502 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 598311502 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 598311502 # number of overall hits -system.cpu.icache.overall_hits::total 598311502 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 958 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 958 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 958 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 958 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 958 # number of overall misses -system.cpu.icache.overall_misses::total 958 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 76821500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 76821500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 76821500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 76821500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 76821500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 76821500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 598312460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 598312460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 598312460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 598312460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 598312460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 598312460 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 749.172343 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.365807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.365807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 873 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1195998929 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1195998929 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 597998029 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 597998029 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 597998029 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 597998029 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 597998029 # number of overall hits +system.cpu.icache.overall_hits::total 597998029 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses +system.cpu.icache.overall_misses::total 957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 77181000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 77181000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 77181000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 77181000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 77181000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 77181000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 597998986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 597998986 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 597998986 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 597998986 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 597998986 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 597998986 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80648.902821 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80648.902821 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80648.902821 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -522,125 +521,125 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 958 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 958 # 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number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172109 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 958 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1952627 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1953585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 958 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1952627 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1953585 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60964956000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60964956000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64844500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64844500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90672100500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90672100500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64844500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151637056500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 151701901000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64844500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151637056500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 151701901000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 780512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 957 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 957 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1172140 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1172140 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1952652 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1953609 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1952652 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1953609 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60948826000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60948826000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 65216500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 65216500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 90691390500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 90691390500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65216500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 151640216500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 151705433000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65216500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 151640216500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 151705433000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413555 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413555 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161921 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161921 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.161926 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.161926 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213961 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214043 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213964 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214046 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213961 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214043 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78108.328059 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78108.328059 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67687.369520 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67687.369520 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77358.078899 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77358.078899 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67687.369520 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77657.973848 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.084458 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67687.369520 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77657.973848 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.084458 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213964 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214046 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78088.262576 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78088.262576 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68146.812957 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68146.812957 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77372.490061 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77372.490061 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68146.812957 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68146.812957 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77658.597897 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77653.938429 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7239709 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4708782 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6334073 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238751 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1919 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374174 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27376093 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820016000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820077312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1920858 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20169903 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.095234 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.293538 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 7239716 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4708732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6334139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238759 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1917 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27376067 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820011072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820072320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1920882 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20169910 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.095235 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.293539 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18249045 90.48% 90.48% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1920858 9.52% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18249028 90.48% 90.48% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1920882 9.52% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20169903 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12811182500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 20169910 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12811105000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1437000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1435500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689135000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13689123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1173067 # Transaction distribution -system.membus.trans_dist::Writeback 1022122 # Transaction distribution -system.membus.trans_dist::CleanEvict 897712 # Transaction distribution -system.membus.trans_dist::ReadExReq 780518 # Transaction distribution -system.membus.trans_dist::ReadExResp 780518 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1173067 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827004 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5827004 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190445248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190445248 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1173097 # Transaction distribution +system.membus.trans_dist::Writeback 1022141 # Transaction distribution +system.membus.trans_dist::CleanEvict 897719 # Transaction distribution +system.membus.trans_dist::ReadExReq 780512 # Transaction distribution +system.membus.trans_dist::ReadExResp 780512 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1173097 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5827078 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5827078 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190448000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190448000 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3873419 # Request fanout histogram +system.membus.snoop_fanout::samples 3873469 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3873419 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3873469 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3873419 # Request fanout histogram -system.membus.reqLayer0.occupancy 8427454000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3873469 # Request fanout histogram +system.membus.reqLayer0.occupancy 8428000500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10685206000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10685481750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 0be38fe21..88e337781 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -150,7 +150,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -497,7 +497,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -546,7 +546,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -609,7 +609,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 488ad0a2f..abe06b1e2 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:36:02 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 21:26:54 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +26,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 672881519500 because target called exit() +Exiting @ tick 669556582000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index fd8f8a2dd..cb7ba764c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.671755 # Number of seconds simulated -sim_ticks 671754803000 # Number of ticks simulated -final_tick 671754803000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.669557 # Number of seconds simulated +sim_ticks 669556582000 # Number of ticks simulated +final_tick 669556582000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168955 # Simulator instruction rate (inst/s) -host_op_rate 168955 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65376371 # Simulator tick rate (ticks/s) -host_mem_usage 298196 # Number of bytes of host memory used -host_seconds 10275.19 # Real time elapsed on the host +host_inst_rate 125035 # Simulator instruction rate (inst/s) +host_op_rate 125035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48223337 # Simulator tick rate (ticks/s) +host_mem_usage 292576 # Number of bytes of host memory used +host_seconds 13884.49 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 62400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125486976 # Number of bytes read from this memory -system.physmem.bytes_read::total 125549376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62400 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65552256 # Number of bytes written to this memory -system.physmem.bytes_written::total 65552256 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 975 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960734 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961709 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1024254 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1024254 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 186804732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 186897623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 97583606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 97583606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 97583606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 186804732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 284481229 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961709 # Number of read requests accepted -system.physmem.writeReqs 1024254 # Number of write requests accepted -system.physmem.readBursts 1961709 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1024254 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125464000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 85376 # Total number of bytes read from write queue -system.physmem.bytesWritten 65551040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125549376 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65552256 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1334 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125490304 # Number of bytes read from this memory +system.physmem.bytes_read::total 125551168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 60864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65555584 # Number of bytes written to this memory +system.physmem.bytes_written::total 65555584 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 951 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960786 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961737 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1024306 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1024306 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 90902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 187423001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 187513903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 90902 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90902 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97908953 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97908953 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97908953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 90902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 187423001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 285422856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961737 # Number of read requests accepted +system.physmem.writeReqs 1024306 # Number of write requests accepted +system.physmem.readBursts 1961737 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1024306 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125467392 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83776 # Total number of bytes read from write queue +system.physmem.bytesWritten 65553984 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125551168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65555584 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118672 # Per bank write bursts -system.physmem.perBankRdBursts::1 113926 # Per bank write bursts -system.physmem.perBankRdBursts::2 116092 # Per bank write bursts -system.physmem.perBankRdBursts::3 117630 # Per bank write bursts -system.physmem.perBankRdBursts::4 117777 # Per bank write bursts -system.physmem.perBankRdBursts::5 117495 # Per bank write bursts -system.physmem.perBankRdBursts::6 119900 # Per bank write bursts -system.physmem.perBankRdBursts::7 124641 # Per bank write bursts -system.physmem.perBankRdBursts::8 127326 # Per bank write bursts -system.physmem.perBankRdBursts::9 130085 # Per bank write bursts -system.physmem.perBankRdBursts::10 128786 # Per bank write bursts -system.physmem.perBankRdBursts::11 130484 # Per bank write bursts -system.physmem.perBankRdBursts::12 126296 # Per bank write bursts -system.physmem.perBankRdBursts::13 125416 # Per bank write bursts -system.physmem.perBankRdBursts::14 122597 # Per bank write bursts -system.physmem.perBankRdBursts::15 123252 # Per bank write bursts -system.physmem.perBankWrBursts::0 61496 # Per bank write bursts -system.physmem.perBankWrBursts::1 61762 # Per bank write bursts -system.physmem.perBankWrBursts::2 60827 # Per bank write bursts -system.physmem.perBankWrBursts::3 61508 # Per bank write bursts -system.physmem.perBankWrBursts::4 61962 # Per bank write bursts -system.physmem.perBankWrBursts::5 63415 # Per bank write bursts -system.physmem.perBankWrBursts::6 64494 # Per bank write bursts -system.physmem.perBankWrBursts::7 65970 # Per bank write bursts -system.physmem.perBankWrBursts::8 65774 # Per bank write bursts -system.physmem.perBankWrBursts::9 66157 # Per bank write bursts -system.physmem.perBankWrBursts::10 65800 # Per bank write bursts -system.physmem.perBankWrBursts::11 66076 # Per bank write bursts +system.physmem.perBankRdBursts::0 118679 # Per bank write bursts +system.physmem.perBankRdBursts::1 113901 # Per bank write bursts +system.physmem.perBankRdBursts::2 116111 # Per bank write bursts +system.physmem.perBankRdBursts::3 117641 # Per bank write bursts +system.physmem.perBankRdBursts::4 117753 # Per bank write bursts +system.physmem.perBankRdBursts::5 117515 # Per bank write bursts +system.physmem.perBankRdBursts::6 119854 # Per bank write bursts +system.physmem.perBankRdBursts::7 124644 # Per bank write bursts +system.physmem.perBankRdBursts::8 127345 # Per bank write bursts +system.physmem.perBankRdBursts::9 130108 # Per bank write bursts +system.physmem.perBankRdBursts::10 128796 # Per bank write bursts +system.physmem.perBankRdBursts::11 130507 # Per bank write bursts +system.physmem.perBankRdBursts::12 126297 # Per bank write bursts +system.physmem.perBankRdBursts::13 125432 # Per bank write bursts +system.physmem.perBankRdBursts::14 122623 # Per bank write bursts +system.physmem.perBankRdBursts::15 123222 # Per bank write bursts +system.physmem.perBankWrBursts::0 61508 # Per bank write bursts +system.physmem.perBankWrBursts::1 61766 # Per bank write bursts +system.physmem.perBankWrBursts::2 60825 # Per bank write bursts +system.physmem.perBankWrBursts::3 61511 # Per bank write bursts +system.physmem.perBankWrBursts::4 61967 # Per bank write bursts +system.physmem.perBankWrBursts::5 63434 # Per bank write bursts +system.physmem.perBankWrBursts::6 64481 # Per bank write bursts +system.physmem.perBankWrBursts::7 65996 # Per bank write bursts +system.physmem.perBankWrBursts::8 65770 # Per bank write bursts +system.physmem.perBankWrBursts::9 66159 # Per bank write bursts +system.physmem.perBankWrBursts::10 65809 # Per bank write bursts +system.physmem.perBankWrBursts::11 66083 # Per bank write bursts system.physmem.perBankWrBursts::12 64701 # Per bank write bursts -system.physmem.perBankWrBursts::13 64671 # Per bank write bursts -system.physmem.perBankWrBursts::14 65003 # Per bank write bursts -system.physmem.perBankWrBursts::15 64619 # Per bank write bursts +system.physmem.perBankWrBursts::13 64659 # Per bank write bursts +system.physmem.perBankWrBursts::14 65023 # Per bank write bursts +system.physmem.perBankWrBursts::15 64589 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 671754707500 # Total gap between requests +system.physmem.totGap 669556486500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961709 # Read request sizes (log2) +system.physmem.readPktSize::6 1961737 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1024254 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1618535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 241019 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69861 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1024306 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1618471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 241016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 26136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 63697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 65054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 63649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 65159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,150 +193,149 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1769993 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.917046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.949504 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 137.477186 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1374954 77.68% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271630 15.35% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53313 3.01% 96.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21496 1.21% 97.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12783 0.72% 97.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6453 0.36% 98.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4820 0.27% 98.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3869 0.22% 98.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20675 1.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1769993 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60112 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.611592 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 146.109791 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 59940 99.71% 99.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 128 0.21% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1769592 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.945804 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.951779 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 137.536097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1374979 77.70% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 270914 15.31% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53662 3.03% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21295 1.20% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12785 0.72% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6489 0.37% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4949 0.28% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3948 0.22% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20571 1.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1769592 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60107 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.574625 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 148.683386 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 59945 99.73% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 118 0.20% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 10 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 7 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 6 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 4 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 6 0.01% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 8 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-3071 5 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3583 3 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-4095 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-4607 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-8703 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-9727 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-12799 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60112 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60112 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.038778 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.996488 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.239516 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31933 53.12% 53.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1463 2.43% 55.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 20988 34.91% 90.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4635 7.71% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 815 1.36% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 185 0.31% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 40 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::14848-15359 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 60107 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60107 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.040960 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.998792 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.235687 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31915 53.10% 53.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1364 2.27% 55.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 21027 34.98% 90.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4732 7.87% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 816 1.36% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 161 0.27% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 44 0.07% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::23 14 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::26 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60112 # Writes before turning the bus around for reads -system.physmem.totQLat 40612494250 # Total ticks spent queuing -system.physmem.totMemAccLat 77369525500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9801875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20716.70 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::36 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60107 # Writes before turning the bus around for reads +system.physmem.totQLat 40555708000 # Total ticks spent queuing +system.physmem.totMemAccLat 77313733000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9802140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20687.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39466.70 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 186.77 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 97.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 186.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 97.58 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39437.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 187.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 97.91 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 187.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 97.91 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.22 # Data bus utilization in percentage +system.physmem.busUtil 2.23 # Data bus utilization in percentage system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing -system.physmem.readRowHits 792670 # Number of row buffer hits during reads -system.physmem.writeRowHits 421939 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.19 # Row buffer hit rate for writes -system.physmem.avgGap 224970.87 # Average gap between requests -system.physmem.pageHitRate 40.70 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6484688280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3538272375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7379814000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3249285840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43875505440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 305078205825 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 135438254250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 505044026010 # Total energy per rank (pJ) -system.physmem_0.averagePower 751.831975 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 223329404750 # Time in different power states -system.physmem_0.memoryStateTime::REF 22431240000 # Time in different power states +system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing +system.physmem.readRowHits 792895 # Number of row buffer hits during reads +system.physmem.writeRowHits 422217 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.22 # Row buffer hit rate for writes +system.physmem.avgGap 224228.68 # Average gap between requests +system.physmem.pageHitRate 40.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6483387960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3537562875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7379541000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3249642240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43732091520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 304280359155 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 134820686250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 503483271000 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.966482 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 222309059500 # Time in different power states +system.physmem_0.memoryStateTime::REF 22357920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 425992710250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 424888778500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6896405880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3762919875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7910526000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3387653280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43875505440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 312108901605 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 129270987000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 507212899080 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.060642 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 213031369750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22431240000 # Time in different power states +system.physmem_1.actEnergy 6894704880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3761991750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7911610200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3387698640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43732091520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 311328000180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 128638545000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 505654642170 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.209486 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 211980924500 # Time in different power states +system.physmem_1.memoryStateTime::REF 22357920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 436288612000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 435216639250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 410738673 # Number of BP lookups -system.cpu.branchPred.condPredicted 319032195 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16276977 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282876736 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279471264 # Number of BTB hits +system.cpu.branchPred.lookups 409355418 # Number of BP lookups +system.cpu.branchPred.condPredicted 318166975 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15963047 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282312141 # Number of BTB lookups +system.cpu.branchPred.BTBHits 278580615 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.796129 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26377862 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.678227 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26172204 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646528255 # DTB read hits -system.cpu.dtb.read_misses 12150594 # DTB read misses +system.cpu.dtb.read_hits 644928587 # DTB read hits +system.cpu.dtb.read_misses 12158902 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 658678849 # DTB read accesses -system.cpu.dtb.write_hits 218209856 # DTB write hits -system.cpu.dtb.write_misses 7511426 # DTB write misses +system.cpu.dtb.read_accesses 657087489 # DTB read accesses +system.cpu.dtb.write_hits 218092717 # DTB write hits +system.cpu.dtb.write_misses 7512154 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225721282 # DTB write accesses -system.cpu.dtb.data_hits 864738111 # DTB hits -system.cpu.dtb.data_misses 19662020 # DTB misses +system.cpu.dtb.write_accesses 225604871 # DTB write accesses +system.cpu.dtb.data_hits 863021304 # DTB hits +system.cpu.dtb.data_misses 19671056 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 884400131 # DTB accesses -system.cpu.itb.fetch_hits 422614397 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 882692360 # DTB accesses +system.cpu.itb.fetch_hits 420625120 # ITB hits +system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422614441 # ITB accesses +system.cpu.itb.fetch_accesses 420625157 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -350,238 +349,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1343509607 # number of cpu cycles simulated +system.cpu.numCycles 1339113165 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433913722 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3420789895 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410738673 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305849126 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 886512749 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 46016020 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1692 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 55 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422614397 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8419525 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1343436257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.546299 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.150257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 431760554 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3410003764 # Number of instructions fetch has processed +system.cpu.fetch.Branches 409355418 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 304752819 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 884588278 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 45380492 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1660 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 420625120 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8288982 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1339040790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.546602 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.150665 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 716181443 53.31% 53.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48040729 3.58% 56.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24412482 1.82% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45272149 3.37% 62.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 143062816 10.65% 72.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66221905 4.93% 77.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43789018 3.26% 80.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29632862 2.21% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226822853 16.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 714026661 53.32% 53.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47659433 3.56% 56.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24224234 1.81% 58.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45105968 3.37% 62.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 142792146 10.66% 72.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 65943853 4.92% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43594254 3.26% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29429342 2.20% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226264899 16.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1343436257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305721 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.546160 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355607674 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 404003493 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525762782 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 35055109 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 23007199 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62310513 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 875 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3265200378 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2135 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 23007199 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373983702 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 211600441 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6939 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538809166 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 196028810 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3182220984 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1833786 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 20271739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 149993150 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30859152 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2378179455 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4128151916 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4127979405 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 172510 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1339040790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305691 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.546464 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 353769612 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 403558275 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 524215531 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34807834 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 22689538 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62027781 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 752 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3256129377 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2069 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 22689538 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 372008249 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212535269 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7646 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 537155328 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194644760 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3173788478 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1809495 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20462310 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 148566154 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30882701 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2371842618 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4117718959 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4117582524 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 136434 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001976492 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 195 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 195 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99605318 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719399499 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272964536 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90785513 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58783416 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2890757443 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 174 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624793649 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1589988 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1154713835 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 506306579 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 145 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1343436257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.953791 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.147325 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 995639655 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 143 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 142 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99637264 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 717251547 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272457871 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90453848 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 58428187 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2884203449 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 122 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2620051581 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1544935 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1148159789 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 502731368 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1339040790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.956663 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.148213 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 538259461 40.07% 40.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 170012804 12.66% 52.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158478310 11.80% 64.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149374624 11.12% 75.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126330762 9.40% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84386661 6.28% 91.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68107665 5.07% 96.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34089750 2.54% 98.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14396220 1.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 535540081 39.99% 39.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169652118 12.67% 52.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 157969981 11.80% 64.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149186997 11.14% 75.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 125999252 9.41% 85.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84166081 6.29% 91.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68019052 5.08% 96.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34101039 2.55% 98.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14406189 1.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1343436257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1339040790 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13176390 35.76% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19068779 51.75% 87.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4600766 12.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13157777 35.84% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18965028 51.65% 87.49% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4592425 12.51% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719677353 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 897887 0.03% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 158 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 22 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 673327193 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230890880 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1716938805 65.53% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896154 0.03% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 19 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 163 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 26 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 671533572 25.63% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230682699 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624793649 # Type of FU issued -system.cpu.iq.rate 1.953684 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36845935 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014038 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6629473751 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4044314699 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2522399915 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1985727 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1304235 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 894550 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2660653801 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 985783 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69567792 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2620051581 # Type of FU issued +system.cpu.iq.rate 1.956557 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36715230 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014013 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6615464746 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4031257680 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2518620612 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1939371 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1248863 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 886699 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2655799836 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 966975 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69396280 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274803836 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379517 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 149864 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112236034 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 272655884 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 373351 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 145486 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 111729369 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 312 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6300661 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 229 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6306976 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 23007199 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 150535686 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 19606000 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3042042837 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6687461 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719399499 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272964536 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 174 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 810054 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19058140 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 149864 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10895731 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8841524 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19737255 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2579092054 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658678856 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45701595 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 22689538 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149806110 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21267531 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3035207367 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6595956 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 717251547 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272457871 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 122 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 801675 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 20722786 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 145486 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10633585 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8701131 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19334716 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2574896999 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 657087498 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45154582 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151285220 # number of nop insts executed -system.cpu.iew.exec_refs 884400225 # number of memory reference insts executed -system.cpu.iew.exec_branches 315980786 # Number of branches executed -system.cpu.iew.exec_stores 225721369 # Number of stores executed -system.cpu.iew.exec_rate 1.919668 # Inst execution rate -system.cpu.iew.wb_sent 2553280591 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2523294465 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489396348 # num instructions producing a value -system.cpu.iew.wb_consumers 1920808747 # num instructions consuming a value +system.cpu.iew.exec_nop 151003796 # number of nop insts executed +system.cpu.iew.exec_refs 882692437 # number of memory reference insts executed +system.cpu.iew.exec_branches 315488895 # Number of branches executed +system.cpu.iew.exec_stores 225604939 # Number of stores executed +system.cpu.iew.exec_rate 1.922837 # Inst execution rate +system.cpu.iew.wb_sent 2549331117 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2519507311 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1487495376 # num instructions producing a value +system.cpu.iew.wb_consumers 1918378348 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.878137 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775401 # average fanout of values written-back +system.cpu.iew.wb_rate 1.881475 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775392 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1006176660 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 998666714 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16276166 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1204408845 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.510932 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.544476 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15962339 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1201055691 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.515150 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.548433 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 715098033 59.37% 59.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159881136 13.27% 72.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79829015 6.63% 79.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52096588 4.33% 83.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28578407 2.37% 85.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19544658 1.62% 87.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20010855 1.66% 89.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23112076 1.92% 91.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106258077 8.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 712334289 59.31% 59.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159635442 13.29% 72.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79514551 6.62% 79.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52029279 4.33% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28475742 2.37% 85.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19476450 1.62% 87.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19964545 1.66% 89.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23047887 1.92% 91.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106577506 8.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1204408845 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1201055691 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -627,344 +626,343 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106258077 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3838328354 # The number of ROB reads -system.cpu.rob.rob_writes 5791077348 # The number of ROB writes -system.cpu.timesIdled 692 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 73350 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 106577506 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3827145825 # The number of ROB reads +system.cpu.rob.rob_writes 5775013033 # The number of ROB writes +system.cpu.timesIdled 710 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 72375 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.773892 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.773892 # CPI: Total CPI of All Threads -system.cpu.ipc 1.292171 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.292171 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3468538615 # number of integer regfile reads -system.cpu.int_regfile_writes 2022734233 # number of integer regfile writes -system.cpu.fp_regfile_reads 46009 # number of floating regfile reads -system.cpu.fp_regfile_writes 540 # number of floating regfile writes +system.cpu.cpi 0.771359 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.771359 # CPI: Total CPI of All Threads +system.cpu.ipc 1.296413 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.296413 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3463596666 # number of integer regfile reads +system.cpu.int_regfile_writes 2019349968 # number of integer regfile writes +system.cpu.fp_regfile_reads 39643 # number of floating regfile reads +system.cpu.fp_regfile_writes 588 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9208722 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.471997 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713777147 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9212818 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.476527 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5130746500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.471997 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997918 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997918 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9207223 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.441459 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 712346742 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9211319 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.333848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5127954500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.441459 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997911 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997911 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 709 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2958 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 707 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2960 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1473023486 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1473023486 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558278644 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558278644 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155498498 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155498498 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 5 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 713777142 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 713777142 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 713777142 # number of overall hits -system.cpu.dcache.overall_hits::total 713777142 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12898182 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12898182 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5230004 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5230004 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 1470153653 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1470153653 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 556848599 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 556848599 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155498140 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155498140 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 712346739 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 712346739 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 712346739 # number of overall hits +system.cpu.dcache.overall_hits::total 712346739 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12894062 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12894062 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5230362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5230362 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18128186 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18128186 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18128186 # number of overall misses -system.cpu.dcache.overall_misses::total 18128186 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 411532558500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 411532558500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 315240579886 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 315240579886 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 18124424 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18124424 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18124424 # number of overall misses +system.cpu.dcache.overall_misses::total 18124424 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 412011773000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 412011773000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 315105865697 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 315105865697 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 726773138386 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 726773138386 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 726773138386 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 726773138386 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571176826 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571176826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 727117638697 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 727117638697 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 727117638697 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 727117638697 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 569742661 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 569742661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 731905328 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 731905328 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731905328 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731905328 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022582 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022582 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032539 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032539 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024768 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024768 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024768 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024768 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31906.245275 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31906.245275 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60275.399385 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60275.399385 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 730471163 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 730471163 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 730471163 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 730471163 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022631 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022631 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032542 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032542 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.250000 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024812 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024812 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024812 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024812 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31953.605698 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31953.605698 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60245.517556 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60245.517556 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40090.781195 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40090.781195 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40090.781195 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40090.781195 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15662934 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 9568706 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1102908 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67982 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.201487 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 140.753523 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40118.110164 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40118.110164 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40118.110164 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40118.110164 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15661523 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9569226 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1103711 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 68026 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.189877 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 140.670126 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3728522 # number of writebacks -system.cpu.dcache.writebacks::total 3728522 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5564399 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5564399 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3350970 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3350970 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8915369 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8915369 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8915369 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8915369 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333783 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333783 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879034 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879034 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3727748 # number of writebacks +system.cpu.dcache.writebacks::total 3727748 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5561934 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5561934 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3351172 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3351172 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8913106 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8913106 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8913106 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8913106 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332128 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7332128 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879190 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879190 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9212817 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9212817 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9212817 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9212817 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183008143000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 183008143000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84351384400 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 84351384400 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9211318 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9211318 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9211318 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9211318 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 182959853500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 182959853500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84331903655 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84331903655 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267359527400 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 267359527400 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267359527400 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 267359527400 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012840 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012840 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.166667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.166667 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012587 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012587 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012587 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012587 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24954.125722 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24954.125722 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44890.823902 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44890.823902 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 267291757155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 267291757155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 267291757155 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 267291757155 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.250000 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24953.172326 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24953.172326 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44876.730748 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44876.730748 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71500 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29020.388378 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29020.388378 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29020.388378 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29020.388378 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29017.753719 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29017.753719 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29017.753719 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29017.753719 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 774.831914 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 422612882 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 975 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 433449.109744 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 755.106219 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 420623640 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 951 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 442296.151420 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 774.831914 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.378336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.378336 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 974 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 755.106219 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.368704 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.368704 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 950 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 909 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.475586 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 845229769 # Number of tag accesses -system.cpu.icache.tags.data_accesses 845229769 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422612882 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422612882 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422612882 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422612882 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422612882 # number of overall hits -system.cpu.icache.overall_hits::total 422612882 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1515 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1515 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1515 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1515 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1515 # number of overall misses -system.cpu.icache.overall_misses::total 1515 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 116523500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 116523500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 116523500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 116523500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 116523500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 116523500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422614397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422614397 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422614397 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422614397 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422614397 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422614397 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 886 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.463867 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 841251191 # Number of tag accesses +system.cpu.icache.tags.data_accesses 841251191 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 420623640 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 420623640 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 420623640 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 420623640 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 420623640 # number of overall hits +system.cpu.icache.overall_hits::total 420623640 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1480 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1480 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1480 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1480 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1480 # number of overall misses +system.cpu.icache.overall_misses::total 1480 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 114807500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 114807500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 114807500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 114807500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 114807500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 114807500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 420625120 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 420625120 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 420625120 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 420625120 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 420625120 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 420625120 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76913.201320 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76913.201320 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76913.201320 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76913.201320 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76913.201320 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76913.201320 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 961 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77572.635135 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77572.635135 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77572.635135 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77572.635135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77572.635135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77572.635135 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 120.125000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 540 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 540 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 540 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 82864500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 82864500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 529 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 529 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 529 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 529 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 529 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 951 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 951 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 951 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 951 # 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average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1024254 # number of writebacks -system.cpu.l2cache.writebacks::total 1024254 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1024306 # number of writebacks +system.cpu.l2cache.writebacks::total 1024306 # number of writebacks system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 241 # number of CleanEvict MSHR misses system.cpu.l2cache.CleanEvict_mshr_misses::total 241 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772262 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 772262 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 975 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 975 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188472 # 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number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94648969500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94648969500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71646500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156278918500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 156350565000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71646500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156278918500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 156350565000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 772416 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 772416 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 951 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 951 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1188370 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1188370 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 951 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960786 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961737 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 951 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1960786 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961737 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61608280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61608280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68730000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68730000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 94619528500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 94619528500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68730000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156227809000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 156296539000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68730000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156227809000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 156296539000 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410986 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410986 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411033 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162055 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162055 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162077 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162077 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212827 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.212910 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212867 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.212948 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212827 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.212910 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79804.456260 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79804.456260 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73483.589744 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73483.589744 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79639.208580 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79639.208580 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73483.589744 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79704.293647 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79701.201860 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73483.589744 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79704.293647 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79701.201860 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212867 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.212948 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79760.492403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79760.492403 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72271.293375 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72271.293375 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79621.269891 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79621.269891 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72271.293375 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72271.293375 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79676.114069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79672.524401 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7334745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4752776 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6384952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879048 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 975 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333770 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1951 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27634358 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27636309 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828245760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 828308160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1929005 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20351521 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.094784 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.292917 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 7333064 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4752054 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6384201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879206 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 951 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332113 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629861 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27631764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 828100288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 828161152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1929031 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20348525 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.094800 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.292938 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18422516 90.52% 90.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 1929005 9.48% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18419494 90.52% 90.52% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 1929031 9.48% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20351521 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12939780000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 20348525 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12937495000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1462500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1426500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13819227000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13816978500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1189447 # Transaction distribution -system.membus.trans_dist::Writeback 1024254 # Transaction distribution +system.membus.trans_dist::ReadResp 1189321 # Transaction distribution +system.membus.trans_dist::Writeback 1024306 # Transaction distribution system.membus.trans_dist::CleanEvict 903687 # Transaction distribution -system.membus.trans_dist::ReadExReq 772262 # Transaction distribution -system.membus.trans_dist::ReadExResp 772262 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1189447 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851359 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5851359 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191101632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191101632 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 772416 # Transaction distribution +system.membus.trans_dist::ReadExResp 772416 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1189321 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5851467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5851467 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191106752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191106752 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3889650 # Request fanout histogram +system.membus.snoop_fanout::samples 3889730 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3889650 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3889730 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3889650 # Request fanout histogram -system.membus.reqLayer0.occupancy 8475841500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3889730 # Request fanout histogram +system.membus.reqLayer0.occupancy 8475633500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 10684260000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 10684578250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index a70b71696..97b7b2c5a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -78,7 +78,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -118,7 +118,7 @@ eventq_index=0 size=64 [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -167,7 +167,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini index ca8e0ac4e..cb09befab 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -759,7 +759,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout index b4e05a41a..1664fb28c 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 02:59:16 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x2c50960 info: Entering event queue @ 0. Starting simulation... spec_init Loading Input Data @@ -25,4 +27,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1121241432500 because target called exit() +Exiting @ tick 1116876142500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 27ca4a2ca..bd1131ae5 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.117365 # Number of seconds simulated -sim_ticks 1117365374500 # Number of ticks simulated -final_tick 1117365374500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.116876 # Number of seconds simulated +sim_ticks 1116876142500 # Number of ticks simulated +final_tick 1116876142500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 236504 # Simulator instruction rate (inst/s) -host_op_rate 254797 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171091237 # Simulator tick rate (ticks/s) -host_mem_usage 314716 # Number of bytes of host memory used -host_seconds 6530.82 # Real time elapsed on the host +host_inst_rate 161785 # Simulator instruction rate (inst/s) +host_op_rate 174299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 116987267 # Simulator tick rate (ticks/s) +host_mem_usage 309392 # Number of bytes of host memory used +host_seconds 9546.99 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130973248 # Number of bytes read from this memory -system.physmem.bytes_read::total 131024000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67225152 # Number of bytes written to this memory -system.physmem.bytes_written::total 67225152 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2046457 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2047250 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1050393 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1050393 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45421 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117216133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 117261554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45421 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45421 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60163984 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60163984 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60163984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117216133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 177425537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2047250 # Number of read requests accepted -system.physmem.writeReqs 1050393 # Number of write requests accepted -system.physmem.readBursts 2047250 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1050393 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 130939136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue -system.physmem.bytesWritten 67223488 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131024000 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67225152 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130931520 # Number of bytes read from this memory +system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67207936 # Number of bytes written to this memory +system.physmem.bytes_written::total 67207936 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2045805 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1050124 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1050124 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117230116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117275213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45097 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 60174923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 60174923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 60174923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117230116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177450137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2046592 # Number of read requests accepted +system.physmem.writeReqs 1050124 # Number of write requests accepted +system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1050124 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 130897216 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 84672 # Total number of bytes read from write queue +system.physmem.bytesWritten 67206464 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67207936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1323 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127156 # Per bank write bursts -system.physmem.perBankRdBursts::1 124552 # Per bank write bursts -system.physmem.perBankRdBursts::2 121687 # Per bank write bursts -system.physmem.perBankRdBursts::3 123679 # Per bank write bursts -system.physmem.perBankRdBursts::4 122821 # Per bank write bursts -system.physmem.perBankRdBursts::5 122785 # Per bank write bursts -system.physmem.perBankRdBursts::6 123231 # Per bank write bursts -system.physmem.perBankRdBursts::7 123758 # Per bank write bursts -system.physmem.perBankRdBursts::8 131446 # Per bank write bursts -system.physmem.perBankRdBursts::9 133531 # Per bank write bursts -system.physmem.perBankRdBursts::10 132174 # Per bank write bursts -system.physmem.perBankRdBursts::11 133285 # Per bank write bursts -system.physmem.perBankRdBursts::12 133312 # Per bank write bursts -system.physmem.perBankRdBursts::13 133367 # Per bank write bursts -system.physmem.perBankRdBursts::14 129415 # Per bank write bursts -system.physmem.perBankRdBursts::15 129725 # Per bank write bursts -system.physmem.perBankWrBursts::0 66071 # Per bank write bursts -system.physmem.perBankWrBursts::1 64336 # Per bank write bursts -system.physmem.perBankWrBursts::2 62582 # Per bank write bursts -system.physmem.perBankWrBursts::3 63010 # Per bank write bursts -system.physmem.perBankWrBursts::4 63074 # Per bank write bursts -system.physmem.perBankWrBursts::5 63174 # Per bank write bursts -system.physmem.perBankWrBursts::6 64441 # Per bank write bursts -system.physmem.perBankWrBursts::7 65447 # Per bank write bursts -system.physmem.perBankWrBursts::8 67324 # Per bank write bursts -system.physmem.perBankWrBursts::9 67820 # Per bank write bursts -system.physmem.perBankWrBursts::10 67591 # Per bank write bursts -system.physmem.perBankWrBursts::11 67884 # Per bank write bursts -system.physmem.perBankWrBursts::12 67359 # Per bank write bursts -system.physmem.perBankWrBursts::13 67795 # Per bank write bursts -system.physmem.perBankWrBursts::14 66531 # Per bank write bursts -system.physmem.perBankWrBursts::15 65928 # Per bank write bursts +system.physmem.perBankRdBursts::0 127284 # Per bank write bursts +system.physmem.perBankRdBursts::1 124662 # Per bank write bursts +system.physmem.perBankRdBursts::2 121597 # Per bank write bursts +system.physmem.perBankRdBursts::3 123658 # Per bank write bursts +system.physmem.perBankRdBursts::4 122617 # Per bank write bursts +system.physmem.perBankRdBursts::5 122675 # Per bank write bursts +system.physmem.perBankRdBursts::6 123246 # Per bank write bursts +system.physmem.perBankRdBursts::7 123759 # Per bank write bursts +system.physmem.perBankRdBursts::8 131397 # Per bank write bursts +system.physmem.perBankRdBursts::9 133511 # Per bank write bursts +system.physmem.perBankRdBursts::10 132080 # Per bank write bursts +system.physmem.perBankRdBursts::11 133309 # Per bank write bursts +system.physmem.perBankRdBursts::12 133252 # Per bank write bursts +system.physmem.perBankRdBursts::13 133368 # Per bank write bursts +system.physmem.perBankRdBursts::14 129308 # Per bank write bursts +system.physmem.perBankRdBursts::15 129546 # Per bank write bursts +system.physmem.perBankWrBursts::0 66136 # Per bank write bursts +system.physmem.perBankWrBursts::1 64410 # Per bank write bursts +system.physmem.perBankWrBursts::2 62576 # Per bank write bursts +system.physmem.perBankWrBursts::3 63006 # Per bank write bursts +system.physmem.perBankWrBursts::4 63000 # Per bank write bursts +system.physmem.perBankWrBursts::5 63100 # Per bank write bursts +system.physmem.perBankWrBursts::6 64443 # Per bank write bursts +system.physmem.perBankWrBursts::7 65435 # Per bank write bursts +system.physmem.perBankWrBursts::8 67311 # Per bank write bursts +system.physmem.perBankWrBursts::9 67795 # Per bank write bursts +system.physmem.perBankWrBursts::10 67548 # Per bank write bursts +system.physmem.perBankWrBursts::11 67883 # Per bank write bursts +system.physmem.perBankWrBursts::12 67328 # Per bank write bursts +system.physmem.perBankWrBursts::13 67793 # Per bank write bursts +system.physmem.perBankWrBursts::14 66483 # Per bank write bursts +system.physmem.perBankWrBursts::15 65854 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1117365281000 # Total gap between requests +system.physmem.totGap 1116876049000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2047250 # Read request sizes (log2) +system.physmem.readPktSize::6 2046592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1050393 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1917221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128684 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1050124 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1916546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,30 +144,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 61212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61641 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 61133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -193,106 +193,106 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1911200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.683951 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.443095 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1486351 77.77% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 305207 15.97% 93.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52508 2.75% 96.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21149 1.11% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13340 0.70% 98.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7581 0.40% 98.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5505 0.29% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5122 0.27% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14437 0.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1911200 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.403649 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 159.275472 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 61115 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 22 0.04% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1910492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.692259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.833601 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.494474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1485528 77.76% 77.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305524 15.99% 93.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52470 2.75% 96.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20903 1.09% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13406 0.70% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7575 0.40% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5481 0.29% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5100 0.27% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14505 0.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1910492 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61132 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.413630 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.636391 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 61087 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61162 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61162 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.173523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.138356 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.100510 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27168 44.42% 44.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1036 1.69% 46.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28675 46.88% 93.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3829 6.26% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 390 0.64% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 50 0.08% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 61132 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61132 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.177599 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.142637 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.096979 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 26963 44.11% 44.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1122 1.84% 45.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28754 47.04% 92.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3885 6.36% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 352 0.58% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 46 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61162 # Writes before turning the bus around for reads -system.physmem.totQLat 38200049000 # Total ticks spent queuing -system.physmem.totMemAccLat 76561124000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10229620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18671.29 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61132 # Writes before turning the bus around for reads +system.physmem.totQLat 38139021250 # Total ticks spent queuing +system.physmem.totMemAccLat 76487815000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10226345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18647.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37421.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 117.19 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 117.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37397.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 60.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.39 # Data bus utilization in percentage system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing -system.physmem.readRowHits 773325 # Number of row buffer hits during reads -system.physmem.writeRowHits 411756 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.20 # Row buffer hit rate for writes -system.physmem.avgGap 360714.67 # Average gap between requests -system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7043954400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3843427500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7719106200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3318634800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 72980394240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 421878506670 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 300346094250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 817130118060 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.305386 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 496942671500 # Time in different power states -system.physmem_0.memoryStateTime::REF 37311040000 # Time in different power states +system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing +system.physmem.readRowHits 773003 # Number of row buffer hits during reads +system.physmem.writeRowHits 411872 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes +system.physmem.avgGap 360664.67 # Average gap between requests +system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7041119400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3841880625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7718053200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 420554384415 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301217964750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 816640712790 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.183278 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 498392390000 # Time in different power states +system.physmem_0.memoryStateTime::REF 37294920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583108431500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 581188236250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7404702480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4040264250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8238734400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3487743360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 72980394240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 429447905460 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 293706270750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 819306014940 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.252744 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 485853174500 # Time in different power states -system.physmem_1.memoryStateTime::REF 37311040000 # Time in different power states +system.physmem_1.actEnergy 7402200120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4038898875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8234990400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3486207600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 429475728015 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 293392224750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 818979113280 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.276976 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 485326311500 # Time in different power states +system.physmem_1.memoryStateTime::REF 37294920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 594197830000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 594254742500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 239770012 # Number of BP lookups -system.cpu.branchPred.condPredicted 186474623 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14592511 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 129773424 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122091028 # Number of BTB hits +system.cpu.branchPred.lookups 239639069 # Number of BP lookups +system.cpu.branchPred.condPredicted 186342280 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 130646098 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122079384 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.080147 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15653619 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -412,68 +412,68 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2234730749 # number of cpu cycles simulated +system.cpu.numCycles 2233752285 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41613452 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41470092 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.446837 # CPI: cycles per instruction -system.cpu.ipc 0.691163 # IPC: instructions per cycle -system.cpu.tickCycles 1834912752 # Number of cycles that the object actually ticked -system.cpu.idleCycles 399817997 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9221614 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.621118 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624237491 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9225710 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.662813 # Average number of references to valid blocks. +system.cpu.cpi 1.446203 # CPI: cycles per instruction +system.cpu.ipc 0.691466 # IPC: instructions per cycle +system.cpu.tickCycles 1834122948 # Number of cycles that the object actually ticked +system.cpu.idleCycles 399629337 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9221039 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.616333 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624218905 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.665016 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.621118 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997466 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997466 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616333 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276880692 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276880692 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453906230 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453906230 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170331138 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170331138 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276841915 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276841915 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453887721 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453887721 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331061 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331061 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624237368 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624237368 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624237369 # number of overall hits -system.cpu.dcache.overall_hits::total 624237369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7335089 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7335089 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2254909 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2254909 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624218782 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624218782 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624218783 # number of overall hits +system.cpu.dcache.overall_hits::total 624218783 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254986 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254986 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9589998 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9589998 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9590000 # number of overall misses -system.cpu.dcache.overall_misses::total 9590000 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 191000565000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 191000565000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 109144177000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 109144177000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 300144742000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 300144742000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 300144742000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 300144742000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461241319 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461241319 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9589483 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9589483 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9589485 # number of overall misses +system.cpu.dcache.overall_misses::total 9589485 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 190949826000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 190949826000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060330000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109060330000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 300010156000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 300010156000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 300010156000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 300010156000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461222218 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461222218 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -482,28 +482,28 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633827366 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633827366 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633827369 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633827369 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015903 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015903 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013065 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013065 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 633808265 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633808265 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633808268 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633808268 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26039.297546 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26039.297546 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48402.918699 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 48402.918699 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31297.685568 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31297.685568 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31297.679041 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31297.679041 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26034.481438 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26034.481438 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48364.082970 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48364.082970 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.331649 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31285.331649 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.325124 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31285.325124 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -512,109 +512,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3684549 # number of writebacks -system.cpu.dcache.writebacks::total 3684549 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364078 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 364078 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364289 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364289 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364289 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364289 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334878 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334878 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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.874092 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.874092 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.874092 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.874092 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.874092 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.874092 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.048780 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.048780 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2014550 # number of replacements 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misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 787 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2045805 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2045805 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62419073500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62419073500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52090500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52090500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96214883500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96214883500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52090500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158633957000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158686047500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52090500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158633957000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158686047500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423781 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423781 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.960048 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.960048 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169758 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169758 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960048 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221821 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.221887 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960048 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221821 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.221887 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77967.480304 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77967.480304 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66169.609079 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66169.609079 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77306.067182 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77306.067182 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66169.609079 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77565.046322 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77560.632312 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66169.609079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77565.046322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77560.632312 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423701 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.959756 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77911.260104 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77911.260104 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66188.691233 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66188.691233 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77302.824732 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77302.824732 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 7335705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4734942 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6499660 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 826 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334879 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1684 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671440 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27673124 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826256576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 826309440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2014550 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 20462732 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.098450 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.297922 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4734688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334283 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669715 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27671384 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2013891 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 20460914 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.098426 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.297890 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 18448182 90.16% 90.16% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2014550 9.84% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 18447023 90.16% 90.16% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2013891 9.84% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 20462732 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12908640000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 20460914 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1239499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13838566996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 1245951 # Transaction distribution -system.membus.trans_dist::Writeback 1050393 # Transaction distribution -system.membus.trans_dist::CleanEvict 963109 # Transaction distribution -system.membus.trans_dist::ReadExReq 801299 # Transaction distribution -system.membus.trans_dist::ReadExResp 801299 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1245951 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6108002 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6108002 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198249152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198249152 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 1245436 # Transaction distribution +system.membus.trans_dist::Writeback 1050124 # Transaction distribution +system.membus.trans_dist::CleanEvict 962723 # Transaction distribution +system.membus.trans_dist::ReadExReq 801156 # Transaction distribution +system.membus.trans_dist::ReadExResp 801156 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198189824 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4060752 # Request fanout histogram +system.membus.snoop_fanout::samples 4059439 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4060752 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4060752 # Request fanout histogram -system.membus.reqLayer0.occupancy 8665729500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4059439 # Request fanout histogram +system.membus.reqLayer0.occupancy 8663029500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11195509250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11191724000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index eea4d6225..578352db1 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index bc5565f58..8ed495e8c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -80,7 +80,7 @@ dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -156,7 +156,7 @@ sys=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -266,7 +266,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index b2f63d5fa..1497b3733 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -84,7 +84,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -134,7 +134,7 @@ system=system port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -200,7 +200,7 @@ system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini index 459f492af..5ec95ce79 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini @@ -125,7 +125,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -548,7 +548,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -597,7 +597,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr index de77515a1..f0a9a7c93 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr @@ -1,3 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout index 4d57fab87..606ce3744 100644..100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-t gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 7 2014 10:41:53 -gem5 started May 7 2014 15:05:33 -gem5 executing on cz3212c2d7 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 20:55:41 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing + Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -25,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 51810251500 because target called exit() +122 123 124 Exiting @ tick 51910606500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index f4338fb5a..5fb393485 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052057 # Number of seconds simulated -sim_ticks 52057006500 # Number of ticks simulated -final_tick 52057006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.051911 # Number of seconds simulated +sim_ticks 51910606500 # Number of ticks simulated +final_tick 51910606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 338250 # Simulator instruction rate (inst/s) -host_op_rate 338250 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191596351 # Simulator tick rate (ticks/s) -host_mem_usage 300296 # Number of bytes of host memory used -host_seconds 271.70 # Real time elapsed on the host +host_inst_rate 229005 # Simulator instruction rate (inst/s) +host_op_rate 229005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 129351336 # Simulator tick rate (ticks/s) +host_mem_usage 295204 # Number of bytes of host memory used +host_seconds 401.31 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 202752 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137664 # Number of bytes read from this memory -system.physmem.bytes_read::total 340480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 340416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202752 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5320 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3896037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2644486 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6540522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3896037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3896037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3896037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2644486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6540522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5320 # Number of read requests accepted +system.physmem.num_reads::total 5319 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3905791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2651944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6557735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3905791 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3905791 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3905791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2651944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6557735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5319 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5320 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5319 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340480 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 340416 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340480 # Total read bytes from the system interface side +system.physmem.bytesReadSys 340416 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 469 # Per bank write bursts system.physmem.perBankRdBursts::1 295 # Per bank write bursts -system.physmem.perBankRdBursts::2 307 # Per bank write bursts +system.physmem.perBankRdBursts::2 308 # Per bank write bursts system.physmem.perBankRdBursts::3 524 # Per bank write bursts system.physmem.perBankRdBursts::4 224 # Per bank write bursts system.physmem.perBankRdBursts::5 238 # Per bank write bursts system.physmem.perBankRdBursts::6 222 # Per bank write bursts system.physmem.perBankRdBursts::7 289 # Per bank write bursts -system.physmem.perBankRdBursts::8 252 # Per bank write bursts +system.physmem.perBankRdBursts::8 251 # Per bank write bursts system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 255 # Per bank write bursts +system.physmem.perBankRdBursts::10 254 # Per bank write bursts system.physmem.perBankRdBursts::11 261 # Per bank write bursts system.physmem.perBankRdBursts::12 410 # Per bank write bursts system.physmem.perBankRdBursts::13 344 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52056919000 # Total gap between requests +system.physmem.totGap 51910519000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5320 # Read request sizes (log2) +system.physmem.readPktSize::6 5319 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 379 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 973 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.809866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.712248 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.458818 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 301 30.94% 30.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 209 21.48% 52.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 98 10.07% 62.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 92 9.46% 71.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 72 7.40% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 4.62% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.47% 86.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 1.95% 88.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 113 11.61% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 973 # Bytes accessed per row activation -system.physmem.totQLat 31528250 # Total ticks spent queuing -system.physmem.totMemAccLat 131278250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26600000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5926.36 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 346.541369 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 213.036393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.369108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 309 31.56% 31.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 207 21.14% 52.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 105 10.73% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 89 9.09% 72.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 71 7.25% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 31 3.17% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 27 2.76% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 27 2.76% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 113 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 979 # Bytes accessed per row activation +system.physmem.totQLat 35331250 # Total ticks spent queuing +system.physmem.totMemAccLat 135062500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6642.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24676.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25392.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.54 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.56 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4340 # Number of row buffer hits during reads +system.physmem.readRowHits 4332 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.58 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9785135.15 # Average gap between requests -system.physmem.pageHitRate 81.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3492720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1905750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19843200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9759450.84 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3507840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1914000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19835400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1761174315 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29685915000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34872054585 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.954967 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49382007750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1738100000 # Time in different power states +system.physmem_0.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1735578180 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29619604500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34770500880 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.907929 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49271576750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 931384250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 898679500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3825360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2087250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21231600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3848040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2099625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3399723600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1805818995 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29646744750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34879431555 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.096868 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49317281000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1738100000 # Time in different power states +system.physmem_1.refreshEnergy 3390060960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1825261695 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29540934750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34783421070 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.156857 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49142723000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1733160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 996955000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1030068000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11466165 # Number of BP lookups -system.cpu.branchPred.condPredicted 8229222 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 788767 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6698071 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5372970 # Number of BTB hits +system.cpu.branchPred.lookups 11441088 # Number of BP lookups +system.cpu.branchPred.condPredicted 8207826 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 765853 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 6077536 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5340604 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.216677 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1174312 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.874494 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1173808 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20431374 # DTB read hits -system.cpu.dtb.read_misses 46957 # DTB read misses +system.cpu.dtb.read_hits 20417089 # DTB read hits +system.cpu.dtb.read_misses 43350 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20478331 # DTB read accesses -system.cpu.dtb.write_hits 6580300 # DTB write hits -system.cpu.dtb.write_misses 270 # DTB write misses +system.cpu.dtb.read_accesses 20460439 # DTB read accesses +system.cpu.dtb.write_hits 6579898 # DTB write hits +system.cpu.dtb.write_misses 278 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580570 # DTB write accesses -system.cpu.dtb.data_hits 27011674 # DTB hits -system.cpu.dtb.data_misses 47227 # DTB misses +system.cpu.dtb.write_accesses 6580176 # DTB write accesses +system.cpu.dtb.data_hits 26996987 # DTB hits +system.cpu.dtb.data_misses 43628 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27058901 # DTB accesses -system.cpu.itb.fetch_hits 23067346 # ITB hits -system.cpu.itb.fetch_misses 89 # ITB misses +system.cpu.dtb.data_accesses 27040615 # DTB accesses +system.cpu.itb.fetch_hits 22953519 # ITB hits +system.cpu.itb.fetch_misses 90 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23067435 # ITB accesses +system.cpu.itb.fetch_accesses 22953609 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,67 +293,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104114013 # number of cpu cycles simulated +system.cpu.numCycles 103821213 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2234090 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2183676 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.132867 # CPI: cycles per instruction -system.cpu.ipc 0.882716 # IPC: instructions per cycle -system.cpu.tickCycles 102384742 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1729271 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.129681 # CPI: cycles per instruction +system.cpu.ipc 0.885205 # IPC: instructions per cycle +system.cpu.tickCycles 102104321 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1716892 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.483845 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26587292 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1447.424804 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26573200 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11922.552466 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11916.233184 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.483845 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353634 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353634 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1447.424804 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353375 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353375 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53183674 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53183674 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20089099 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20089099 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53155492 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53155492 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20075007 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20075007 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498193 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498193 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26587292 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26587292 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26587292 # number of overall hits -system.cpu.dcache.overall_hits::total 26587292 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 520 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 520 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 26573200 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26573200 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26573200 # number of overall hits +system.cpu.dcache.overall_hits::total 26573200 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 521 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2910 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 2910 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3430 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses -system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 40189000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 40189000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 213917000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 213917000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 254106000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 254106000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 254106000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 254106000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20089619 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20089619 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3431 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3431 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3431 # number of overall misses +system.cpu.dcache.overall_misses::total 3431 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40212500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40212500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 214035000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 214035000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 254247500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 254247500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 254247500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 254247500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20075528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20075528 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26590722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26590722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26590722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26590722 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26576631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26576631 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26576631 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26576631 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77286.538462 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77286.538462 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73510.996564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73510.996564 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 74083.381924 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 74083.381924 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 74083.381924 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77183.301344 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77183.301344 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73551.546392 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73551.546392 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74103.031186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74103.031186 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74103.031186 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,14 +380,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 36 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 36 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1165 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1165 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1200 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1200 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1200 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1201 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1201 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1201 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1201 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 485 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 485 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1745 # number of WriteReq MSHR misses @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36729500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36729500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 130660500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167390000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 167390000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167390000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 167390000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37107000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37107000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 131707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 131707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 168814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 168814500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 168814500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 168814500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,69 +412,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75730.927835 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75730.927835 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74877.077364 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74877.077364 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75062.780269 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75062.780269 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76509.278351 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76509.278351 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75477.077364 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75477.077364 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75701.569507 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75701.569507 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13848 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.495432 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23051532 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15813 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1457.758300 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 13850 # number of replacements +system.cpu.icache.tags.tagsinuse 1640.456656 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22937703 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15815 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1450.376415 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.495432 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801511 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.456656 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.801004 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.801004 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 668 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 950 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 671 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 946 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46150505 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46150505 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23051532 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23051532 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23051532 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23051532 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23051532 # number of overall hits -system.cpu.icache.overall_hits::total 23051532 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15814 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15814 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15814 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15814 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15814 # number of overall misses -system.cpu.icache.overall_misses::total 15814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 406574500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 406574500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 406574500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 406574500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 406574500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 406574500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23067346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23067346 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23067346 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23067346 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23067346 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23067346 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25709.782471 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25709.782471 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25709.782471 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25709.782471 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25709.782471 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25709.782471 # average overall miss latency +system.cpu.icache.tags.tag_accesses 45922853 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45922853 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22937703 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22937703 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22937703 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22937703 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22937703 # number of overall hits +system.cpu.icache.overall_hits::total 22937703 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15816 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15816 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15816 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15816 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15816 # number of overall misses +system.cpu.icache.overall_misses::total 15816 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 408931500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 408931500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 408931500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 408931500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 408931500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 408931500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22953519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22953519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22953519 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22953519 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22953519 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22953519 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25855.557663 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25855.557663 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25855.557663 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25855.557663 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25855.557663 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25855.557663 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,129 +483,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15814 # 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number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3168 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 2151 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5320 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3169 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5319 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5320 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 110580000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 110580000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 202589500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 202589500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31119500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31119500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 202589500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 141699500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 344289000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 202589500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 141699500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 344289000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 5319 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111627000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111627000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 204920000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 204920000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31497000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31497000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204920000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 143124000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 348044000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204920000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 143124000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 348044000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985100 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985100 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200405 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200316 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.890722 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294851 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200405 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.294763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200316 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294851 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64328.097731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64328.097731 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63928.526349 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63928.526349 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72035.879630 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72035.879630 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63928.526349 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65876.104138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64715.977444 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.294763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64937.172775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64937.172775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64684.343434 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64684.343434 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72909.722222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72909.722222 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64684.343434 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66538.354254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65434.104155 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 16298 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 16300 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 13898 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 13900 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1745 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15813 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15815 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 485 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45474 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45480 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4617 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 50097 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1012160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1161600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1161728 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 32048 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 32052 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32048 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 32052 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 32048 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 16131000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 32052 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 16133000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23719500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 23722500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3345000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3601 # Transaction distribution +system.membus.trans_dist::ReadResp 3600 # Transaction distribution system.membus.trans_dist::ReadExReq 1719 # Transaction distribution system.membus.trans_dist::ReadExResp 1719 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3601 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10640 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10640 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340480 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 3600 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10638 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10638 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 340416 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5320 # Request fanout histogram +system.membus.snoop_fanout::samples 5319 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5320 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5319 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5320 # Request fanout histogram -system.membus.reqLayer0.occupancy 6410500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5319 # Request fanout histogram +system.membus.reqLayer0.occupancy 6413000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28166750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28165750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 4e01cb733..1d39a1715 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -150,7 +150,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -497,7 +497,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -546,7 +546,7 @@ eventq_index=0 size=48 [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 462b428af..a140d0429 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,13 +1,13 @@ +Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 07:55:25 -gem5 started Apr 22 2015 08:19:48 -gem5 executing on phenom -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing +gem5 compiled Sep 14 2015 20:54:01 +gem5 started Sep 14 2015 21:18:12 +gem5 executing on ribera.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -24,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 22228749500 because target called exit() +122 123 124 Exiting @ tick 21919473500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 2afb0af07..f7c0c31d6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022173 # Number of seconds simulated -sim_ticks 22172615500 # Number of ticks simulated -final_tick 22172615500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.021919 # Number of seconds simulated +sim_ticks 21919473500 # Number of ticks simulated +final_tick 21919473500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207826 # Simulator instruction rate (inst/s) -host_op_rate 207826 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54740698 # Simulator tick rate (ticks/s) -host_mem_usage 301824 # Number of bytes of host memory used -host_seconds 405.05 # Real time elapsed on the host +host_inst_rate 134628 # Simulator instruction rate (inst/s) +host_op_rate 134628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35055621 # Simulator tick rate (ticks/s) +host_mem_usage 296224 # Number of bytes of host memory used +host_seconds 625.28 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138432 # Number of bytes read from this memory -system.physmem.bytes_read::total 334656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196224 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3066 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5229 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8849836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6243377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15093213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8849836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8849836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8849836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6243377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15093213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5229 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 195776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138496 # Number of bytes read from this memory +system.physmem.bytes_read::total 334272 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195776 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3059 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2164 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5223 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8931601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6318400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15250001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8931601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8931601 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8931601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6318400 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15250001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5223 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5229 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5223 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334656 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334272 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334656 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334272 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 472 # Per bank write bursts +system.physmem.perBankRdBursts::0 470 # Per bank write bursts system.physmem.perBankRdBursts::1 290 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 526 # Per bank write bursts -system.physmem.perBankRdBursts::4 217 # Per bank write bursts -system.physmem.perBankRdBursts::5 224 # Per bank write bursts -system.physmem.perBankRdBursts::6 217 # Per bank write bursts -system.physmem.perBankRdBursts::7 285 # Per bank write bursts +system.physmem.perBankRdBursts::3 523 # Per bank write bursts +system.physmem.perBankRdBursts::4 220 # Per bank write bursts +system.physmem.perBankRdBursts::5 223 # Per bank write bursts +system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::7 288 # Per bank write bursts system.physmem.perBankRdBursts::8 239 # Per bank write bursts system.physmem.perBankRdBursts::9 278 # Per bank write bursts -system.physmem.perBankRdBursts::10 248 # Per bank write bursts -system.physmem.perBankRdBursts::11 253 # Per bank write bursts -system.physmem.perBankRdBursts::12 398 # Per bank write bursts +system.physmem.perBankRdBursts::10 249 # Per bank write bursts +system.physmem.perBankRdBursts::11 251 # Per bank write bursts +system.physmem.perBankRdBursts::12 396 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 493 # Per bank write bursts +system.physmem.perBankRdBursts::14 489 # Per bank write bursts system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22172520500 # Total gap between requests +system.physmem.totGap 21919378500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5229 # Read request sizes (log2) +system.physmem.readPktSize::6 5223 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3272 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 237 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.112399 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.773233 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 362.004147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 257 29.78% 29.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 196 22.71% 52.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 76 8.81% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.60% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37 4.29% 72.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 34 3.94% 76.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 3.36% 79.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 50 5.79% 85.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 127 14.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 863 # Bytes accessed per row activation -system.physmem.totQLat 43111750 # Total ticks spent queuing -system.physmem.totMemAccLat 141155500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26145000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8244.74 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 387.497674 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 231.928894 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 358.454487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 254 29.53% 29.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 187 21.74% 51.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 83 9.65% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 58 6.74% 67.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 36 4.19% 71.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 34 3.95% 75.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 4.65% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 50 5.81% 86.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 118 13.72% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 860 # Bytes accessed per row activation +system.physmem.totQLat 44538500 # Total ticks spent queuing +system.physmem.totMemAccLat 142469750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8527.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26994.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27277.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.09 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.25 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4356 # Number of row buffer hits during reads +system.physmem.readRowHits 4358 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.30 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4240298.43 # Average gap between requests -system.physmem.pageHitRate 83.30 # Row buffer hit rate, read and write combined +system.physmem.avgGap 4196702.76 # Average gap between requests +system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3160080 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1724250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19492200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 19741800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1447870320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 926205255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12488167500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14886619605 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.545103 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20772765250 # Time in different power states -system.physmem_0.memoryStateTime::REF 740220000 # Time in different power states +system.physmem_0.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 935708580 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12330335250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14722266360 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.680556 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20510216250 # Time in different power states +system.physmem_0.memoryStateTime::REF 731900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 654868750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 676644750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3311280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1806750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20810400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20872800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1447870320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 909735390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12502614750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14886148890 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.523868 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20796420250 # Time in different power states -system.physmem_1.memoryStateTime::REF 740220000 # Time in different power states +system.physmem_1.refreshEnergy 1431596400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 913464900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12349847250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14720946120 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.620322 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20542312250 # Time in different power states +system.physmem_1.memoryStateTime::REF 731900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 631087250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 644355250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16296711 # Number of BP lookups -system.cpu.branchPred.condPredicted 11841199 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 977322 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9230824 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7630427 # Number of BTB hits +system.cpu.branchPred.lookups 16112018 # Number of BP lookups +system.cpu.branchPred.condPredicted 11701868 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926184 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8628002 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7529875 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.662469 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1605836 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 456 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.272523 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1595504 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 407 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24148862 # DTB read hits -system.cpu.dtb.read_misses 238971 # DTB read misses +system.cpu.dtb.read_hits 24062707 # DTB read hits +system.cpu.dtb.read_misses 205786 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24387833 # DTB read accesses -system.cpu.dtb.write_hits 7164238 # DTB write hits -system.cpu.dtb.write_misses 1251 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7165489 # DTB write accesses -system.cpu.dtb.data_hits 31313100 # DTB hits -system.cpu.dtb.data_misses 240222 # DTB misses -system.cpu.dtb.data_acv 3 # DTB access violations -system.cpu.dtb.data_accesses 31553322 # DTB accesses -system.cpu.itb.fetch_hits 16134293 # ITB hits -system.cpu.itb.fetch_misses 87 # ITB misses +system.cpu.dtb.read_accesses 24268493 # DTB read accesses +system.cpu.dtb.write_hits 7162407 # DTB write hits +system.cpu.dtb.write_misses 1203 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7163610 # DTB write accesses +system.cpu.dtb.data_hits 31225114 # DTB hits +system.cpu.dtb.data_misses 206989 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 31432103 # DTB accesses +system.cpu.itb.fetch_hits 15925407 # ITB hits +system.cpu.itb.fetch_misses 77 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 16134380 # ITB accesses +system.cpu.itb.fetch_accesses 15925484 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,239 +293,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 44345232 # number of cpu cycles simulated +system.cpu.numCycles 43838948 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16871286 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 139358892 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16296711 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9236263 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26208155 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2034698 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 152 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2379 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 16134293 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 382507 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44099332 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.160113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.432013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16632320 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 137954260 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16112018 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9125379 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 25989721 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1930958 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 137 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2266 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 15925407 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 365179 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 43589931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.164819 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.433135 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19660436 44.58% 44.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2660444 6.03% 50.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1334517 3.03% 53.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1958294 4.44% 58.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3041312 6.90% 64.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1304304 2.96% 67.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1378179 3.13% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 896078 2.03% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11865768 26.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19407451 44.52% 44.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2621129 6.01% 50.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1337584 3.07% 53.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1925835 4.42% 58.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3007413 6.90% 64.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1288266 2.96% 67.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1362128 3.12% 71.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 884292 2.03% 73.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11755833 26.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44099332 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367496 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.142590 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13096074 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8205573 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19698619 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2093424 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1005642 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2679978 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12191 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133453867 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 48806 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1005642 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14231650 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4726220 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9532 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20537255 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3589033 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 129931841 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 72505 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1962504 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1321371 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 55153 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 95440121 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 168856219 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 161261081 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7595137 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 43589931 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367527 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.146842 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12848398 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8248987 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19437203 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2101434 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 953909 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2651089 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 11974 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 132128383 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 49953 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 953909 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13970899 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4649700 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10898 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20300581 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3703944 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 128750721 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69632 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2039237 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1388591 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 55010 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 94550726 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 167277672 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 159796203 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7481468 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27012760 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 775 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8114171 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 27101259 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8744711 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3477099 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1649521 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112647261 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1499 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 100144647 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120164 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 28469050 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21866284 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1110 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44099332 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.270888 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.097444 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 26123365 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 949 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8314647 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26912240 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8709829 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3514186 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1623457 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111857121 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1283 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 99743085 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115820 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27678694 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21106490 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 894 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 43589931 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.288214 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.099779 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11543505 26.18% 26.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7764590 17.61% 43.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7534716 17.09% 60.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5714671 12.96% 73.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4493321 10.19% 84.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2994712 6.79% 90.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2021459 4.58% 95.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1167850 2.65% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 864508 1.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11253194 25.82% 25.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7641118 17.53% 43.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7479948 17.16% 60.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5719610 13.12% 73.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4459621 10.23% 83.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2975044 6.83% 90.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2026173 4.65% 95.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1169285 2.68% 98.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 865938 1.99% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44099332 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 43589931 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 476525 19.98% 19.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 437 0.02% 20.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34852 1.46% 21.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 11487 0.48% 21.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1008602 42.30% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 692685 29.05% 93.29% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159938 6.71% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 482162 20.24% 20.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 537 0.02% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34275 1.44% 21.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 12320 0.52% 22.22% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1010506 42.41% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 685066 28.75% 93.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 157661 6.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60907964 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491070 0.49% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2843610 2.84% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115460 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2441189 2.44% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314170 0.31% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765827 0.76% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24997693 24.96% 92.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7267338 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60678292 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 490564 0.49% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2838989 2.85% 64.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115355 0.12% 64.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2438911 2.45% 66.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 313691 0.31% 67.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766049 0.77% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24838081 24.90% 92.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7262827 7.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 100144647 # Type of FU issued -system.cpu.iq.rate 2.258296 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2384526 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023811 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231229628 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131456710 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90023404 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15663688 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9702849 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7180664 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 94162135 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8367031 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1912696 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 99743085 # Type of FU issued +system.cpu.iq.rate 2.275216 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2382527 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023887 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 229948900 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 130065304 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 89786778 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15625548 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9512793 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7169302 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 93776538 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8349067 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1917366 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7105061 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11423 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 42083 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2243608 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6916042 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11056 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 41363 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2208726 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42789 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1512 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42784 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1527 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1005642 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3713444 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 450339 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 123646937 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 273080 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 27101259 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8744711 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1499 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 41770 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 401874 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 42083 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 559712 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 524057 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1083769 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98766968 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24388350 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1377679 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 953909 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3616734 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 464700 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 122788755 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 239982 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26912240 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8709829 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1283 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 38454 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 420547 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 41363 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 525246 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 502956 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1028202 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98432500 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24268972 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1310585 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10998177 # number of nop insts executed -system.cpu.iew.exec_refs 31553871 # number of memory reference insts executed -system.cpu.iew.exec_branches 12528994 # Number of branches executed -system.cpu.iew.exec_stores 7165521 # Number of stores executed -system.cpu.iew.exec_rate 2.227229 # Inst execution rate -system.cpu.iew.wb_sent 97952857 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97204068 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67107593 # num instructions producing a value -system.cpu.iew.wb_consumers 95129025 # num instructions consuming a value +system.cpu.iew.exec_nop 10930351 # number of nop insts executed +system.cpu.iew.exec_refs 31432616 # number of memory reference insts executed +system.cpu.iew.exec_branches 12487704 # Number of branches executed +system.cpu.iew.exec_stores 7163644 # Number of stores executed +system.cpu.iew.exec_rate 2.245321 # Inst execution rate +system.cpu.iew.wb_sent 97645732 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 96956080 # cumulative count of insts written-back +system.cpu.iew.wb_producers 66985594 # num instructions producing a value +system.cpu.iew.wb_consumers 95002941 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.191985 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705438 # average fanout of values written-back +system.cpu.iew.wb_rate 2.211642 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705090 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 31745312 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 30887581 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 965615 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39467684 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.328565 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.908680 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 914614 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39095972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.350704 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.921132 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14970260 37.93% 37.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8589907 21.76% 59.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3909988 9.91% 69.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1952996 4.95% 74.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1374473 3.48% 78.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1034336 2.62% 80.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 694993 1.76% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 731194 1.85% 84.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6209537 15.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 14698430 37.60% 37.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8547015 21.86% 59.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3864183 9.88% 69.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1929221 4.93% 74.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1372371 3.51% 77.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1004316 2.57% 80.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 690404 1.77% 82.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 733733 1.88% 84.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6256299 16.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39467684 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39095972 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,350 +570,350 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6209537 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 156905474 # The number of ROB reads -system.cpu.rob.rob_writes 251988235 # The number of ROB writes -system.cpu.timesIdled 4640 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 245900 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6256299 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 155629269 # The number of ROB reads +system.cpu.rob.rob_writes 250130763 # The number of ROB writes +system.cpu.timesIdled 4629 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 249017 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.526792 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.526792 # CPI: Total CPI of All Threads -system.cpu.ipc 1.898281 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.898281 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133413106 # number of integer regfile reads -system.cpu.int_regfile_writes 73139309 # number of integer regfile writes -system.cpu.fp_regfile_reads 6258544 # number of floating regfile reads -system.cpu.fp_regfile_writes 6168597 # number of floating regfile writes -system.cpu.misc_regfile_reads 718994 # number of misc regfile reads +system.cpu.cpi 0.520778 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.520778 # CPI: Total CPI of All Threads +system.cpu.ipc 1.920204 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.920204 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 132982273 # number of integer regfile reads +system.cpu.int_regfile_writes 72919705 # number of integer regfile writes +system.cpu.fp_regfile_reads 6252521 # number of floating regfile reads +system.cpu.fp_regfile_writes 6155462 # number of floating regfile writes +system.cpu.misc_regfile_reads 719143 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 159 # number of replacements -system.cpu.dcache.tags.tagsinuse 1454.905467 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28683797 # Total number of references to valid blocks. +system.cpu.dcache.tags.replacements 158 # number of replacements +system.cpu.dcache.tags.tagsinuse 1457.350779 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28592916 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2244 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12782.440731 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12741.941176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1454.905467 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355202 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355202 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2085 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1386 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509033 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57388820 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57388820 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22190893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22190893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492625 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492625 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 279 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 279 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28683518 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28683518 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28683518 # number of overall hits -system.cpu.dcache.overall_hits::total 28683518 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1012 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1012 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8478 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8478 # number of WriteReq misses +system.cpu.dcache.tags.occ_blocks::cpu.data 1457.350779 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.355799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.355799 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2086 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57207152 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57207152 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22099846 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22099846 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492613 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492613 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28592459 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28592459 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28592459 # number of overall hits +system.cpu.dcache.overall_hits::total 28592459 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1047 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1047 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8490 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8490 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9490 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9490 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9490 # number of overall misses -system.cpu.dcache.overall_misses::total 9490 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 67994000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 67994000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 547632747 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 547632747 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9537 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9537 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9537 # number of overall misses +system.cpu.dcache.overall_misses::total 9537 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69532500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69532500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 543709251 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 543709251 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 615626747 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 615626747 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 615626747 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 615626747 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22191905 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22191905 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 613241751 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 613241751 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 613241751 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 613241751 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22100893 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22100893 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 280 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 280 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28693008 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28693008 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28693008 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28693008 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003571 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003571 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000331 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000331 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000331 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000331 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67187.747036 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67187.747036 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64594.567941 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64594.567941 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28601996 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28601996 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28601996 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28601996 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001306 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001306 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002183 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002183 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000333 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000333 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66411.174785 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66411.174785 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64041.136749 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64041.136749 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64871.100843 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64871.100843 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64871.100843 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64871.100843 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33428 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 398 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.989950 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64301.326518 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64301.326518 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64301.326518 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32746 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 127 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 389 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 84.179949 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 63.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # 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number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 108 # number of writebacks +system.cpu.dcache.writebacks::total 108 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 540 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6754 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6754 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7294 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7294 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7294 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7294 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 507 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 507 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1736 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1736 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 2243 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 2243 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2243 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2243 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39245500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39245500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 137397495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 137397495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39700000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 39700000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135151495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135151495 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 84000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 84000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176642995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 176642995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176642995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 176642995 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 174851495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 174851495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 174851495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 174851495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003571 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003571 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002183 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002183 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77103.143418 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77103.143418 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79237.309689 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79237.309689 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78303.747535 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78303.747535 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77852.243664 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77852.243664 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 84000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 84000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78753.007133 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78753.007133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78753.007133 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78753.007133 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77954.300045 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77954.300045 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9772 # number of replacements -system.cpu.icache.tags.tagsinuse 1599.606485 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 16119452 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11709 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1376.671962 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9477 # number of replacements +system.cpu.icache.tags.tagsinuse 1601.339074 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 15910864 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11414 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1393.977922 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1599.606485 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781058 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1601.339074 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781904 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781904 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 770 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 934 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 32280293 # Number of tag accesses -system.cpu.icache.tags.data_accesses 32280293 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 16119452 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 16119452 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 16119452 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 16119452 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 16119452 # number of overall hits -system.cpu.icache.overall_hits::total 16119452 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14840 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14840 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14840 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14840 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14840 # number of overall misses -system.cpu.icache.overall_misses::total 14840 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 447595000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 447595000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 447595000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 447595000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 447595000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 447595000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 16134292 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 16134292 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 16134292 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 16134292 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 16134292 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30161.388140 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30161.388140 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 223 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 31862226 # Number of tag accesses +system.cpu.icache.tags.data_accesses 31862226 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 15910864 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 15910864 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 15910864 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 15910864 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 15910864 # number of overall hits +system.cpu.icache.overall_hits::total 15910864 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14542 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14542 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14542 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14542 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14542 # number of overall misses +system.cpu.icache.overall_misses::total 14542 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 447928500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 447928500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 447928500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 447928500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 447928500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 447928500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 15925406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 15925406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 15925406 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 15925406 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 15925406 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 15925406 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000913 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000913 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000913 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000913 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000913 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000913 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30802.399945 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 30802.399945 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 30802.399945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 30802.399945 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 30802.399945 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 837 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 209.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3131 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3131 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3131 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3131 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3131 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3131 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11709 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11709 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11709 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11709 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11709 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11709 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 339198000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 339198000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 339198000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 339198000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 339198000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 339198000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000726 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000726 # 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mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.261850 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.892157 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.892157 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.374758 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.261850 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963904 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.374758 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68677.400468 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68677.400468 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65302.674494 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65302.674494 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73448.351648 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73448.351648 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65302.674494 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69680.998613 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67113.788487 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65302.674494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69680.998613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67113.788487 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1710 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1710 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3059 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3059 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 454 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 454 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3059 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2164 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5223 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3059 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2164 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5223 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115032500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115032500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 203043500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 203043500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 33898500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 33898500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 203043500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 148931000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 351974500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 203043500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 148931000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 351974500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.268004 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.893701 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.893701 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.382413 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.268004 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964349 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.382413 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67270.467836 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67270.467836 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66375.776398 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66375.776398 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74666.299559 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74666.299559 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66375.776398 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68822.088725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67389.335631 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 12219 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 9822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11709 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 510 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 33190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4647 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 37837 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 749376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 899968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadResp 11922 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 108 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 9527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1736 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 11414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 508 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32305 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 36951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730496 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 881024 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23884 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 23293 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 23884 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 23293 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23884 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12051000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23293 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 11754500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17563500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 17121000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3366000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3521 # Transaction distribution -system.membus.trans_dist::ReadExReq 1708 # Transaction distribution -system.membus.trans_dist::ReadExResp 1708 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3521 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10458 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10458 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334656 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3513 # Transaction distribution +system.membus.trans_dist::ReadExReq 1710 # Transaction distribution +system.membus.trans_dist::ReadExResp 1710 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3513 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10446 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334272 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5229 # Request fanout histogram +system.membus.snoop_fanout::samples 5223 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5229 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5223 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5229 # Request fanout histogram -system.membus.reqLayer0.occupancy 6267000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5223 # Request fanout histogram +system.membus.reqLayer0.occupancy 6235500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27480000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 27428750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini index 29e916711..5611a7dae 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini @@ -127,7 +127,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -586,7 +586,7 @@ eventq_index=0 opClass=InstPrefetch [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -696,7 +696,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -759,7 +759,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout index c2579128c..87bca4e9e 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout @@ -1,14 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2015 20:30:55 -gem5 started Mar 15 2015 20:31:14 -gem5 executing on zizzer2 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav -Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2 +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 04:10:24 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing + Global frequency set at 1000000000000 ticks per second - 0: system.cpu.isa: ISA system set to: 0 0x3623b60 info: Entering event queue @ 0. Starting simulation... TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 @@ -24,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 131756455500 because target called exit() +122 123 124 Exiting @ tick 130772636500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index f9aa76ee3..396e2f8dd 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131585 # Number of seconds simulated -sim_ticks 131584694500 # Number of ticks simulated -final_tick 131584694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.130773 # Number of seconds simulated +sim_ticks 130772636500 # Number of ticks simulated +final_tick 130772636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 242795 # Simulator instruction rate (inst/s) -host_op_rate 255945 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 185402255 # Simulator tick rate (ticks/s) -host_mem_usage 318276 # Number of bytes of host memory used -host_seconds 709.73 # Real time elapsed on the host +host_inst_rate 167747 # Simulator instruction rate (inst/s) +host_op_rate 176832 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 127303889 # Simulator tick rate (ticks/s) +host_mem_usage 312696 # Number of bytes of host memory used +host_seconds 1027.25 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 138368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 138112 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory -system.physmem.bytes_read::total 247680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138368 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2162 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 247424 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138112 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2158 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3870 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1051551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 830735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1882286 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1051551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1051551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1051551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 830735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1882286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3870 # Number of read requests accepted +system.physmem.num_reads::total 3866 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1056123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 835894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1892017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1056123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1056123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1056123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 835894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1892017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3866 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3870 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3866 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247680 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247424 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247680 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247424 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -45,14 +45,14 @@ system.physmem.perBankRdBursts::0 305 # Pe system.physmem.perBankRdBursts::1 217 # Per bank write bursts system.physmem.perBankRdBursts::2 135 # Per bank write bursts system.physmem.perBankRdBursts::3 313 # Per bank write bursts -system.physmem.perBankRdBursts::4 308 # Per bank write bursts +system.physmem.perBankRdBursts::4 306 # Per bank write bursts system.physmem.perBankRdBursts::5 305 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts system.physmem.perBankRdBursts::7 222 # Per bank write bursts -system.physmem.perBankRdBursts::8 249 # Per bank write bursts +system.physmem.perBankRdBursts::8 248 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 201 # Per bank write bursts +system.physmem.perBankRdBursts::11 200 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131584601000 # Total gap between requests +system.physmem.totGap 130772543000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3870 # Read request sizes (log2) +system.physmem.readPktSize::6 3866 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.614035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.051598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 274.679496 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 270 29.61% 29.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 347 38.05% 67.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 87 9.54% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 54 5.92% 83.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 40 4.39% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 20 2.19% 89.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 1.97% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation -system.physmem.totQLat 27229750 # Total ticks spent queuing -system.physmem.totMemAccLat 99792250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7036.11 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 905 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 271.628729 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.806384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.022098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 259 28.62% 28.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 38.90% 67.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 86 9.50% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 6.52% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 34 3.76% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 21 2.32% 89.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 17 1.88% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 17 1.88% 93.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 60 6.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 905 # Bytes accessed per row activation +system.physmem.totQLat 28055750 # Total ticks spent queuing +system.physmem.totMemAccLat 100543250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7257.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25786.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26007.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage @@ -216,49 +216,49 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2952 # Number of row buffer hits during reads +system.physmem.readRowHits 2957 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.28 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34001188.89 # Average gap between requests -system.physmem.pageHitRate 76.28 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3129840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1707750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 33826317.38 # Average gap between requests +system.physmem.pageHitRate 76.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3099600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1691250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16161600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3579629355 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75808025250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88002824835 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.815686 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126113612750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4393740000 # Time in different power states +system.physmem_0.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3568801635 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75331661250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 87462680535 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.826718 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 125318913500 # Time in different power states +system.physmem_0.memoryStateTime::REF 4366700000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1075043250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1084715250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3749760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2046000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2033625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13782600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8594155440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3571830900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75814874250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88000431150 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.797424 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126123074750 # Time in different power states -system.physmem_1.memoryStateTime::REF 4393740000 # Time in different power states +system.physmem_1.refreshEnergy 8541265200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3564422325 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75335511000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 87460741830 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.811822 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 125325774500 # Time in different power states +system.physmem_1.memoryStateTime::REF 4366700000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1063297750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1078159500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49889701 # Number of BP lookups -system.cpu.branchPred.condPredicted 39633557 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5745356 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24337782 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23279998 # Number of BTB hits +system.cpu.branchPred.lookups 49732170 # Number of BP lookups +system.cpu.branchPred.condPredicted 39495980 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5592247 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24154061 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23128262 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.653737 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1903300 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 140 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.753099 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1888632 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,26 +377,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263169389 # number of cpu cycles simulated +system.cpu.numCycles 261545273 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11983759 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11660914 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.527233 # CPI: cycles per instruction -system.cpu.ipc 0.654779 # IPC: instructions per cycle -system.cpu.tickCycles 256740818 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6428571 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.517808 # CPI: cycles per instruction +system.cpu.ipc 0.658845 # IPC: instructions per cycle +system.cpu.tickCycles 255251954 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6293319 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.711326 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40793911 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.707601 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40756382 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22538.072376 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22517.338122 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.711326 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336355 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336355 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.707601 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336354 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336354 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id @@ -404,72 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81594514 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81594514 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28385993 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28385993 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362640 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362640 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 464 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 464 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 81519460 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81519460 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28348467 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28348467 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362639 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362639 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40748633 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40748633 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40749097 # number of overall hits -system.cpu.dcache.overall_hits::total 40749097 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 793 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 793 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1647 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1647 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40711106 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40711106 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40711568 # number of overall hits +system.cpu.dcache.overall_hits::total 40711568 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 794 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 794 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1648 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1648 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2440 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2440 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2441 # number of overall misses -system.cpu.dcache.overall_misses::total 2441 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57382000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57382000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 126740000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 126740000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 184122000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 184122000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 184122000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 184122000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28386786 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28386786 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2442 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2442 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2443 # number of overall misses +system.cpu.dcache.overall_misses::total 2443 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58025500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58025500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 126322500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 126322500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184348000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184348000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184348000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184348000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28349261 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28349261 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 465 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 465 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40751073 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40751073 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40751538 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40751538 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40713548 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40713548 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40714011 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40714011 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002151 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002151 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72360.655738 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72360.655738 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76952.034001 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76952.034001 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75459.836066 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75459.836066 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75428.922573 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75428.922573 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73079.974811 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 73079.974811 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76652.002427 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76652.002427 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75490.581491 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75490.581491 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75459.680720 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75459.680720 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -480,14 +480,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 82 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 549 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 549 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 631 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 631 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 631 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 631 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 550 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 550 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 633 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 633 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 633 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 633 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses @@ -498,91 +498,91 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1809 system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51034000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 51034000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85245500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 85245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51768000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51768000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85075000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85075000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 70000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 70000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136279500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 136279500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136349500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 136349500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136843000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136843000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136913000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136913000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002151 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002151 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71777.777778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71777.777778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77637.067395 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77637.067395 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72810.126582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72810.126582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77481.785064 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77481.785064 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75334.162521 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75334.162521 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75331.215470 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75331.215470 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75645.660586 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75645.660586 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75642.541436 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75642.541436 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2889 # number of replacements -system.cpu.icache.tags.tagsinuse 1425.919952 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71538505 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4687 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15263.175805 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2888 # number of replacements +system.cpu.icache.tags.tagsinuse 1423.991727 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71011798 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4684 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15160.503416 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1425.919952 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.696250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.696250 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1798 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1423.991727 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695308 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.877930 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143091073 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143091073 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71538505 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71538505 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71538505 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71538505 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71538505 # number of overall hits -system.cpu.icache.overall_hits::total 71538505 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4688 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4688 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4688 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4688 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4688 # number of overall misses -system.cpu.icache.overall_misses::total 4688 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 199914000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 199914000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 199914000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 199914000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 199914000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 199914000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71543193 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71543193 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71543193 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71543193 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71543193 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71543193 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 142037650 # Number of tag accesses +system.cpu.icache.tags.data_accesses 142037650 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71011798 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71011798 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71011798 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71011798 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71011798 # number of overall hits +system.cpu.icache.overall_hits::total 71011798 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4685 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4685 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4685 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4685 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4685 # number of overall misses +system.cpu.icache.overall_misses::total 4685 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 199910500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 199910500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 199910500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 199910500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 199910500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 199910500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71016483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71016483 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71016483 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71016483 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71016483 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71016483 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42643.771331 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42643.771331 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42643.771331 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42643.771331 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42643.771331 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42643.771331 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42670.330843 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42670.330843 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42670.330843 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42670.330843 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42670.330843 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,129 +591,129 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4688 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4688 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4688 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4688 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4688 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4688 # number of overall MSHR misses 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cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 255188000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139969500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115218500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 255188000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461391 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.460832 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.867978 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.595722 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461391 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595381 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.460832 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.595722 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66617.431193 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66617.431193 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64695.330559 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64695.330559 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68029.126214 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68029.126214 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64695.330559 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.220141 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65768.793593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64695.330559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.220141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65768.793593 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595381 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66461.009174 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66461.009174 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64830.708661 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64830.708661 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69216.828479 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69216.828479 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64830.708661 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67458.138173 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65991.207655 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 5399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2586 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4688 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11943 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11935 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15599 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15591 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 299776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 416832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 416640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9429 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 9425 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9429 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9425 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9429 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4730500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9425 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4728500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7031498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7026998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2721986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 2780 # Transaction distribution +system.membus.trans_dist::ReadResp 2776 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2780 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7740 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7740 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247680 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 2776 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7732 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7732 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3870 # Request fanout histogram +system.membus.snoop_fanout::samples 3866 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3870 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3866 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3870 # Request fanout histogram -system.membus.reqLayer0.occupancy 4532500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3866 # Request fanout histogram +system.membus.reqLayer0.occupancy 4535000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20566750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20543000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 962fb9596..cec07c5fb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -149,7 +149,7 @@ instShiftAmt=2 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -490,7 +490,7 @@ opLat=4 pipelined=true [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -600,7 +600,7 @@ sys=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=prefetcher tags addr_ranges=0:18446744073709551615 assoc=16 @@ -688,7 +688,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf +executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf gid=100 input=cin kvmInSE=false diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 081b32451..1647d5712 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -156,7 +156,7 @@ localPredictorSize=2048 numThreads=1 [system.cpu.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -513,7 +513,7 @@ opLat=3 pipelined=false [system.cpu.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=2 @@ -579,7 +579,7 @@ system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 7449e222c..61db655d7 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Apr 22 2015 08:10:29 -gem5 started Apr 22 2015 10:10:22 -gem5 executing on phenom -command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +gem5 compiled Sep 14 2015 22:13:36 +gem5 started Sep 14 2015 23:11:50 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 @@ -19,397 +21,11 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 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-info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. - 43 44 45 + 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 148668850500 because target called exit() +122 123 124 info: Increasing stack size by one page. +Exiting @ tick 79147317000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 8e968af2a..cd6ba3bb4 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.081371 # Number of seconds simulated -sim_ticks 81371461000 # Number of ticks simulated -final_tick 81371461000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.079147 # Number of seconds simulated +sim_ticks 79147317000 # Number of ticks simulated +final_tick 79147317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90424 # Simulator instruction rate (inst/s) -host_op_rate 151559 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55711800 # Simulator tick rate (ticks/s) -host_mem_usage 348672 # Number of bytes of host memory used -host_seconds 1460.58 # Real time elapsed on the host +host_inst_rate 70947 # Simulator instruction rate (inst/s) +host_op_rate 118914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42517019 # Simulator tick rate (ticks/s) +host_mem_usage 343896 # Number of bytes of host memory used +host_seconds 1861.54 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory -system.physmem.bytes_read::total 349632 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224128 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3502 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5463 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2754381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1542359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4296740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2754381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2754381 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2754381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1542359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4296740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5463 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory +system.physmem.bytes_read::total 346304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5411 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2797012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1578424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4375436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2797012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2797012 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2797012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1578424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4375436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5413 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5463 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 349632 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 346304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 349632 # Total read bytes from the system interface side +system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 312 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 292 # Per bank write bursts -system.physmem.perBankRdBursts::1 354 # Per bank write bursts -system.physmem.perBankRdBursts::2 456 # Per bank write bursts -system.physmem.perBankRdBursts::3 360 # Per bank write bursts -system.physmem.perBankRdBursts::4 330 # Per bank write bursts -system.physmem.perBankRdBursts::5 342 # Per bank write bursts -system.physmem.perBankRdBursts::6 399 # Per bank write bursts -system.physmem.perBankRdBursts::7 387 # Per bank write bursts -system.physmem.perBankRdBursts::8 324 # Per bank write bursts -system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 240 # Per bank write bursts -system.physmem.perBankRdBursts::11 270 # Per bank write bursts -system.physmem.perBankRdBursts::12 220 # Per bank write bursts -system.physmem.perBankRdBursts::13 487 # Per bank write bursts -system.physmem.perBankRdBursts::14 392 # Per bank write bursts -system.physmem.perBankRdBursts::15 328 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 303 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 299 # Per bank write bursts +system.physmem.perBankRdBursts::1 344 # Per bank write bursts +system.physmem.perBankRdBursts::2 461 # Per bank write bursts +system.physmem.perBankRdBursts::3 354 # Per bank write bursts +system.physmem.perBankRdBursts::4 343 # Per bank write bursts +system.physmem.perBankRdBursts::5 326 # Per bank write bursts +system.physmem.perBankRdBursts::6 401 # Per bank write bursts +system.physmem.perBankRdBursts::7 385 # Per bank write bursts +system.physmem.perBankRdBursts::8 338 # Per bank write bursts +system.physmem.perBankRdBursts::9 281 # Per bank write bursts +system.physmem.perBankRdBursts::10 237 # Per bank write bursts +system.physmem.perBankRdBursts::11 285 # Per bank write bursts +system.physmem.perBankRdBursts::12 221 # Per bank write bursts +system.physmem.perBankRdBursts::13 466 # Per bank write bursts +system.physmem.perBankRdBursts::14 386 # Per bank write bursts +system.physmem.perBankRdBursts::15 284 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 81371407000 # Total gap between requests +system.physmem.totGap 79147284500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5463 # Read request sizes (log2) +system.physmem.readPktSize::6 5413 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,313 +186,313 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1133 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.177405 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.606569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.434363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 453 39.98% 39.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 241 21.27% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 107 9.44% 70.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 66 5.83% 76.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 42 3.71% 80.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 53 4.68% 84.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 2.65% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.59% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 123 10.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1133 # Bytes accessed per row activation -system.physmem.totQLat 39364000 # Total ticks spent queuing -system.physmem.totMemAccLat 141795250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27315000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7205.56 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25955.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.bytesPerActivate::samples 1109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.266907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.102740 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.449427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 425 38.32% 38.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 245 22.09% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 103 9.29% 69.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 58 5.23% 74.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 62 5.59% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 4.69% 85.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 2.16% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.62% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 122 11.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1109 # Bytes accessed per row activation +system.physmem.totQLat 39588000 # Total ticks spent queuing +system.physmem.totMemAccLat 141044250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7313.50 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4998.15 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26056.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4322 # Number of row buffer hits during reads +system.physmem.readRowHits 4302 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.11 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14895004.03 # Average gap between requests -system.physmem.pageHitRate 79.11 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4898880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2673000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22627800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14621704.14 # Average gap between requests +system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4951800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2701875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22721400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5314452000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2576418525 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 46559935500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 54481005705 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.574677 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 77452365250 # Time in different power states -system.physmem_0.memoryStateTime::REF 2717000000 # Time in different power states +system.physmem_0.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2476092825 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 45316483500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 52992463800 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.540663 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 75384383500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1197234500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1120221500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3643920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1988250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19640400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3432240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1872750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19484400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5314452000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2400589485 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 46714163250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 54454477305 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.248755 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 77713281250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2717000000 # Time in different power states +system.physmem_1.refreshEnergy 5169512400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2281510215 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 45487170000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 52962982005 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.168172 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 75669637750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 939125250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 834967250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 21769917 # Number of BP lookups -system.cpu.branchPred.condPredicted 21769917 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1549122 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 13731962 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12878566 # Number of BTB hits +system.cpu.branchPred.lookups 20588400 # Number of BP lookups +system.cpu.branchPred.condPredicted 20588400 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1327971 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12696525 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12013993 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.785331 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1523299 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21478 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.624261 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1440282 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 16776 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 162742923 # number of cpu cycles simulated +system.cpu.numCycles 158294635 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27183337 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 241535825 # Number of instructions fetch has processed -system.cpu.fetch.Branches 21769917 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14401865 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 133481172 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3672135 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 7 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 3449 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 35973 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 25247816 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227405263 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20588400 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13454275 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 131222766 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3194613 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 1919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 20727 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 110 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26033005 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 318152 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 162540128 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.445335 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.347989 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24255799 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 267811 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 158090598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.379045 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324681 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 96819226 59.57% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4970692 3.06% 62.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3926504 2.42% 65.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4600449 2.83% 67.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4436163 2.73% 70.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5045508 3.10% 73.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5083113 3.13% 76.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3898601 2.40% 79.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33759872 20.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95773120 60.58% 60.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4766421 3.01% 63.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3796193 2.40% 66.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4366321 2.76% 68.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4228924 2.68% 71.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4813507 3.04% 74.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4702194 2.97% 77.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3700875 2.34% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31943043 20.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162540128 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.133769 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.484156 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16504764 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96892991 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 25874540 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21431766 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1836067 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 352818767 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1836067 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24444805 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 33422530 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 30828 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38315708 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 64490190 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 343379412 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1374 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57139077 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7429063 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 172376 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 397453727 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 950141626 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 627304694 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4642412 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 158090598 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130064 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.436595 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15405711 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96196393 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23270128 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21621060 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1597306 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336557336 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1597306 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23296942 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31816084 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30705 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35988234 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 65361327 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328199746 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1272 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57739687 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7687780 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 164697 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 380395487 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 909798638 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600491080 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4191135 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 138024277 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2171 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2092 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 120106098 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 87123680 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 31143046 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 62089518 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21014033 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 331702995 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4700 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 264529155 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 75427 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 110344311 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 226235086 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3455 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162540128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.627470 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.538199 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 120966037 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1948 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1925 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 121028118 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 82726275 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 29782185 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59498195 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20364114 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 317775977 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4062 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 259339716 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 70716 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 96416655 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197093622 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2817 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 158090598 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640450 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.524161 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 42962851 26.43% 26.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47766675 29.39% 55.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33381943 20.54% 76.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18299706 11.26% 87.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 11254917 6.92% 94.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4928041 3.03% 97.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2601211 1.60% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 925935 0.57% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 418849 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40031018 25.32% 25.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47550925 30.08% 55.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33058238 20.91% 76.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17999758 11.39% 87.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10966409 6.94% 94.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4755401 3.01% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2459487 1.56% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 881418 0.56% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 387944 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162540128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 158090598 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 228422 7.18% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2563241 80.56% 87.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 390075 12.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 232409 7.35% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2543467 80.43% 87.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 386453 12.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211775 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 165335672 62.50% 62.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 786316 0.30% 63.26% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038827 2.66% 65.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1212035 0.46% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66231753 25.04% 91.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22712777 8.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1213129 0.47% 0.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161789317 62.39% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789379 0.30% 63.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7038032 2.71% 65.87% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1187047 0.46% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64866508 25.01% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22456304 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 264529155 # Type of FU issued -system.cpu.iq.rate 1.625442 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3181738 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012028 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 689869496 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 438078029 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 258256761 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4986107 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4289171 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2392105 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263990006 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2509112 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18745493 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 259339716 # Type of FU issued +system.cpu.iq.rate 1.638335 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3162329 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012194 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 675146049 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410783686 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253609186 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4857026 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3709843 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2340813 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 258843472 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2445444 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18733712 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 30474102 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13683 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 322031 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10627329 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26076688 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 12661 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 303068 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9266468 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 52743 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1836067 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 14124717 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 495168 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 331707695 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 107609 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 87123689 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 31143046 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2075 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 394182 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 62934 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 322031 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 682027 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 925981 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1608008 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 262198462 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65303975 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2330693 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1597306 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12475143 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 492608 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 317780039 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 92128 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 82726275 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 29782185 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1904 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 385254 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 64210 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 303068 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 551876 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 825683 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1377559 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 257278299 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64049933 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2061417 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87811155 # number of memory reference insts executed -system.cpu.iew.exec_branches 14511685 # Number of branches executed -system.cpu.iew.exec_stores 22507180 # Number of stores executed -system.cpu.iew.exec_rate 1.611121 # Inst execution rate -system.cpu.iew.wb_sent 261483321 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 260648866 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208559295 # num instructions producing a value -system.cpu.iew.wb_consumers 374938421 # num instructions consuming a value +system.cpu.iew.exec_refs 86328991 # number of memory reference insts executed +system.cpu.iew.exec_branches 14325599 # Number of branches executed +system.cpu.iew.exec_stores 22279058 # Number of stores executed +system.cpu.iew.exec_rate 1.625313 # Inst execution rate +system.cpu.iew.wb_sent 256636877 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 255949999 # cumulative count of insts written-back +system.cpu.iew.wb_producers 204329368 # num instructions producing a value +system.cpu.iew.wb_consumers 369642243 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.601599 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.556249 # average fanout of values written-back +system.cpu.iew.wb_rate 1.616922 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552776 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 110351288 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 96424533 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1552443 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147477365 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.500999 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.940236 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1329745 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 144946815 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.527204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.957309 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 47558134 32.25% 32.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57784481 39.18% 71.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14247523 9.66% 81.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11907169 8.07% 89.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4233466 2.87% 92.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2889588 1.96% 93.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 908406 0.62% 94.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1058674 0.72% 95.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6889924 4.67% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45502245 31.39% 31.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57364882 39.58% 70.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14168547 9.77% 80.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11990061 8.27% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4061557 2.80% 91.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2847156 1.96% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 903972 0.62% 94.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1081775 0.75% 95.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7026620 4.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147477365 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 144946815 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -538,124 +538,125 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6889924 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 472302113 # The number of ROB reads -system.cpu.rob.rob_writes 678534776 # The number of ROB writes -system.cpu.timesIdled 2601 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 202795 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7026620 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 455708112 # The number of ROB reads +system.cpu.rob.rob_writes 648756933 # The number of ROB writes +system.cpu.timesIdled 2654 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 204037 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.232236 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.232236 # CPI: Total CPI of All Threads -system.cpu.ipc 0.811533 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.811533 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 453858264 # number of integer regfile reads -system.cpu.int_regfile_writes 236894069 # number of integer regfile writes -system.cpu.fp_regfile_reads 3268800 # number of floating regfile reads -system.cpu.fp_regfile_writes 2052370 # number of floating regfile writes -system.cpu.cc_regfile_reads 102728686 # number of cc regfile reads -system.cpu.cc_regfile_writes 60021475 # number of cc regfile writes -system.cpu.misc_regfile_reads 135450288 # number of misc regfile reads +system.cpu.cpi 1.198555 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.198555 # CPI: Total CPI of All Threads +system.cpu.ipc 0.834338 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.834338 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 448462774 # number of integer regfile reads +system.cpu.int_regfile_writes 232558570 # number of integer regfile writes +system.cpu.fp_regfile_reads 3214394 # number of floating regfile reads +system.cpu.fp_regfile_writes 1998880 # number of floating regfile writes +system.cpu.cc_regfile_reads 102524460 # number of cc regfile reads +system.cpu.cc_regfile_writes 59518831 # number of cc regfile writes +system.cpu.misc_regfile_reads 132416718 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 22 # number of replacements -system.cpu.dcache.tags.tagsinuse 1449.922463 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 66913357 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1999 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33473.415208 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 53 # number of replacements +system.cpu.dcache.tags.tagsinuse 1431.895248 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 65702088 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1996 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32916.877756 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1449.922463 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353985 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353985 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 483 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1444 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.482666 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 133833717 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 133833717 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46399026 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46399026 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513875 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513875 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 66912901 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 66912901 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 66912901 # number of overall hits -system.cpu.dcache.overall_hits::total 66912901 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1102 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1856 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1856 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2958 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2958 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2958 # number of overall misses -system.cpu.dcache.overall_misses::total 2958 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 70369000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 70369000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 128824000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 128824000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 199193000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 199193000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 199193000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 199193000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46400128 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46400128 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1431.895248 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.349584 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.349584 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1943 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.474365 # Percentage of cache occupancy per task id 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+system.cpu.dcache.overall_miss_latency::cpu.data 195173500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 195173500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45188778 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45188778 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 66915859 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 66915859 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 66915859 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 66915859 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 65704509 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 65704509 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 65704509 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 65704509 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000090 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000090 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63855.716878 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63855.716878 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69409.482759 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69409.482759 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67340.432725 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67340.432725 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67340.432725 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67340.432725 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 318 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 52 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66079.659319 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66079.659319 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70079.175705 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70079.175705 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68674.700915 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68674.700915 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68674.700915 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 52 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 93.714286 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 70 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 11 # number of writebacks -system.cpu.dcache.writebacks::total 11 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 641 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 641 # number of ReadReq MSHR hits +system.cpu.dcache.writebacks::writebacks 12 # number of writebacks +system.cpu.dcache.writebacks::total 12 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 541 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 541 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 643 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 643 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 643 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 643 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 461 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 461 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1854 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1854 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2315 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2315 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2315 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2315 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36642000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36642000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126830000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 126830000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163472000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 163472000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163472000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 163472000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 543 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 543 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 543 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 543 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 457 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1842 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1842 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2299 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2299 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2299 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2299 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36552500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36552500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127238000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127238000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163790500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163790500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163790500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 163790500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000090 # mshr miss rate for WriteReq accesses @@ -664,214 +665,212 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79483.731020 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79483.731020 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68408.845739 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68408.845739 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70614.254860 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70614.254860 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70614.254860 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70614.254860 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79983.588621 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79983.588621 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69076.004343 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69076.004343 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71244.236625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71244.236625 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5619 # number of replacements -system.cpu.icache.tags.tagsinuse 1637.148267 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26022644 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7593 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3427.188726 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5044 # number of replacements +system.cpu.icache.tags.tagsinuse 1638.951309 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 24246301 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7022 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3452.905298 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1637.148267 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.799389 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.799389 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1974 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1638.951309 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800269 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800269 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 882 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 786 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.963867 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 52073916 # Number of tag accesses -system.cpu.icache.tags.data_accesses 52073916 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26022649 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26022649 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26022649 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26022649 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26022649 # number of overall hits -system.cpu.icache.overall_hits::total 26022649 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10355 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10355 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10355 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10355 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10355 # number of overall misses -system.cpu.icache.overall_misses::total 10355 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 419159499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 419159499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 419159499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 419159499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 419159499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 419159499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26033004 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26033004 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26033004 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26033004 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26033004 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26033004 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses 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task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 874 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 48518920 # Number of tag accesses +system.cpu.icache.tags.data_accesses 48518920 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24246303 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24246303 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24246303 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24246303 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24246303 # number of overall hits +system.cpu.icache.overall_hits::total 24246303 # number of overall hits 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-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.930435 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461285 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980990 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.569582 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461285 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980990 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.569582 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74643.835616 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75733.799600 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75733.799600 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83026.869159 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83026.869159 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75733.799600 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76473.482917 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75999.267936 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75733.799600 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76473.482917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75999.267936 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 7022 # number of ReadCleanReq accesses(hits+misses) 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miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996751 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.996751 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.493022 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.493022 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.914661 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.914661 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.493022 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.977956 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.600355 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.493022 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.977956 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.600355 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75038.461538 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75038.461538 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75529.462738 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75529.462738 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84796.650718 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84796.650718 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75529.462738 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77128.073770 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76105.836720 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75529.462738 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77128.073770 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76105.836720 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -880,122 +879,122 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 312 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 312 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3503 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3503 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 428 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 428 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3503 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5464 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3503 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5464 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6464000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6464000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99099000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99099000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 230285500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 230285500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 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UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996101 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.461285 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.461285 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.930435 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.930435 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461285 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980990 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.569582 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461285 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980990 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.569582 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20717.948718 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20717.948718 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64643.835616 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65739.508992 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65739.508992 # average ReadCleanReq mshr miss latency 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+system.cpu.l2cache.UpgradeReq_mshr_misses::total 303 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1534 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3462 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3462 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 418 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 418 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1952 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5414 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1952 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6283500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6283500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 99769000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 99769000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 226893000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 226893000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31265000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31265000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 226893000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131034000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 357927000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 226893000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131034000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 357927000 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.493022 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.493022 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.914661 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.914661 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.493022 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.977956 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.600355 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.493022 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.977956 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.600355 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20737.623762 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20737.623762 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65038.461538 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65038.461538 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65538.128250 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65538.128250 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74796.650718 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74796.650718 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65538.128250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67128.073770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66111.377909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65538.128250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67128.073770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66111.377909 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadResp 8368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 316 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 316 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7781 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 4947 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 303 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1539 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 460 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4651 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 25555 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 485888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 614528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 316 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 15866 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 457 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19253 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4650 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 449216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 577728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 305 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 14723 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15866 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14723 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 15866 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7944000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 14723 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7373500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11862000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10986000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3157498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3145500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3929 # Transaction distribution -system.membus.trans_dist::UpgradeReq 312 # Transaction distribution -system.membus.trans_dist::UpgradeResp 312 # Transaction distribution -system.membus.trans_dist::ReadExReq 1533 # Transaction distribution -system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3930 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11549 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11549 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11549 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 349568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 349568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 349568 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3877 # Transaction distribution +system.membus.trans_dist::UpgradeReq 303 # Transaction distribution +system.membus.trans_dist::UpgradeResp 303 # Transaction distribution +system.membus.trans_dist::ReadExReq 1534 # Transaction distribution +system.membus.trans_dist::ReadExResp 1534 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3879 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11430 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 346304 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5775 # Request fanout histogram +system.membus.snoop_fanout::samples 5716 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5775 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5716 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5775 # Request fanout histogram -system.membus.reqLayer0.occupancy 7111000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5716 # Request fanout histogram +system.membus.reqLayer0.occupancy 7099000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29581688 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29276697 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |