diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-05-30 12:54:18 -0400 |
| commit | 74553c7d3fc5430752c0c08f2b319a99fb7ed632 (patch) | |
| tree | 79b2a309fff0edaf1ef3e9aa62656904c3351650 /tests/long/se | |
| parent | 3bc4ecdcb4785a976a1c3fd463bf7052b8415d8b (diff) | |
| download | gem5-74553c7d3fc5430752c0c08f2b319a99fb7ed632.tar.xz | |
stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
Diffstat (limited to 'tests/long/se')
70 files changed, 17437 insertions, 13495 deletions
diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt index 0e822db77..f322f4941 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.269669 # Number of seconds simulated -sim_ticks 269668883500 # Number of ticks simulated -final_tick 269668883500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.269772 # Number of seconds simulated +sim_ticks 269771922500 # Number of ticks simulated +final_tick 269771922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49435 # Simulator instruction rate (inst/s) -host_op_rate 49435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22150100 # Simulator tick rate (ticks/s) -host_mem_usage 271532 # Number of bytes of host memory used -host_seconds 12174.61 # Real time elapsed on the host +host_inst_rate 152624 # Simulator instruction rate (inst/s) +host_op_rate 152624 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68411173 # Simulator tick rate (ticks/s) +host_mem_usage 225196 # Number of bytes of host memory used +host_seconds 3943.39 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory @@ -23,17 +23,17 @@ system.physmem.num_reads::cpu.data 25453 # Nu system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 199593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6040712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6240305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 199593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 199593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 240651 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 240651 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 240651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 199593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6040712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6480955 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 199517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6038405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6237921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 240559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 240559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 240559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6038405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6478480 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 26294 # Total number of read requests seen system.physmem.writeReqs 1014 # Total number of write requests seen system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady @@ -43,41 +43,41 @@ system.physmem.bytesConsumedRd 1682816 # by system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1672 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1579 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1680 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1732 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1867 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1493 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1505 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 63 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 70 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 71 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 70 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 79 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 64 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 89 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 33 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 38 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 48 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 269668831500 # Total gap between requests +system.physmem.totGap 269771850500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 1014 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 16677 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1891 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 17534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,8 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see @@ -147,8 +147,8 @@ system.physmem.wrQLenPdf::19 44 # Wh system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -156,14 +156,96 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 383236250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1095312500 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 8692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 200.548550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.216882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 827.235747 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 7745 89.10% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 118 1.36% 90.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 74 0.85% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 56 0.64% 91.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 40 0.46% 92.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 23 0.26% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 20 0.23% 92.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 390 4.49% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4 0.05% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 9 0.10% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 7 0.08% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 0.07% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 2 0.02% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.05% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 0.08% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 4 0.05% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 3 0.03% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 2 0.02% 97.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 1 0.01% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 9 0.10% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.05% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.03% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 3 0.03% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 4 0.05% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 3 0.03% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.02% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 2 0.02% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 2 0.02% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 4 0.05% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 2 0.02% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.02% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.02% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 3 0.03% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 3 0.03% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 2 0.02% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 1 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.02% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.02% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 4 0.05% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 44 0.51% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 9 0.10% 99.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 5 0.06% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 11 0.13% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8577 2 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8692 # Bytes accessed per row activation +system.physmem.totQLat 332225750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 999160750 # Sum of mem lat for all requests system.physmem.totBusLat 131400000 # Total cycles spent in databus access -system.physmem.totBankLat 580676250 # Total cycles spent in bank access -system.physmem.avgQLat 14582.81 # Average queueing delay per request -system.physmem.avgBankLat 22095.75 # Average bank access latency per request +system.physmem.totBankLat 535535000 # Total cycles spent in bank access +system.physmem.avgQLat 12641.77 # Average queueing delay per request +system.physmem.avgBankLat 20378.04 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 41678.56 # Average memory access latency +system.physmem.avgMemAccLat 38019.82 # Average memory access latency system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s @@ -172,36 +254,52 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 12.19 # Average write queue length over time -system.physmem.readRowHits 16315 # Number of row buffer hits during reads -system.physmem.writeRowHits 296 # Number of row buffer hits during writes -system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes -system.physmem.avgGap 9875085.38 # Average gap between requests -system.cpu.branchPred.lookups 86401588 # Number of BP lookups -system.cpu.branchPred.condPredicted 81471319 # Number of conditional branches predicted +system.physmem.readRowHits 18015 # Number of row buffer hits during reads +system.physmem.writeRowHits 585 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.69 # Row buffer hit rate for writes +system.physmem.avgGap 9878857.86 # Average gap between requests +system.membus.throughput 6478480 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4966 # Transaction distribution +system.membus.trans_dist::ReadResp 4966 # Transaction distribution +system.membus.trans_dist::Writeback 1014 # Transaction distribution +system.membus.trans_dist::ReadExReq 21328 # Transaction distribution +system.membus.trans_dist::ReadExResp 21328 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 53602 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 53602 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1747712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1747712 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1747712 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 40219500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 248608250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.branchPred.lookups 86401392 # Number of BP lookups +system.cpu.branchPred.condPredicted 81471121 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 36340860 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 45048223 # Number of BTB lookups -system.cpu.branchPred.BTBHits 34648139 # Number of BTB hits +system.cpu.branchPred.BTBLookups 45048026 # Number of BTB lookups +system.cpu.branchPred.BTBHits 34648141 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 76.913442 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 76.913783 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 114517866 # DTB read hits +system.cpu.dtb.read_hits 114525360 # DTB read hits system.cpu.dtb.read_misses 2631 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 114520497 # DTB read accesses -system.cpu.dtb.write_hits 39453488 # DTB write hits +system.cpu.dtb.read_accesses 114527991 # DTB read accesses +system.cpu.dtb.write_hits 39455215 # DTB write hits system.cpu.dtb.write_misses 2302 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 39455790 # DTB write accesses -system.cpu.dtb.data_hits 153971354 # DTB hits +system.cpu.dtb.write_accesses 39457517 # DTB write accesses +system.cpu.dtb.data_hits 153980575 # DTB hits system.cpu.dtb.data_misses 4933 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 153976287 # DTB accesses +system.cpu.dtb.data_accesses 153985508 # DTB accesses system.cpu.itb.fetch_hits 24966979 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -219,34 +317,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 539337768 # number of cpu cycles simulated +system.cpu.numCycles 539543846 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 37213741 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 49187847 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 541069811 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 37213743 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 49187649 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 541069671 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 1004924657 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 1004924517 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 255160339 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 255160482 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 154930401 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 34118747 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 2217126 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 36335873 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 26212045 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 58.092858 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 412134920 # Number of Instructions Executed. +system.cpu.execution_unit.executions 412134922 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 535759851 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 535782792 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 296128 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 50805895 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 488531873 # Number of cycles cpu stages are processed. -system.cpu.activity 90.579949 # Percentage of cycles cpu is active +system.cpu.timesIdled 294264 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 51002909 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 488540937 # Number of cycles cpu stages are processed. +system.cpu.activity 90.547032 # Percentage of cycles cpu is active system.cpu.comLoads 114514042 # Number of Load instructions committed system.cpu.comStores 39451321 # Number of Store instructions committed system.cpu.comBranches 62547159 # Number of Branches instructions committed @@ -258,124 +356,144 @@ system.cpu.committedInsts 601856964 # Nu system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total) -system.cpu.cpi 0.896123 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.896465 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.896123 # CPI: Total CPI of All Threads -system.cpu.ipc 1.115918 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.896465 # CPI: Total CPI of All Threads +system.cpu.ipc 1.115492 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.115918 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 200608412 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 338729356 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 62.804679 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 228909431 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 310428337 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 57.557315 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 197773731 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 341564037 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.330265 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 427958956 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 111378812 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.651031 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 192540057 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 346797711 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.300654 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.115492 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 200810173 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 338733673 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 62.781491 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 229113520 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 310430326 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 57.535700 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 197979216 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 341564630 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.306186 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 428164340 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 111379506 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.643272 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 192742225 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 346801621 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.276819 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 30 # number of replacements -system.cpu.icache.tagsinuse 729.833568 # Cycle average of tags in use -system.cpu.icache.total_refs 24965946 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 729.672642 # Cycle average of tags in use +system.cpu.icache.total_refs 24965940 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 29199.936842 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 29199.929825 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 729.833568 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 24965946 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24965946 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24965946 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24965946 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24965946 # number of overall hits -system.cpu.icache.overall_hits::total 24965946 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1033 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1033 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1033 # number of overall misses -system.cpu.icache.overall_misses::total 1033 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55677000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55677000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55677000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55677000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55677000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55677000 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 729.672642 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.356285 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.356285 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 24965940 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24965940 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24965940 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24965940 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24965940 # number of overall hits +system.cpu.icache.overall_hits::total 24965940 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses +system.cpu.icache.overall_misses::total 1039 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 73110500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 73110500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 73110500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 73110500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 73110500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 73110500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 24966979 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 24966979 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 24966979 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 24966979 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 24966979 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 24966979 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000041 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000041 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000041 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000041 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000041 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53898.354308 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53898.354308 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53898.354308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53898.354308 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53898.354308 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 133 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70366.217517 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70366.217517 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70366.217517 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70366.217517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70366.217517 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70366.217517 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 267 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 66.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 133.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 178 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 178 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 178 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 178 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 178 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 178 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 184 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 184 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 184 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 184 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 184 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 184 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 855 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 855 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 855 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45946500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45946500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45946500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45946500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45946500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45946500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 60213000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 60213000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60213000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 60213000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000034 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000034 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53738.596491 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53738.596491 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53738.596491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53738.596491 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70424.561404 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70424.561404 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70424.561404 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70424.561404 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70424.561404 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70424.561404 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 211885535 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 202062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 202062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 254188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 254188 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1710 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1349387 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 57160768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 57160768 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 883455500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1282500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 683092999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) system.cpu.l2cache.replacements 1042 # number of replacements -system.cpu.l2cache.tagsinuse 22879.137372 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 22873.227488 # Cycle average of tags in use system.cpu.l2cache.total_refs 531830 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 23279 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 22.845913 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21684.500481 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 718.953671 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 475.683220 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.661758 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.021941 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.014517 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.698216 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21678.205650 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 718.794355 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 476.227482 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.661566 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.021936 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.014533 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.698036 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 197082 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 197096 # number of ReadReq hits @@ -400,17 +518,17 @@ system.cpu.l2cache.demand_misses::total 26294 # nu system.cpu.l2cache.overall_misses::cpu.inst 841 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 25453 # number of overall misses system.cpu.l2cache.overall_misses::total 26294 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44941500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 470659500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 515601000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1197956000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1197956000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 44941500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1668615500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1713557000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 44941500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1668615500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1713557000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 59208000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 554748000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 613956000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1528945500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1528945500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 59208000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2083693500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2142901500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 59208000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2083693500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2142901500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 201207 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 202062 # number of ReadReq accesses(hits+misses) @@ -435,17 +553,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.057631 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.983626 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.055892 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.057631 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53438.168847 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 114099.272727 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 103826.218284 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56168.229557 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56168.229557 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65169.126036 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53438.168847 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65556.732016 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65169.126036 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70401.902497 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 134484.363636 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 123631.896899 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71687.242123 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71687.242123 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70401.902497 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81864.357836 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81497.737126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70401.902497 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81864.357836 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81497.737126 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -467,17 +585,17 @@ system.cpu.l2cache.demand_mshr_misses::total 26294 system.cpu.l2cache.overall_mshr_misses::cpu.inst 841 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 25453 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 26294 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34505688 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 418277231 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 452782919 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 932478797 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 932478797 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34505688 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1350756028 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1385261716 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34505688 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1350756028 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1385261716 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48784500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 502370250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 551154750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1264256500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1264256500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1766626750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1815411250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1766626750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1815411250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020501 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024577 # mshr miss rate for ReadReq accesses @@ -489,51 +607,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.057631 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983626 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055892 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.057631 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41029.355529 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 101400.540848 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 91176.584575 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43720.873828 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43720.873828 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41029.355529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53068.637410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52683.567202 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58007.728894 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 121786.727273 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 110985.652437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59276.842648 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59276.842648 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58007.728894 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69407.407771 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69042.794934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58007.728894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69407.407771 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69042.794934 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 451299 # number of replacements -system.cpu.dcache.tagsinuse 4093.423663 # Cycle average of tags in use -system.cpu.dcache.total_refs 151786149 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 4093.048176 # Cycle average of tags in use +system.cpu.dcache.total_refs 151792699 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 333.306578 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4093.423663 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 114120800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114120800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37665349 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37665349 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 151786149 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 151786149 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 151786149 # number of overall hits -system.cpu.dcache.overall_hits::total 151786149 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 393242 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 393242 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1785972 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1785972 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2179214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2179214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2179214 # number of overall misses -system.cpu.dcache.overall_misses::total 2179214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984700000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5984700000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23169621500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23169621500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29154321500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29154321500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29154321500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29154321500 # number of overall miss cycles +system.cpu.dcache.avg_refs 333.320961 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 382930000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.048176 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999279 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 114127941 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114127941 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37664758 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37664758 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 151792699 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 151792699 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 151792699 # number of overall hits +system.cpu.dcache.overall_hits::total 151792699 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 386101 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 386101 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1786563 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1786563 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2172664 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2172664 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2172664 # number of overall misses +system.cpu.dcache.overall_misses::total 2172664 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6056986500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6056986500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25183645000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25183645000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31240631500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31240631500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31240631500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31240631500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) @@ -542,40 +660,40 @@ system.cpu.dcache.demand_accesses::cpu.data 153965363 # system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003434 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003434 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045270 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045270 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15218.872857 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15218.872857 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.115760 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.115760 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13378.365548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13378.365548 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 191067 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6052 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.570886 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003372 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003372 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045285 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045285 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014111 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014111 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014111 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014111 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15687.570092 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15687.570092 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14096.141586 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14096.141586 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14378.952061 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14378.952061 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 376840 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 954 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 17814 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.154148 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 95.400000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks system.cpu.dcache.writebacks::total 436887 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192010 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 192010 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531809 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1531809 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1723819 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1723819 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1723819 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1723819 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 184869 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 184869 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1532400 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1532400 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1717269 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1717269 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1717269 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1717269 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses @@ -584,14 +702,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 455395 system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643678500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643678500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782203500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782203500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6425882000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6425882000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6425882000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6425882000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2727636001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2727636001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4113048000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4113048000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6840684001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6840684001 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6840684001 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6840684001 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses @@ -600,14 +718,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.465711 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.465711 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.015333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.015333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13554.683157 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13554.683157 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16182.717390 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16182.717390 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt index 1f1ca601b..8b45989c8 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133697 # Number of seconds simulated -sim_ticks 133696809500 # Number of ticks simulated -final_tick 133696809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133885 # Number of seconds simulated +sim_ticks 133884967500 # Number of ticks simulated +final_tick 133884967500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77616 # Simulator instruction rate (inst/s) -host_op_rate 77616 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18348551 # Simulator tick rate (ticks/s) -host_mem_usage 272684 # Number of bytes of host memory used -host_seconds 7286.51 # Real time elapsed on the host +host_inst_rate 162173 # Simulator instruction rate (inst/s) +host_op_rate 162173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38391719 # Simulator tick rate (ticks/s) +host_mem_usage 228276 # Number of bytes of host memory used +host_seconds 3487.34 # Real time elapsed on the host sim_insts 565552443 # Number of instructions simulated sim_ops 565552443 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory -system.physmem.bytes_read::total 1697664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory -system.physmem.bytes_written::total 67072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 26526 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 457154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12240711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12697865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 457154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 457154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 501672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 501672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 501672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 457154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12240711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13199537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 26526 # Total number of read requests seen -system.physmem.writeReqs 1048 # Total number of write requests seen -system.physmem.cpureqs 27574 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1697664 # Total number of bytes read from memory -system.physmem.bytesWritten 67072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1697664 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 61056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory +system.physmem.bytes_read::total 1697216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61056 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66944 # Number of bytes written to this memory +system.physmem.bytes_written::total 66944 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory +system.physmem.num_reads::total 26519 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 456033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12220640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12676673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 456033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 456033 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 500011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 500011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 500011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 456033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12220640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13176685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 26519 # Total number of read requests seen +system.physmem.writeReqs 1046 # Total number of write requests seen +system.physmem.cpureqs 27565 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1697216 # Total number of bytes read from memory +system.physmem.bytesWritten 66944 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1697216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 66944 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1631 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1627 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1646 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 56 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 60 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1674 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1739 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1730 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1813 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1787 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1675 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1459 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1440 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1505 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1515 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 64 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 61 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 71 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 72 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 73 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 80 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 90 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 34 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 44 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 52 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 133696776000 # Total gap between requests +system.physmem.totGap 133884902000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 26526 # Categorize read packet sizes +system.physmem.readPktSize::6 26519 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1048 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 9044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11316 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1070 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 11989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 9624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,7 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see @@ -135,8 +135,8 @@ system.physmem.wrQLenPdf::7 46 # Wh system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see @@ -147,7 +147,7 @@ system.physmem.wrQLenPdf::19 45 # Wh system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -156,56 +156,157 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 652146750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1350583000 # Sum of mem lat for all requests -system.physmem.totBusLat 132555000 # Total cycles spent in databus access -system.physmem.totBankLat 565881250 # Total cycles spent in bank access -system.physmem.avgQLat 24599.10 # Average queueing delay per request -system.physmem.avgBankLat 21345.15 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 8244 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 213.286754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.643190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 848.319386 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 6744 81.80% 81.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 612 7.42% 89.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 105 1.27% 90.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 71 0.86% 91.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 43 0.52% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 25 0.30% 92.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 16 0.19% 92.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 389 4.72% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 10 0.12% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 9 0.11% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.04% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 3 0.04% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.06% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 0.10% 97.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 9 0.11% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.08% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 0.06% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.04% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 7 0.08% 97.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.07% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.05% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.02% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.01% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.04% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 4 0.05% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.01% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.02% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.02% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 3 0.04% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.01% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.02% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.01% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.02% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.02% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 2 0.02% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 3 0.04% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.01% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 1 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.02% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 6 0.07% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.02% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 43 0.52% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 11 0.13% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 4 0.05% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 3 0.04% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 13 0.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 8244 # Bytes accessed per row activation +system.physmem.totQLat 457304500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1107883250 # Sum of mem lat for all requests +system.physmem.totBusLat 132520000 # Total cycles spent in databus access +system.physmem.totBankLat 518058750 # Total cycles spent in bank access +system.physmem.avgQLat 17254.17 # Average queueing delay per request +system.physmem.avgBankLat 19546.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 50944.25 # Average memory access latency -system.physmem.avgRdBW 12.70 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 41800.61 # Average memory access latency +system.physmem.avgRdBW 12.68 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 12.70 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 12.68 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.10 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.33 # Average write queue length over time -system.physmem.readRowHits 16975 # Number of row buffer hits during reads -system.physmem.writeRowHits 275 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 26.24 # Row buffer hit rate for writes -system.physmem.avgGap 4848653.66 # Average gap between requests -system.cpu.branchPred.lookups 76441752 # Number of BP lookups -system.cpu.branchPred.condPredicted 70864410 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2706781 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 43062122 # Number of BTB lookups -system.cpu.branchPred.BTBHits 41938047 # Number of BTB hits +system.physmem.avgWrQLen 7.87 # Average write queue length over time +system.physmem.readRowHits 18718 # Number of row buffer hits during reads +system.physmem.writeRowHits 577 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 55.16 # Row buffer hit rate for writes +system.physmem.avgGap 4857061.56 # Average gap between requests +system.membus.throughput 13176685 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5255 # Transaction distribution +system.membus.trans_dist::ReadResp 5255 # Transaction distribution +system.membus.trans_dist::Writeback 1046 # Transaction distribution +system.membus.trans_dist::ReadExReq 21264 # Transaction distribution +system.membus.trans_dist::ReadExResp 21264 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 54084 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 54084 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1764160 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1764160 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1764160 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 40437500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 246430250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.branchPred.lookups 76481142 # Number of BP lookups +system.cpu.branchPred.condPredicted 70905485 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2712830 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 43152568 # Number of BTB lookups +system.cpu.branchPred.BTBHits 41951176 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.389643 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1605813 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 97.215943 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1604071 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 122608255 # DTB read hits -system.cpu.dtb.read_misses 28801 # DTB read misses +system.cpu.dtb.read_hits 122621956 # DTB read hits +system.cpu.dtb.read_misses 28776 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 122637056 # DTB read accesses -system.cpu.dtb.write_hits 40754827 # DTB write hits -system.cpu.dtb.write_misses 25617 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 40780444 # DTB write accesses -system.cpu.dtb.data_hits 163363082 # DTB hits -system.cpu.dtb.data_misses 54418 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 163417500 # DTB accesses -system.cpu.itb.fetch_hits 65484737 # ITB hits +system.cpu.dtb.read_accesses 122650732 # DTB read accesses +system.cpu.dtb.write_hits 40755113 # DTB write hits +system.cpu.dtb.write_misses 25625 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 40780738 # DTB write accesses +system.cpu.dtb.data_hits 163377069 # DTB hits +system.cpu.dtb.data_misses 54401 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 163431470 # DTB accesses +system.cpu.itb.fetch_hits 65530786 # ITB hits system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 65484778 # ITB accesses +system.cpu.itb.fetch_accesses 65530827 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,133 +320,133 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 267393620 # number of cpu cycles simulated +system.cpu.numCycles 267769936 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 67132788 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 699091920 # Number of instructions fetch has processed -system.cpu.fetch.Branches 76441752 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 43543860 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 117791826 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11623941 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73287443 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 65484737 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 927172 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 267096777 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.617373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.445045 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 67189108 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 699431830 # Number of instructions fetch has processed +system.cpu.fetch.Branches 76481142 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 43555247 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 117843991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11666830 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 73504935 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1313 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 65530786 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 931341 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 267451900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.615169 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.444449 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 149304951 55.90% 55.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10344865 3.87% 59.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 11847519 4.44% 64.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10566772 3.96% 68.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7010837 2.62% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2867971 1.07% 71.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3579531 1.34% 73.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3103336 1.16% 74.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68470995 25.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 149607909 55.94% 55.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10348918 3.87% 59.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11847203 4.43% 64.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10573344 3.95% 68.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7008253 2.62% 70.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2869794 1.07% 71.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3587132 1.34% 73.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3111076 1.16% 74.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68498271 25.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 267096777 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.285877 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.614467 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 84255179 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 57589844 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 102698571 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 13670600 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8882583 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3874487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 931 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 691126555 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3231 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 8882583 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 92229912 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12770086 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1212 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 103061748 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 50151236 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 680987279 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 38480754 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 5456693 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 520711815 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 896998441 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 896995902 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2539 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 267451900 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285623 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.612063 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 84322843 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 57802490 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 102700565 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13714405 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8911597 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3873381 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 948 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 691440481 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3137 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 8911597 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 92312573 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 12823003 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1534 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 103090752 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 50312441 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681258889 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 435 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 38630282 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 5470230 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 520856634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 897283230 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 897280730 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2500 # Number of floating rename lookups system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 56856926 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 56 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 61 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 112143528 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 126973457 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 42377854 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14839100 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 10235293 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 621082747 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 48 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 604577802 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 299631 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 54891737 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29918454 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 267096777 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.263516 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.822324 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 57001745 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 66 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 72 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 112491401 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 126996487 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42388542 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 14811954 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 10030949 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 621209385 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 604684391 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 299599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 55017699 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 29989465 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 267451900 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.260909 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.823825 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52289348 19.58% 19.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55783537 20.89% 40.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 53427937 20.00% 60.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 36631888 13.71% 74.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31292246 11.72% 85.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 23678415 8.87% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10025583 3.75% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3414414 1.28% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 553409 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52525807 19.64% 19.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 56031435 20.95% 40.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 53465406 19.99% 60.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 36379699 13.60% 74.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31195818 11.66% 85.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 23840953 8.91% 94.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10047725 3.76% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3411796 1.28% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 553261 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 267096777 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 267451900 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2692091 70.58% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 42 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 729838 19.13% 89.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 392410 10.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2753778 71.24% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 45 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 726781 18.80% 90.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 385136 9.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 439064264 72.62% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7069 0.00% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 439140797 72.62% 72.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7079 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued @@ -373,84 +474,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 72.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 124327148 20.56% 93.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 41179273 6.81% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 124346650 20.56% 93.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 41189817 6.81% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 604577802 # Type of FU issued -system.cpu.iq.rate 2.261003 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3814381 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006309 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1480362706 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 675977802 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 596495784 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3687 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2189 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1715 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 608390320 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1863 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12281051 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 604684391 # Type of FU issued +system.cpu.iq.rate 2.258224 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3865740 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006393 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1480982314 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 676230303 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 596557394 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3707 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2213 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1724 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 608548258 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1873 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 12279987 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 12459415 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 35750 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 5512 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2926533 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 12482445 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 36037 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5437 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2937221 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6468 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 56300 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 6392 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 65545 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8882583 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1439479 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 190555 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 663921502 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1696631 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 126973457 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 42377854 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 142659 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7414 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 5512 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1334753 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1804223 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3138976 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599473269 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 122637223 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5104533 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8911597 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1457895 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 191973 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 664097895 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1705444 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 126996487 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 42388542 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 144321 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7199 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 5437 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1338458 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1807769 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3146227 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599553495 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 122650887 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5130896 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 42838707 # number of nop insts executed -system.cpu.iew.exec_refs 163435917 # number of memory reference insts executed -system.cpu.iew.exec_branches 66623579 # Number of branches executed -system.cpu.iew.exec_stores 40798694 # Number of stores executed -system.cpu.iew.exec_rate 2.241913 # Inst execution rate -system.cpu.iew.wb_sent 597432372 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 596497499 # cumulative count of insts written-back -system.cpu.iew.wb_producers 415924305 # num instructions producing a value -system.cpu.iew.wb_consumers 530247239 # num instructions consuming a value +system.cpu.iew.exec_nop 42888454 # number of nop insts executed +system.cpu.iew.exec_refs 163450221 # number of memory reference insts executed +system.cpu.iew.exec_branches 66634078 # Number of branches executed +system.cpu.iew.exec_stores 40799334 # Number of stores executed +system.cpu.iew.exec_rate 2.239062 # Inst execution rate +system.cpu.iew.wb_sent 597495724 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 596559118 # cumulative count of insts written-back +system.cpu.iew.wb_producers 415919830 # num instructions producing a value +system.cpu.iew.wb_consumers 530239470 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.230784 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.784397 # average fanout of values written-back +system.cpu.iew.wb_rate 2.227879 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.784400 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 61940872 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 62116663 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2705903 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 258214194 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.330844 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.692748 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2711961 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 258540303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.327904 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.691623 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 79436879 30.76% 30.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 72473576 28.07% 58.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 25624236 9.92% 68.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9154468 3.55% 72.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10267531 3.98% 76.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 21039855 8.15% 84.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6818360 2.64% 87.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3702360 1.43% 88.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29696929 11.50% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 79687582 30.82% 30.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 72573675 28.07% 58.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 25533783 9.88% 68.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9229698 3.57% 72.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 10307338 3.99% 76.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 20995746 8.12% 84.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6840090 2.65% 87.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3701122 1.43% 88.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29671269 11.48% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 258214194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 258540303 # Number of insts commited each cycle system.cpu.commit.committedInsts 601856963 # Number of instructions committed system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,192 +562,212 @@ system.cpu.commit.branches 62547159 # Nu system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions. system.cpu.commit.int_insts 563954763 # Number of committed integer instructions. system.cpu.commit.function_calls 1197610 # Number of function calls committed. -system.cpu.commit.bw_lim_events 29696929 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29671269 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 892250711 # The number of ROB reads -system.cpu.rob.rob_writes 1336492363 # The number of ROB writes -system.cpu.timesIdled 34289 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 296843 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 892778271 # The number of ROB reads +system.cpu.rob.rob_writes 1336872912 # The number of ROB writes +system.cpu.timesIdled 34547 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 318036 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.472801 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.472801 # CPI: Total CPI of All Threads -system.cpu.ipc 2.115056 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.115056 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 844981893 # number of integer regfile reads -system.cpu.int_regfile_writes 490535855 # number of integer regfile writes -system.cpu.fp_regfile_reads 379 # number of floating regfile reads +system.cpu.cpi 0.473466 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.473466 # CPI: Total CPI of All Threads +system.cpu.ipc 2.112083 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.112083 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 845093769 # number of integer regfile reads +system.cpu.int_regfile_writes 490581182 # number of integer regfile writes +system.cpu.fp_regfile_reads 382 # number of floating regfile reads system.cpu.fp_regfile_writes 54 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 39 # number of replacements -system.cpu.icache.tagsinuse 825.626517 # Cycle average of tags in use -system.cpu.icache.total_refs 65483355 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 973 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 67300.467626 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 435443419 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 211400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 211400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 444967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 254560 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 254560 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1374943 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1376887 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58237120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 58299328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 58299328 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 900430500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1458499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 697482499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu.icache.replacements 40 # number of replacements +system.cpu.icache.tagsinuse 824.576664 # Cycle average of tags in use +system.cpu.icache.total_refs 65529394 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 972 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 67417.072016 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 825.626517 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.403138 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.403138 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 65483355 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 65483355 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 65483355 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 65483355 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 65483355 # number of overall hits -system.cpu.icache.overall_hits::total 65483355 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses -system.cpu.icache.overall_misses::total 1381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 73729000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 73729000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 73729000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 73729000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 73729000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 73729000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 65484736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 65484736 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 65484736 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 65484736 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 65484736 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 65484736 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 824.576664 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.402625 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.402625 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 65529394 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 65529394 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 65529394 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 65529394 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 65529394 # number of overall hits +system.cpu.icache.overall_hits::total 65529394 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1391 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1391 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1391 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1391 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1391 # number of overall misses +system.cpu.icache.overall_misses::total 1391 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 90149500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 90149500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 90149500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 90149500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 90149500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 90149500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 65530785 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 65530785 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 65530785 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 65530785 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 65530785 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 65530785 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53388.124547 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53388.124547 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53388.124547 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53388.124547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53388.124547 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53388.124547 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64809.130122 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 64809.130122 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 64809.130122 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 64809.130122 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 64809.130122 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 64809.130122 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 33.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 408 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 408 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 408 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 408 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 408 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 408 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 973 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 973 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 973 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 973 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 973 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54179000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54179000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54179000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54179000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 419 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 419 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 419 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 419 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 419 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 419 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 972 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 972 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 972 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 972 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 972 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 972 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 66407501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 66407501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 66407501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 66407501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 66407501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 66407501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000015 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000015 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000015 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000015 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55682.425488 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55682.425488 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55682.425488 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55682.425488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55682.425488 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55682.425488 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68320.474280 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68320.474280 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68320.474280 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68320.474280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68320.474280 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68320.474280 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1081 # number of replacements -system.cpu.l2cache.tagsinuse 22922.098360 # Cycle average of tags in use -system.cpu.l2cache.total_refs 547070 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 23518 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 23.261757 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 1077 # number of replacements +system.cpu.l2cache.tagsinuse 22914.008377 # Cycle average of tags in use +system.cpu.l2cache.total_refs 547130 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 23515 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 23.267276 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21473.132839 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 816.078621 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 632.886901 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.655308 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.024905 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019314 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.699527 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 21467.928297 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 816.924139 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 629.155942 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.655149 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.024931 # 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average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 460841 # number of replacements -system.cpu.dcache.tagsinuse 4090.895658 # Cycle average of tags in use -system.cpu.dcache.total_refs 146899681 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 464937 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 315.956099 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 301835000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4090.895658 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998754 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998754 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 109250298 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 109250298 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 37649372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 37649372 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 146899670 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 146899670 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 146899670 # number of overall hits -system.cpu.dcache.overall_hits::total 146899670 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1022486 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1022486 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1801949 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1801949 # number of WriteReq misses +system.cpu.dcache.replacements 460892 # number of replacements +system.cpu.dcache.tagsinuse 4090.586607 # Cycle average of tags in use +system.cpu.dcache.total_refs 146918843 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 464988 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 315.962655 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 315391000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4090.586607 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998678 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998678 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 109270363 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 109270363 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 37648463 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 37648463 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 17 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 17 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 146918826 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 146918826 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 146918826 # number of overall hits +system.cpu.dcache.overall_hits::total 146918826 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1007750 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1007750 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1802858 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1802858 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2824435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2824435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2824435 # number of overall misses -system.cpu.dcache.overall_misses::total 2824435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15308231000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15308231000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26204381408 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26204381408 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 2810608 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2810608 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2810608 # number of overall misses +system.cpu.dcache.overall_misses::total 2810608 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15255049500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15255049500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27585273680 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27585273680 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 48500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 48500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41512612408 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41512612408 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41512612408 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41512612408 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 110272784 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 110272784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 42840323180 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42840323180 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42840323180 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42840323180 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 110278113 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 110278113 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 149724105 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 149724105 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 149724105 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 149724105 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009272 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009272 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045675 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.045675 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.312500 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.312500 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018864 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018864 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018864 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018864 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14971.580051 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14971.580051 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14542.243653 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14542.243653 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 149729434 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 149729434 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 149729434 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 149729434 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009138 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009138 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045698 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045698 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.227273 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.227273 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018771 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018771 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018771 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018771 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15137.732076 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15137.732076 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15300.857683 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15300.857683 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9700 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9700 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14697.669590 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14697.669590 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14697.669590 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14697.669590 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 306629 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2099 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 18462 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.608656 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 190.818182 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15242.368619 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15242.368619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15242.368619 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15242.368619 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 382457 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1107 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20340 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.803196 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 92.250000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 444926 # number of writebacks -system.cpu.dcache.writebacks::total 444926 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 812044 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 812044 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1547454 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1547454 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 444967 # number of writebacks +system.cpu.dcache.writebacks::total 444967 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 797322 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 797322 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1548298 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1548298 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2359498 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2359498 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2359498 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2359498 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210442 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 210442 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254495 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 254495 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 464937 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 464937 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 464937 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 464937 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2697776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2697776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4104342498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4104342498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6802118498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6802118498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6802118498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6802118498 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 2345620 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2345620 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2345620 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2345620 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210428 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210428 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254560 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 254560 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 464988 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 464988 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 464988 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 464988 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2709117501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2709117501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4357981491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4357981491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7067098992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7067098992 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7067098992 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7067098992 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001908 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001908 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006451 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003105 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12819.570238 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12819.570238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16127.399352 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16127.399352 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.320437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.320437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17119.663305 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17119.663305 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15198.454567 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15198.454567 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15198.454567 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15198.454567 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt index 0780eabd0..fbf28575b 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.300931 # Nu sim_ticks 300930958000 # Number of ticks simulated final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2641824 # Simulator instruction rate (inst/s) -host_op_rate 2641824 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1320922836 # Simulator tick rate (ticks/s) -host_mem_usage 264040 # Number of bytes of host memory used -host_seconds 227.82 # Real time elapsed on the host +host_inst_rate 3984763 # Simulator instruction rate (inst/s) +host_op_rate 3984763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1992397518 # Simulator tick rate (ticks/s) +host_mem_usage 217612 # Number of bytes of host memory used +host_seconds 151.04 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 507324022 # Wr system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9755262308 # Throughput (bytes/s) +system.membus.data_through_bus 2935660432 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt index 19cf772df..52085a7cc 100644 --- a/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.762403 # Nu sim_ticks 762403375000 # Number of ticks simulated final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1151537 # Simulator instruction rate (inst/s) -host_op_rate 1151537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1458711281 # Simulator tick rate (ticks/s) -host_mem_usage 272496 # Number of bytes of host memory used -host_seconds 522.66 # Real time elapsed on the host +host_inst_rate 1417339 # Simulator instruction rate (inst/s) +host_op_rate 1417339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1795416637 # Simulator tick rate (ticks/s) +host_mem_usage 225056 # Number of bytes of host memory used +host_seconds 424.64 # Real time elapsed on the host sim_insts 601856964 # Number of instructions simulated sim_ops 601856964 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 84449 # To system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2136486 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2286664 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 2286664 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4910 # Transaction distribution +system.membus.trans_dist::ReadResp 4910 # Transaction distribution +system.membus.trans_dist::Writeback 1006 # Transaction distribution +system.membus.trans_dist::ReadExReq 21324 # Transaction distribution +system.membus.trans_dist::ReadExResp 21324 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 53474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 53474 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1743360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1743360 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1743360 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 35288000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 236106000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -405,5 +421,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 74969406 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 202027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 202027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 254163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 254163 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1349267 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 57156928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 57156928 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 883425500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1192500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 683092500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index 595117ec0..01544a32c 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164563 # Number of seconds simulated -sim_ticks 164562530500 # Number of ticks simulated -final_tick 164562530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164717 # Number of seconds simulated +sim_ticks 164716794500 # Number of ticks simulated +final_tick 164716794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62422 # Simulator instruction rate (inst/s) -host_op_rate 65960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18020016 # Simulator tick rate (ticks/s) -host_mem_usage 288128 # Number of bytes of host memory used -host_seconds 9132.21 # Real time elapsed on the host +host_inst_rate 131424 # Simulator instruction rate (inst/s) +host_op_rate 138873 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37975042 # Simulator tick rate (ticks/s) +host_mem_usage 246336 # Number of bytes of host memory used +host_seconds 4337.50 # Real time elapsed on the host sim_insts 570051585 # Number of instructions simulated sim_ops 602359791 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1701120 # Number of bytes read from this memory -system.physmem.bytes_read::total 1748096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 47232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1701568 # Number of bytes read from this memory +system.physmem.bytes_read::total 1748800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 47232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 47232 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory system.physmem.bytes_written::total 162368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26580 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27314 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 738 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26587 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27325 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 285460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10337226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10622685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 285460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 285460 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 986664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 986664 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 986664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 285460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10337226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11609350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27315 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 286747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10330264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10617011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 286747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 286747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 985740 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 985740 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 985740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 286747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10330264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11602751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27326 # Total number of read requests seen system.physmem.writeReqs 2537 # Total number of write requests seen -system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1748096 # Total number of bytes read from memory +system.physmem.cpureqs 29863 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1748800 # Total number of bytes read from memory system.physmem.bytesWritten 162368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1748096 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 1748800 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1691 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1759 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1740 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1680 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 163 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1621 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1738 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1816 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1757 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1788 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1779 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1795 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1657 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1673 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1647 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 166 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 158 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 164562514500 # Total gap between requests +system.physmem.totGap 164716777500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27315 # Categorize read packet sizes +system.physmem.readPktSize::6 27326 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,12 +92,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 2537 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 14709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2877 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,8 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see @@ -147,8 +147,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -156,14 +156,87 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 922192000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1672085750 # Sum of mem lat for all requests -system.physmem.totBusLat 136575000 # Total cycles spent in databus access -system.physmem.totBankLat 613318750 # Total cycles spent in bank access -system.physmem.avgQLat 33761.38 # Average queueing delay per request -system.physmem.avgBankLat 22453.55 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 9336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 204.188518 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.332799 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 802.540236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 7834 83.91% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 317 3.40% 87.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 190 2.04% 89.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 83 0.89% 90.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 60 0.64% 90.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 70 0.75% 91.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 60 0.64% 92.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 493 5.28% 97.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 6 0.06% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 7 0.07% 97.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.03% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.04% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.03% 97.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 4 0.04% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.05% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.07% 97.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 0.05% 98.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.05% 98.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.04% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 6 0.06% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.01% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 4 0.04% 98.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.02% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 7 0.07% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.02% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.02% 98.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 4 0.04% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.01% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.01% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.01% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 5 0.05% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 3 0.03% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 4 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.02% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.06% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 7 0.07% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 2 0.02% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.04% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 2 0.02% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.04% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.03% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 6 0.06% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 4 0.04% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.03% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 60 0.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 9336 # Bytes accessed per row activation +system.physmem.totQLat 724618250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1428985750 # Sum of mem lat for all requests +system.physmem.totBusLat 136630000 # Total cycles spent in databus access +system.physmem.totBankLat 567737500 # Total cycles spent in bank access +system.physmem.avgQLat 26517.54 # Average queueing delay per request +system.physmem.avgBankLat 20776.46 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 61214.93 # Average memory access latency +system.physmem.avgMemAccLat 52294.00 # Average memory access latency system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s @@ -171,21 +244,37 @@ system.physmem.avgConsumedWrBW 0.99 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.09 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 5.61 # Average write queue length over time -system.physmem.readRowHits 16878 # Number of row buffer hits during reads -system.physmem.writeRowHits 1046 # Number of row buffer hits during writes -system.physmem.readRowHitRate 61.79 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.23 # Row buffer hit rate for writes -system.physmem.avgGap 5512612.71 # Average gap between requests -system.cpu.branchPred.lookups 85150983 # Number of BP lookups -system.cpu.branchPred.condPredicted 79934550 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2340692 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47125153 # Number of BTB lookups -system.cpu.branchPred.BTBHits 46874770 # Number of BTB hits +system.physmem.avgWrQLen 5.04 # Average write queue length over time +system.physmem.readRowHits 18612 # Number of row buffer hits during reads +system.physmem.writeRowHits 1908 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes +system.physmem.avgGap 5515747.83 # Average gap between requests +system.membus.throughput 11602751 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5535 # Transaction distribution +system.membus.trans_dist::ReadResp 5534 # Transaction distribution +system.membus.trans_dist::Writeback 2537 # Transaction distribution +system.membus.trans_dist::ReadExReq 21791 # Transaction distribution +system.membus.trans_dist::ReadExResp 21791 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 57188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 57188 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1911168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1911168 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1911168 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 59882500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 257832500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.branchPred.lookups 85149850 # Number of BP lookups +system.cpu.branchPred.condPredicted 79935034 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2341119 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 47171100 # Number of BTB lookups +system.cpu.branchPred.BTBHits 46877755 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.468685 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1426734 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1006 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.378126 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1426315 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1039 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,134 +318,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329125062 # number of cpu cycles simulated +system.cpu.numCycles 329433590 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 68488081 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 666859732 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85150983 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48301504 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 129623989 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13095310 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119330996 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 68491080 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 666869934 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85149850 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48304070 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 129626718 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13098656 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119406737 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 265 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 67073182 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 755353 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 328169942 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.165410 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.193997 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 278 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 67075214 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 755042 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 328254094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.164915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.193789 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 198546194 60.50% 60.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20910126 6.37% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4967453 1.51% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14343462 4.37% 72.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8888191 2.71% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9444820 2.88% 78.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4399595 1.34% 79.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5788141 1.76% 81.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 60881960 18.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 198627609 60.51% 60.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20909439 6.37% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4965485 1.51% 68.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14345312 4.37% 72.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8888539 2.71% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9448384 2.88% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4398392 1.34% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5788124 1.76% 81.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 60882810 18.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 328169942 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258719 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.026159 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 92898933 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96237751 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 107895398 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20412735 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10725125 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4735181 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1555 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 703255584 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 5767 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 10725125 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107098247 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14386106 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 39798 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114033717 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 81886949 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 694825042 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59412332 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20333868 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 677 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 721309974 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3230585653 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3230585525 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 328254094 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258473 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.024292 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 92927462 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96288420 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 107921370 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20389102 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10727740 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4734116 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1608 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 703272688 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6032 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10727740 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107129786 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14463787 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40672 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114031737 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81860372 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 694842750 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59365311 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20352093 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 658 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 721318867 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3230668466 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3230668338 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 93892601 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1652 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1598 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 170754110 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172203089 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80461729 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21612175 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28771400 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 679988719 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2878 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 645594653 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1373062 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 77449325 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 193321568 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 174 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 328169942 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.967257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.725062 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 93901494 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1663 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1606 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 170675033 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172203367 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80466872 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21668199 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28984539 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 680005400 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2870 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 645602000 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1370838 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 77464153 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 193377702 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 328254094 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.966775 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.724168 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 68186439 20.78% 20.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85247300 25.98% 46.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 75946350 23.14% 69.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40813735 12.44% 82.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28838397 8.79% 91.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14924394 4.55% 95.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5564389 1.70% 97.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6539948 1.99% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2108990 0.64% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 68222380 20.78% 20.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85248644 25.97% 46.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 76005248 23.15% 69.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 40782290 12.42% 82.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28865696 8.79% 91.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14929305 4.55% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5554109 1.69% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6609349 2.01% 99.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2037073 0.62% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 328169942 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 328254094 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 216923 5.73% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2702396 71.39% 77.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 865914 22.88% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 217031 5.77% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2685741 71.41% 77.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 858362 22.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403371824 62.48% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403375767 62.48% 62.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6562 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued @@ -384,84 +473,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.48% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 165561293 25.64% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76654974 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 165561645 25.64% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76658023 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 645594653 # Type of FU issued -system.cpu.iq.rate 1.961548 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3785233 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005863 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1624517507 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 757453052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 637549292 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 645602000 # Type of FU issued +system.cpu.iq.rate 1.959733 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3761134 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005826 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1624590030 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 757484567 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 637551440 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 649379866 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 649363114 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30368159 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30365020 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23250496 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 123413 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12359 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10240716 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23250774 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 122077 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12388 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10245859 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12899 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 36224 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12881 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 36063 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10725125 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 795867 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 92517 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 679994676 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 687635 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172203089 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80461729 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1550 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32824 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16429 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12359 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1356301 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1461196 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2817497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 641509024 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 163485499 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4085629 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10727740 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 829837 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 90327 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 680011324 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 689748 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172203367 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80466872 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1542 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 33020 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14329 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12388 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1357418 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1460538 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2817956 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 641515531 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163488286 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4086469 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3079 # number of nop insts executed -system.cpu.iew.exec_refs 239366742 # number of memory reference insts executed -system.cpu.iew.exec_branches 74672084 # Number of branches executed -system.cpu.iew.exec_stores 75881243 # Number of stores executed -system.cpu.iew.exec_rate 1.949135 # Inst execution rate -system.cpu.iew.wb_sent 638953926 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 637549308 # cumulative count of insts written-back -system.cpu.iew.wb_producers 418527294 # num instructions producing a value -system.cpu.iew.wb_consumers 649860425 # num instructions consuming a value +system.cpu.iew.exec_nop 3054 # number of nop insts executed +system.cpu.iew.exec_refs 239371647 # number of memory reference insts executed +system.cpu.iew.exec_branches 74671273 # Number of branches executed +system.cpu.iew.exec_stores 75883361 # Number of stores executed +system.cpu.iew.exec_rate 1.947329 # Inst execution rate +system.cpu.iew.wb_sent 638961836 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 637551456 # cumulative count of insts written-back +system.cpu.iew.wb_producers 418605320 # num instructions producing a value +system.cpu.iew.wb_consumers 649951687 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937103 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644026 # average fanout of values written-back +system.cpu.iew.wb_rate 1.935296 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644056 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 77643008 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 77660016 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2339215 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 317444817 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.897526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.237559 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 2339596 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 317526354 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.897039 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.237311 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93252713 29.38% 29.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104341557 32.87% 62.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42984071 13.54% 75.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8786627 2.77% 78.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25947006 8.17% 86.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12913913 4.07% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7624115 2.40% 93.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1170537 0.37% 93.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20424278 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93315961 29.39% 29.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104358414 32.87% 62.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42989043 13.54% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8780083 2.77% 78.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25952112 8.17% 86.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12911096 4.07% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7631938 2.40% 93.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1174119 0.37% 93.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20413588 6.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 317444817 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 317526354 # Number of insts commited each cycle system.cpu.commit.committedInsts 570051636 # Number of instructions committed system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,191 +561,217 @@ system.cpu.commit.branches 70892524 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 533522631 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20424278 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20413588 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 977022777 # The number of ROB reads -system.cpu.rob.rob_writes 1370762747 # The number of ROB writes -system.cpu.timesIdled 43954 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 955120 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 977132012 # The number of ROB reads +system.cpu.rob.rob_writes 1370799549 # The number of ROB writes +system.cpu.timesIdled 46711 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1179496 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 570051585 # Number of Instructions Simulated system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated -system.cpu.cpi 0.577360 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.577360 # CPI: Total CPI of All Threads -system.cpu.ipc 1.732021 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.732021 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3204272502 # number of integer regfile reads -system.cpu.int_regfile_writes 663034338 # number of integer regfile writes +system.cpu.cpi 0.577901 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577901 # CPI: Total CPI of All Threads +system.cpu.ipc 1.730399 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.730399 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3204308856 # number of integer regfile reads +system.cpu.int_regfile_writes 663036750 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 234758554 # number of misc regfile reads +system.cpu.misc_regfile_reads 234764578 # number of misc regfile reads system.cpu.misc_regfile_writes 2656 # number of misc regfile writes -system.cpu.icache.replacements 49 # number of replacements -system.cpu.icache.tagsinuse 688.587828 # Cycle average of tags in use -system.cpu.icache.total_refs 67072069 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 83009.986386 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 336903691 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 198317 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 198316 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 421602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247171 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1310945 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1312578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 52224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55441408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 55493632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 55493632 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 64 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 855147500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1225999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 667010989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu.icache.replacements 51 # number of replacements +system.cpu.icache.tagsinuse 691.196113 # Cycle average of tags in use +system.cpu.icache.total_refs 67074062 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 816 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 82198.605392 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 688.587828 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.336225 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.336225 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67072069 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67072069 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67072069 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67072069 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67072069 # number of overall hits -system.cpu.icache.overall_hits::total 67072069 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1113 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1113 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1113 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1113 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1113 # number of overall misses -system.cpu.icache.overall_misses::total 1113 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 54408499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 54408499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 54408499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 54408499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 54408499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 54408499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67073182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67073182 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67073182 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67073182 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67073182 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67073182 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 691.196113 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.337498 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.337498 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67074062 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67074062 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67074062 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67074062 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67074062 # number of overall hits +system.cpu.icache.overall_hits::total 67074062 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1152 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1152 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1152 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1152 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1152 # number of overall misses +system.cpu.icache.overall_misses::total 1152 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 71751999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 71751999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 71751999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 71751999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 71751999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 71751999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67075214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67075214 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67075214 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67075214 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67075214 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67075214 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000017 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000017 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000017 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000017 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000017 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48884.545373 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48884.545373 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48884.545373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48884.545373 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48884.545373 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62284.721354 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62284.721354 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62284.721354 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62284.721354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62284.721354 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62284.721354 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61.857143 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 304 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 304 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 304 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 304 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 304 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 304 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 809 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 809 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 809 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 809 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 809 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 809 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42322999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42322999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42322999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42322999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42322999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42322999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 335 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 335 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 335 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 335 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 335 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 817 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 817 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 817 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 817 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 817 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 817 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 53391000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 53391000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53391000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 53391000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52315.202719 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52315.202719 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52315.202719 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52315.202719 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52315.202719 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52315.202719 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65350.061200 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65350.061200 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65350.061200 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 65350.061200 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65350.061200 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 65350.061200 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 2559 # number of replacements -system.cpu.l2cache.tagsinuse 22357.775190 # Cycle average of tags in use -system.cpu.l2cache.total_refs 517077 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24151 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 21.410169 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 22356.312317 # Cycle average of tags in use +system.cpu.l2cache.total_refs 517275 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24166 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 21.405073 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20763.745562 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 648.701789 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 945.327839 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.633659 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.019797 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.028849 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.682305 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 74 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 192736 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 192810 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 421641 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 421641 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 225382 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 225382 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 74 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 418118 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 418192 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 74 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 418118 # number of overall hits -system.cpu.l2cache.overall_hits::total 418192 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 735 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.088162 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.088162 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.905637 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.059815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.061364 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.905637 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.059815 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.061364 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70077.131258 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 148662.991471 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 138191.489362 # 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number of cycles access was blocked @@ -668,168 +783,168 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 2537 # number of writebacks system.cpu.l2cache.writebacks::total 2537 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 11 # 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number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1326 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1326 # number of LoadLockedReq hits +system.cpu.dcache.replacements 440574 # number of replacements +system.cpu.dcache.tagsinuse 4091.363669 # Cycle average of tags in use +system.cpu.dcache.total_refs 197559820 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 444670 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 444.284121 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 321256000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4091.363669 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998868 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998868 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 131518279 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 131518279 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 66038889 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 66038889 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1323 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1323 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 197559804 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 197559804 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 197559804 # number of overall hits -system.cpu.dcache.overall_hits::total 197559804 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 341685 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 341685 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3370037 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3370037 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3711722 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3711722 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3711722 # number of overall misses -system.cpu.dcache.overall_misses::total 3711722 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5064964500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5064964500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 40707637762 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 40707637762 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 338000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 338000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45772602262 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45772602262 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45772602262 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45772602262 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 131853995 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 131853995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 197557168 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 197557168 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 197557168 # number of overall hits +system.cpu.dcache.overall_hits::total 197557168 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 341807 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 341807 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3378642 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3378642 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 3720449 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3720449 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3720449 # number of overall misses +system.cpu.dcache.overall_misses::total 3720449 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5118261000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5118261000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 44228568380 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 44228568380 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 392500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 392500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 49346829380 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 49346829380 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 49346829380 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 49346829380 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 131860086 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 131860086 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1348 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1348 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 201271526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 201271526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 201271526 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 201271526 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002591 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002591 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048547 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.048547 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016320 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016320 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.018441 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.018441 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018441 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018441 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14823.490935 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14823.490935 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12079.285112 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 12079.285112 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15363.636364 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15363.636364 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12331.904777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12331.904777 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 146535 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 32 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5250 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 201277617 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201277617 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201277617 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201277617 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048671 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.048671 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.018484 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.018484 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018484 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018484 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14974.125749 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14974.125749 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13090.634752 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13090.634752 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.217391 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.217391 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13263.675804 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13263.675804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13263.675804 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13263.675804 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 148047 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 158 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5424 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.911429 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.294801 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 421641 # number of writebacks -system.cpu.dcache.writebacks::total 421641 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144151 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 144151 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3122863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3122863 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3267014 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3267014 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3267014 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3267014 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197534 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 197534 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247174 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 247174 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 444708 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 444708 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 444708 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 444708 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2832398000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2832398000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097760821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097760821 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6930158821 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6930158821 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6930158821 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6930158821 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 421602 # number of writebacks +system.cpu.dcache.writebacks::total 421602 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144306 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 144306 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3131471 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3131471 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 23 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 23 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3275777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3275777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3275777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3275777 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197501 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 197501 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247171 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 247171 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 444672 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 444672 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 444672 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 444672 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2858072011 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2858072011 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4363789439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4363789439 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7221861450 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7221861450 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7221861450 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7221861450 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses @@ -838,14 +953,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002209 system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14338.787247 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14338.787247 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16578.446038 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16578.446038 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14471.177417 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14471.177417 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17654.941069 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17654.941069 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16240.872936 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16240.872936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16240.872936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16240.872936 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index 0212f6dff..e6e533fb5 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu sim_ticks 301191365000 # Number of ticks simulated final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1714897 # Simulator instruction rate (inst/s) -host_op_rate 1812090 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 906079333 # Simulator tick rate (ticks/s) -host_mem_usage 278712 # Number of bytes of host memory used -host_seconds 332.41 # Real time elapsed on the host +host_inst_rate 1664644 # Simulator instruction rate (inst/s) +host_op_rate 1758990 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 879528148 # Simulator tick rate (ticks/s) +host_mem_usage 233480 # Number of bytes of host memory used +host_seconds 342.45 # Real time elapsed on the host sim_insts 570051636 # Number of instructions simulated sim_ops 602359842 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 784748962 # Wr system.physmem.bw_total::cpu.inst 7570927872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2112350170 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9683278042 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9683278042 # Throughput (bytes/s) +system.membus.data_through_bus 2916519731 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 42a2fd6fd..f13bbbf22 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.793670 # Nu sim_ticks 793670137000 # Number of ticks simulated final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 904187 # Simulator instruction rate (inst/s) -host_op_rate 954854 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1262227313 # Simulator tick rate (ticks/s) -host_mem_usage 287296 # Number of bytes of host memory used -host_seconds 628.79 # Real time elapsed on the host +host_inst_rate 583678 # Simulator instruction rate (inst/s) +host_op_rate 616385 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 814802699 # Simulator tick rate (ticks/s) +host_mem_usage 241980 # Number of bytes of host memory used +host_seconds 974.06 # Real time elapsed on the host sim_insts 568539335 # Number of instructions simulated sim_ops 600398272 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 201031 # To system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 2360195 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4941 # Transaction distribution +system.membus.trans_dist::ReadResp 4941 # Transaction distribution +system.membus.trans_dist::Writeback 2493 # Transaction distribution +system.membus.trans_dist::ReadExReq 21835 # Transaction distribution +system.membus.trans_dist::ReadExResp 21835 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 56045 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 56045 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1873216 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1873216 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1873216 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 49213000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 240984000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 69093329 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 190459 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 190459 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 418626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247748 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1286 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1293754 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1295040 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 41152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 54796160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 54837312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 54837312 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 847042500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 964500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 656346000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt index fc36793dc..812998109 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.387291 # Number of seconds simulated -sim_ticks 387290918500 # Number of ticks simulated -final_tick 387290918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.387399 # Number of seconds simulated +sim_ticks 387398892000 # Number of ticks simulated +final_tick 387398892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75176 # Simulator instruction rate (inst/s) -host_op_rate 75413 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20778674 # Simulator tick rate (ticks/s) -host_mem_usage 280588 # Number of bytes of host memory used -host_seconds 18638.87 # Real time elapsed on the host +host_inst_rate 157866 # Simulator instruction rate (inst/s) +host_op_rate 158364 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43646663 # Simulator tick rate (ticks/s) +host_mem_usage 236680 # Number of bytes of host memory used +host_seconds 8875.80 # Real time elapsed on the host sim_insts 1401188945 # Number of instructions simulated sim_ops 1405604139 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 76672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1678656 # Number of bytes read from this memory -system.physmem.bytes_read::total 1755328 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 76672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 76672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory -system.physmem.bytes_written::total 162112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1198 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26229 # Number of read requests responded to by this memory -system.physmem.num_reads::total 27427 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 197970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4334354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4532324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197970 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197970 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 418579 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 418579 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 418579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4334354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4950904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 27428 # Total number of read requests seen -system.physmem.writeReqs 2533 # Total number of write requests seen -system.physmem.cpureqs 29961 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1755328 # Total number of bytes read from memory -system.physmem.bytesWritten 162112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1755328 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 76288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1678592 # Number of bytes read from this memory +system.physmem.bytes_read::total 1754880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162048 # Number of bytes written to this memory +system.physmem.bytes_written::total 162048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1192 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26228 # Number of read requests responded to by this memory +system.physmem.num_reads::total 27420 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 2532 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2532 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 196924 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4332981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4529905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 196924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 196924 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 418298 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 418298 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 418298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 196924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4332981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4948202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 27421 # Total number of read requests seen +system.physmem.writeReqs 2532 # Total number of write requests seen +system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1754880 # Total number of bytes read from memory +system.physmem.bytesWritten 162048 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1754880 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162048 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1674 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1884 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1775 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1871 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1665 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1646 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1602 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1689 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1531 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1801 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 152 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 149 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 155 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 162 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 387290890500 # Total gap between requests +system.physmem.totGap 387398864000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 27428 # Categorize read packet sizes +system.physmem.readPktSize::6 27421 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2533 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 8079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 13230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 5144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2532 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 9983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 520 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -124,9 +124,9 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see @@ -147,8 +147,8 @@ system.physmem.wrQLenPdf::19 110 # Wh system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -156,14 +156,99 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 716281750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 1441798000 # Sum of mem lat for all requests -system.physmem.totBusLat 137140000 # Total cycles spent in databus access -system.physmem.totBankLat 588376250 # Total cycles spent in bank access -system.physmem.avgQLat 26114.98 # Average queueing delay per request -system.physmem.avgBankLat 21451.66 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 9394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 203.806685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 84.980950 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 820.153394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 8091 86.13% 86.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 139 1.48% 87.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 97 1.03% 88.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 115 1.22% 89.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 131 1.39% 91.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 46 0.49% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 57 0.61% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 495 5.27% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.05% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 8 0.09% 97.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 8 0.09% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 0.06% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 0.06% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 3 0.03% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.03% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.05% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.01% 98.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.01% 98.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 7 0.07% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.03% 98.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.03% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.02% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.02% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.03% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.01% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.03% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 3 0.03% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.02% 98.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 3 0.03% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.02% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 3 0.03% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.02% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.02% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.01% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.01% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.01% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 2 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.01% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 2 0.02% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.02% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 2 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.01% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.03% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.02% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 1 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 2 0.02% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 2 0.02% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 3 0.03% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.04% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.03% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 3 0.03% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 63 0.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 9394 # Bytes accessed per row activation +system.physmem.totQLat 539470500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 1246251750 # Sum of mem lat for all requests +system.physmem.totBusLat 137105000 # Total cycles spent in databus access +system.physmem.totBankLat 569676250 # Total cycles spent in bank access +system.physmem.avgQLat 19673.63 # Average queueing delay per request +system.physmem.avgBankLat 20775.18 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52566.65 # Average memory access latency +system.physmem.avgMemAccLat 45448.81 # Average memory access latency system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s @@ -171,252 +256,268 @@ system.physmem.avgConsumedWrBW 0.42 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 17.33 # Average write queue length over time -system.physmem.readRowHits 17584 # Number of row buffer hits during reads -system.physmem.writeRowHits 1051 # Number of row buffer hits during writes -system.physmem.readRowHitRate 64.11 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.49 # Row buffer hit rate for writes -system.physmem.avgGap 12926500.80 # Average gap between requests -system.cpu.branchPred.lookups 97760274 # Number of BP lookups -system.cpu.branchPred.condPredicted 88050389 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 3615826 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 65794197 # Number of BTB lookups -system.cpu.branchPred.BTBHits 65495164 # Number of BTB hits +system.physmem.avgWrQLen 16.43 # Average write queue length over time +system.physmem.readRowHits 18651 # Number of row buffer hits during reads +system.physmem.writeRowHits 1906 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.28 # Row buffer hit rate for writes +system.physmem.avgGap 12933558.04 # Average gap between requests +system.membus.throughput 4948202 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5633 # Transaction distribution +system.membus.trans_dist::ReadResp 5632 # Transaction distribution +system.membus.trans_dist::Writeback 2532 # Transaction distribution +system.membus.trans_dist::ReadExReq 21788 # Transaction distribution +system.membus.trans_dist::ReadExResp 21788 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 57373 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 57373 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1916928 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1916928 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1916928 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 57596000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 256936750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.branchPred.lookups 97761890 # Number of BP lookups +system.cpu.branchPred.condPredicted 88051950 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 3615398 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 65795011 # Number of BTB lookups +system.cpu.branchPred.BTBHits 65493795 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.545502 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.542190 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1333 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 49 # Number of system calls -system.cpu.numCycles 774581838 # number of cpu cycles simulated +system.cpu.numCycles 774797785 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 164861421 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1642294018 # Number of instructions fetch has processed -system.cpu.fetch.Branches 97760274 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 65496491 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 329212106 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20844019 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 263270886 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2530 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 161941896 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 736850 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 774347981 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.126883 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.146753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 164870049 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1642248421 # Number of instructions fetch has processed +system.cpu.fetch.Branches 97761890 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 65495128 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 329214190 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20840770 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 263425370 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2796 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 161945451 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 735894 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 774503521 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.126508 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.146615 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 445135875 57.49% 57.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 74066133 9.56% 67.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 37898132 4.89% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 9078559 1.17% 73.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28105360 3.63% 76.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18771878 2.42% 79.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 11487710 1.48% 80.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3792341 0.49% 81.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 146011993 18.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 445289331 57.49% 57.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 74062894 9.56% 67.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37897346 4.89% 71.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 9078563 1.17% 73.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28105911 3.63% 76.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18772818 2.42% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 11485706 1.48% 80.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3794812 0.49% 81.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 146016140 18.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 774347981 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.120233 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 216009984 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 214299096 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 284224623 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 42813319 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 17000959 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 1636588191 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 17000959 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 239857670 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36775472 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52409372 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 302053149 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 126251359 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1625741176 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 30927043 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 73283464 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 3120923 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1356412040 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2746512805 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2712406209 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34106596 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 774503521 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.126177 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.119583 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 216045393 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 214430589 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 284206110 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 42830421 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 16991008 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 1636611354 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 16991008 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 239885098 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36871695 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52473274 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 302059993 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 126222453 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1625714374 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 30924746 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 73227733 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 3172404 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1356421780 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2746534895 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2712238159 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34296736 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 111641601 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2643056 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2663342 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271532800 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 436949673 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 179753673 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 254530912 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 83488154 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1512578374 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2608372 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1459383903 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 52245 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 109279211 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 130205744 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 364701 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 774347981 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.884662 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.431358 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 111651341 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2642938 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2663443 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 271529341 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 436963345 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 179743092 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 254343956 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 83161988 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1512506564 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2608276 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1459339733 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 53312 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 109205745 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 130222811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 364605 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 774503521 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.884226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.431683 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 145644273 18.81% 18.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 184515384 23.83% 42.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 209689604 27.08% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 131356597 16.96% 86.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 70636694 9.12% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20383529 2.63% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8079794 1.04% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3860513 0.50% 99.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181593 0.02% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 145873373 18.83% 18.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 184398139 23.81% 42.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 209824996 27.09% 69.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131195131 16.94% 86.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 70728709 9.13% 95.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 20383962 2.63% 98.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8004266 1.03% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3913593 0.51% 99.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 181352 0.02% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 774347981 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 774503521 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 108798 6.48% 6.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 95504 5.69% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1157743 69.01% 81.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 315646 18.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 114122 6.75% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 97466 5.77% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1164668 68.90% 81.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 314034 18.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 866498027 59.37% 59.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 866437474 59.37% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2644895 0.18% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 419117526 28.72% 88.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 171123455 11.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2644764 0.18% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 419138356 28.72% 88.27% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 171119139 11.73% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1459383903 # Type of FU issued -system.cpu.iq.rate 1.884093 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1677691 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001150 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3677006053 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1615499463 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1443256661 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 17839670 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9205608 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 8545927 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1451932919 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 9128675 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 215271062 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1459339733 # Type of FU issued +system.cpu.iq.rate 1.883510 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1690290 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3677004243 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1615280670 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1443165364 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 17922346 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9279147 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 8546420 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1451856157 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 9173866 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 215403822 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 34436830 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 58273 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 245758 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 12905531 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 34450502 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 58568 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 246048 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 12894950 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3343 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 99974 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 138899 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 17000959 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3021185 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 246438 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1608872021 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 4125769 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 436949673 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 179753673 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2525299 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 148197 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1793 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 245758 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 2269874 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1473729 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 3743603 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1454064480 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 416571691 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 5319423 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 16991008 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3096733 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 244441 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1608794631 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 4137633 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 436963345 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 179743092 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2525201 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 147095 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1875 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 246048 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2270642 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1473051 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 3743693 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1454012420 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 416588335 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 5327313 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 93685275 # number of nop insts executed -system.cpu.iew.exec_refs 587019661 # number of memory reference insts executed -system.cpu.iew.exec_branches 89035299 # Number of branches executed -system.cpu.iew.exec_stores 170447970 # Number of stores executed -system.cpu.iew.exec_rate 1.877225 # Inst execution rate -system.cpu.iew.wb_sent 1452686018 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1451802588 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1153472607 # num instructions producing a value -system.cpu.iew.wb_consumers 1204727325 # num instructions consuming a value +system.cpu.iew.exec_nop 93679791 # number of nop insts executed +system.cpu.iew.exec_refs 587032224 # number of memory reference insts executed +system.cpu.iew.exec_branches 89032109 # Number of branches executed +system.cpu.iew.exec_stores 170443889 # Number of stores executed +system.cpu.iew.exec_rate 1.876635 # Inst execution rate +system.cpu.iew.wb_sent 1452595352 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1451711784 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1153369073 # num instructions producing a value +system.cpu.iew.wb_consumers 1204594740 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.874305 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.957455 # average fanout of values written-back +system.cpu.iew.wb_rate 1.873665 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.957475 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119253312 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 119176384 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 3615826 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 757347022 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.966765 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.509958 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 3615398 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 757512513 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.966335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.509470 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 240030131 31.69% 31.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 275730182 36.41% 68.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 42558160 5.62% 73.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 54684817 7.22% 80.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19637761 2.59% 83.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 13291596 1.76% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 30564343 4.04% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10573009 1.40% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70277023 9.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 240122511 31.70% 31.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 275742858 36.40% 68.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 42578645 5.62% 73.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 54721179 7.22% 80.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19701382 2.60% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13286584 1.75% 85.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 30581396 4.04% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10490891 1.38% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 70287067 9.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 757347022 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 757512513 # Number of insts commited each cycle system.cpu.commit.committedInsts 1485108088 # Number of instructions committed system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -427,192 +528,212 @@ system.cpu.commit.branches 86248928 # Nu system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions. system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions. system.cpu.commit.function_calls 1206914 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70277023 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 70287067 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2295781723 # The number of ROB reads -system.cpu.rob.rob_writes 3234577019 # The number of ROB writes -system.cpu.timesIdled 25986 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 233857 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2295860242 # The number of ROB reads +system.cpu.rob.rob_writes 3234413109 # The number of ROB writes +system.cpu.timesIdled 27770 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 294264 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1401188945 # Number of Instructions Simulated system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated -system.cpu.cpi 0.552803 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.552803 # CPI: Total CPI of All Threads -system.cpu.ipc 1.808962 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.808962 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1979163604 # number of integer regfile reads -system.cpu.int_regfile_writes 1275210426 # number of integer regfile writes -system.cpu.fp_regfile_reads 16962684 # number of floating regfile reads -system.cpu.fp_regfile_writes 10491940 # number of floating regfile writes -system.cpu.misc_regfile_reads 592672173 # number of misc regfile reads +system.cpu.cpi 0.552957 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.552957 # CPI: Total CPI of All Threads +system.cpu.ipc 1.808458 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.808458 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1979095871 # number of integer regfile reads +system.cpu.int_regfile_writes 1275125772 # number of integer regfile writes +system.cpu.fp_regfile_reads 16962854 # number of floating regfile reads +system.cpu.fp_regfile_writes 10491602 # number of floating regfile writes +system.cpu.misc_regfile_reads 592684666 # number of misc regfile reads system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes -system.cpu.icache.replacements 197 # number of replacements -system.cpu.icache.tagsinuse 1035.819290 # Cycle average of tags in use -system.cpu.icache.total_refs 161939953 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 121031.355007 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 150116939 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 202209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 202208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 444002 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1370676 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1373347 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 85440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58069696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 58155136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 58155136 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 898339500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2002500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 695005500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.icache.replacements 199 # number of replacements +system.cpu.icache.tagsinuse 1032.766528 # Cycle average of tags in use +system.cpu.icache.total_refs 161943463 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1335 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 121305.964794 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1035.819290 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.505771 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.505771 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161939953 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161939953 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161939953 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161939953 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161939953 # number of overall hits -system.cpu.icache.overall_hits::total 161939953 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses -system.cpu.icache.overall_misses::total 1943 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 84888000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 84888000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 84888000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 84888000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 84888000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 84888000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 161941896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 161941896 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 161941896 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 161941896 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 161941896 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 161941896 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1032.766528 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.504281 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.504281 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161943463 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161943463 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161943463 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161943463 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161943463 # number of overall hits +system.cpu.icache.overall_hits::total 161943463 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1988 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1988 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1988 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1988 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1988 # number of overall misses +system.cpu.icache.overall_misses::total 1988 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115233000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115233000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115233000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115233000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115233000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115233000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 161945451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 161945451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 161945451 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 161945451 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 161945451 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 161945451 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000012 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000012 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000012 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000012 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43689.140504 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43689.140504 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43689.140504 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43689.140504 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43689.140504 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43689.140504 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57964.285714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 57964.285714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 57964.285714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 57964.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 57964.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 57964.285714 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 604 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 604 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 604 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 604 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 604 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 604 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62446000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 62446000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62446000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 62446000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62446000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 62446000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 652 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 652 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 652 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 652 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 652 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 652 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1336 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1336 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1336 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1336 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1336 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1336 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 82779000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 82779000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 82779000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 82779000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 82779000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 82779000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000008 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000008 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000008 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000008 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46636.295743 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46636.295743 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46636.295743 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 46636.295743 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46636.295743 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 46636.295743 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61960.329341 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61960.329341 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61960.329341 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61960.329341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61960.329341 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61960.329341 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2556 # number of replacements -system.cpu.l2cache.tagsinuse 22452.577609 # Cycle average of tags in use -system.cpu.l2cache.total_refs 550279 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 24276 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 22.667614 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 2555 # number of replacements +system.cpu.l2cache.tagsinuse 22446.824248 # Cycle average of tags in use +system.cpu.l2cache.total_refs 550534 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 24268 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 22.685594 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 20742.053836 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1060.970953 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 649.552820 # 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average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 107120.495495 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 98636.605716 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86369.217000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86369.217000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67062.028500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89882.091658 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88889.263703 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67062.028500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89882.091658 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88889.263703 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # 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mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54653.185247 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 94808.783784 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 86304.322741 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73989.512576 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73989.512576 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54653.185247 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77513.897362 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76519.300901 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54653.185247 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77513.897362 # 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number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 200258461 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 164955659 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 164955659 # number of WriteReq hits +system.cpu.dcache.replacements 459241 # number of replacements +system.cpu.dcache.tagsinuse 4093.680719 # Cycle average of tags in use +system.cpu.dcache.total_refs 365075170 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 463337 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 787.925786 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 357850000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4093.680719 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999434 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999434 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 200118468 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 200118468 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 164955383 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 164955383 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 1319 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 365214120 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 365214120 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 365214120 # number of overall hits -system.cpu.dcache.overall_hits::total 365214120 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 922594 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 922594 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1891157 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1891157 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 365073851 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 365073851 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 365073851 # number of overall hits +system.cpu.dcache.overall_hits::total 365073851 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907674 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907674 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1891433 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1891433 # number of WriteReq misses system.cpu.dcache.SwapReq_misses::cpu.data 7 # number of SwapReq misses system.cpu.dcache.SwapReq_misses::total 7 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 2813751 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2813751 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2813751 # number of overall misses -system.cpu.dcache.overall_misses::total 2813751 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14741568500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14741568500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31920810636 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31920810636 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 150000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 150000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46662379136 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46662379136 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46662379136 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46662379136 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 201181055 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 201181055 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2799107 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2799107 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2799107 # number of overall misses +system.cpu.dcache.overall_misses::total 2799107 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14763566000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14763566000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33756143071 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33756143071 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 142000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 142000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48519709071 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48519709071 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48519709071 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48519709071 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 201026142 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 201026142 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 166846816 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 1326 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 368027871 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 368027871 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 368027871 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 368027871 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004586 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004586 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011335 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011335 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 367872958 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 367872958 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 367872958 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 367872958 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004515 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004515 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011336 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011336 # miss rate for WriteReq accesses system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.005279 # miss rate for SwapReq accesses system.cpu.dcache.SwapReq_miss_rate::total 0.005279 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007645 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007645 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007645 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007645 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15978.391904 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15978.391904 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16878.985000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16878.985000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 21428.571429 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 21428.571429 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16583.691711 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16583.691711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16583.691711 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16583.691711 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 590874 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 35646 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.576166 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.007609 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007609 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007609 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007609 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16265.273656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16265.273656 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17846.861650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 17846.861650 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 20285.714286 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 20285.714286 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17333.995832 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17333.995832 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17333.995832 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17333.995832 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 694627 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 38063 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.249402 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 46 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 443878 # number of writebacks -system.cpu.dcache.writebacks::total 443878 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721765 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 721765 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628742 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1628742 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2350507 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2350507 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2350507 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2350507 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200829 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 200829 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262415 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 262415 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 444002 # number of writebacks +system.cpu.dcache.writebacks::total 444002 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 706801 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 706801 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628976 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1628976 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2335777 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2335777 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2335777 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2335777 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200873 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 200873 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262457 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 262457 # number of WriteReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 463244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 463244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 463244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 463244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2611858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2611858000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4360853500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4360853500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6972711500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6972711500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6972711500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6972711500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 463330 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 463330 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 463330 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 463330 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643681500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643681500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4650895000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4650895000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 128000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 128000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7294576500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7294576500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7294576500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7294576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses @@ -785,16 +906,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001259 system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.382689 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.382689 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16618.156355 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16618.156355 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13160.959910 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13160.959910 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17720.598041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17720.598041 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 18285.714286 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 18285.714286 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15743.803553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15743.803553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15743.803553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15743.803553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt index 9073b6f33..b5f7d83aa 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.744764 # Nu sim_ticks 744764112500 # Number of ticks simulated final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2243211 # Simulator instruction rate (inst/s) -host_op_rate 2249879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1124943447 # Simulator tick rate (ticks/s) -host_mem_usage 273192 # Number of bytes of host memory used -host_seconds 662.05 # Real time elapsed on the host +host_inst_rate 3917871 # Simulator instruction rate (inst/s) +host_op_rate 3929519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1964765726 # Simulator tick rate (ticks/s) +host_mem_usage 224984 # Number of bytes of host memory used +host_seconds 379.06 # Real time elapsed on the host sim_insts 1485108088 # Number of instructions simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory @@ -35,6 +35,9 @@ system.physmem.bw_write::total 825324492 # Wr system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2686071498 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10662358072 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10662372316 # Throughput (bytes/s) +system.membus.data_through_bus 7940952255 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 1489528226 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt index 226830c92..860c680b8 100644 --- a/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.061066 # Nu sim_ticks 2061066313000 # Number of ticks simulated final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1083437 # Simulator instruction rate (inst/s) -host_op_rate 1086658 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1503618533 # Simulator tick rate (ticks/s) -host_mem_usage 281644 # Number of bytes of host memory used -host_seconds 1370.74 # Real time elapsed on the host +host_inst_rate 684045 # Simulator instruction rate (inst/s) +host_op_rate 686079 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 949333559 # Simulator tick rate (ticks/s) +host_mem_usage 233488 # Number of bytes of host memory used +host_seconds 2171.07 # Real time elapsed on the host sim_insts 1485108088 # Number of instructions simulated sim_ops 1489523282 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 78189 # To system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 921310 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5293 # Transaction distribution +system.membus.trans_dist::ReadResp 5293 # Transaction distribution +system.membus.trans_dist::Writeback 2518 # Transaction distribution +system.membus.trans_dist::ReadExReq 21859 # Transaction distribution +system.membus.trans_dist::ReadExResp 21859 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 56822 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 56822 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1898880 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 1898880 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1898880 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 49814000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 244368000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 49 # Number of system calls system.cpu.numCycles 4122132626 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -393,5 +409,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 27625902 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 194593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 194593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 435341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 259735 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 259735 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2214 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1341783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1343997 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 70848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56867968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 56938816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56938816 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 880175500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1660500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 679831500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt index b2e32248a..29e9634dd 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.602332 # Number of seconds simulated -sim_ticks 602332345500 # Number of ticks simulated -final_tick 602332345500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.602519 # Number of seconds simulated +sim_ticks 602519213000 # Number of ticks simulated +final_tick 602519213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59375 # Simulator instruction rate (inst/s) -host_op_rate 109402 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40639301 # Simulator tick rate (ticks/s) -host_mem_usage 298404 # Number of bytes of host memory used -host_seconds 14821.42 # Real time elapsed on the host +host_inst_rate 94132 # Simulator instruction rate (inst/s) +host_op_rate 173444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64448799 # Simulator tick rate (ticks/s) +host_mem_usage 251596 # Number of bytes of host memory used +host_seconds 9348.80 # Real time elapsed on the host sim_insts 880025277 # Number of instructions simulated sim_ops 1621493927 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 57280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 57152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory system.physmem.bytes_read::total 1750464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 57280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 57280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 162240 # Number of bytes written to this memory -system.physmem.bytes_written::total 162240 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 57152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 57152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory +system.physmem.bytes_written::total 162112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 893 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory system.physmem.num_reads::total 27351 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 2535 # Number of write requests responded to by this memory -system.physmem.num_writes::total 2535 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 95097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2811046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2906143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 95097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 95097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 269353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 269353 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 269353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 95097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2811046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3175496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 94855 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2810387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2905242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 94855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 94855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 269057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 269057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 269057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 94855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2810387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3174299 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 27351 # Total number of read requests seen -system.physmem.writeReqs 2535 # Total number of write requests seen -system.physmem.cpureqs 29886 # Reqs generatd by CPU via cache - shady +system.physmem.writeReqs 2533 # Total number of write requests seen +system.physmem.cpureqs 29884 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 1750464 # Total number of bytes read from memory -system.physmem.bytesWritten 162240 # Total number of bytes written to memory +system.physmem.bytesWritten 162112 # Total number of bytes written to memory system.physmem.bytesConsumedRd 1750464 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 162240 # bytesWritten derated as per pkt->getSize() +system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1741 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1657 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1659 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1713 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1703 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1737 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1742 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 1661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1729 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1565 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1748 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1766 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1802 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1763 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1767 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1734 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1727 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1630 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 168 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 156 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 147 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 162 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 159 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 602332206500 # Total gap between requests +system.physmem.totGap 602519006000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -91,13 +91,13 @@ system.physmem.writePktSize::2 0 # Ca system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 2535 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 26932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 72 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2533 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 26975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 303 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -127,8 +127,8 @@ system.physmem.rdQLenPdf::31 0 # Wh system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see @@ -156,14 +156,82 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 88037750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 893262750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 9709 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 196.647235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 83.287733 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 790.384353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 8486 87.40% 87.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 125 1.29% 88.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 100 1.03% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 90 0.93% 90.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 83 0.85% 91.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 70 0.72% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 47 0.48% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 479 4.93% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 8 0.08% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3 0.03% 97.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.04% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2 0.02% 97.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 5 0.05% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 2 0.02% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 8 0.08% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 3 0.03% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 9 0.09% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.05% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.02% 98.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.04% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.04% 98.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.03% 98.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 4 0.04% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.01% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.01% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 5 0.05% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 7 0.07% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.02% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 4 0.04% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.04% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 9 0.09% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 13 0.13% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.01% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.03% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.05% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 4 0.04% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 5 0.05% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 2 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 4 0.04% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.02% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 60 0.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 9709 # Bytes accessed per row activation +system.physmem.totQLat 62966000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 815954750 # Sum of mem lat for all requests system.physmem.totBusLat 136755000 # Total cycles spent in databus access -system.physmem.totBankLat 668470000 # Total cycles spent in bank access -system.physmem.avgQLat 3218.81 # Average queueing delay per request -system.physmem.avgBankLat 24440.42 # Average bank access latency per request +system.physmem.totBankLat 616233750 # Total cycles spent in bank access +system.physmem.avgQLat 2302.15 # Average queueing delay per request +system.physmem.avgBankLat 22530.57 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32659.24 # Average memory access latency +system.physmem.avgMemAccLat 29832.72 # Average memory access latency system.physmem.avgRdBW 2.91 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.91 # Average consumed read bandwidth in MB/s @@ -171,146 +239,167 @@ system.physmem.avgConsumedWrBW 0.27 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time -system.physmem.avgWrQLen 8.01 # Average write queue length over time -system.physmem.readRowHits 16404 # Number of row buffer hits during reads -system.physmem.writeRowHits 1020 # Number of row buffer hits during writes -system.physmem.readRowHitRate 59.98 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.24 # Row buffer hit rate for writes -system.physmem.avgGap 20154326.66 # Average gap between requests -system.cpu.branchPred.lookups 155894666 # Number of BP lookups -system.cpu.branchPred.condPredicted 155894666 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25699129 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80742532 # Number of BTB lookups -system.cpu.branchPred.BTBHits 80542859 # Number of BTB hits +system.physmem.avgWrQLen 7.81 # Average write queue length over time +system.physmem.readRowHits 18284 # Number of row buffer hits during reads +system.physmem.writeRowHits 1888 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.54 # Row buffer hit rate for writes +system.physmem.avgGap 20161926.32 # Average gap between requests +system.membus.throughput 3174299 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5448 # Transaction distribution +system.membus.trans_dist::ReadResp 5448 # Transaction distribution +system.membus.trans_dist::Writeback 2533 # Transaction distribution +system.membus.trans_dist::ReadExReq 21903 # Transaction distribution +system.membus.trans_dist::ReadExResp 21903 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 57235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 57235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 57235 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 57235 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1912576 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1912576 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 54010000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 256633000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 156229699 # Number of BP lookups +system.cpu.branchPred.condPredicted 156229699 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25700090 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80130735 # Number of BTB lookups +system.cpu.branchPred.BTBHits 79954590 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.752704 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 2586842 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5513 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.780178 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 2760708 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5575 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 1204664695 # number of cpu cycles simulated +system.cpu.numCycles 1205038430 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175314236 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1434822441 # Number of instructions fetch has processed -system.cpu.fetch.Branches 155894666 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 83129701 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 393116244 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 83893731 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 577823849 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 123 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 791 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 184597714 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11658023 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1204295068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.043367 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.243240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 175276442 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1436709759 # Number of instructions fetch has processed +system.cpu.fetch.Branches 156229699 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 82715298 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 393071073 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 83888584 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 578277772 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 906 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 184712777 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11835246 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1204659879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.045547 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.246119 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 818096949 67.93% 67.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 26918487 2.24% 70.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 12895052 1.07% 71.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20223867 1.68% 72.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26382325 2.19% 75.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 18061341 1.50% 76.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 31920988 2.65% 79.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 38294164 3.18% 82.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 211501895 17.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 818506882 67.95% 67.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 26870857 2.23% 70.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 12535228 1.04% 71.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20195142 1.68% 72.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26380482 2.19% 75.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 18063889 1.50% 76.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31357703 2.60% 79.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 38322925 3.18% 82.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212426771 17.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1204295068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129409 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.191055 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 284492311 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 500325603 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 268669661 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 92767668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 58039825 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2310318754 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 58039825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 333414311 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 124348906 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 3625 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 298566996 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 389921405 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2218156227 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 243059098 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 121762189 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2583430749 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5648758417 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5648752173 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6244 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1204659879 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.129647 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.192252 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 284492310 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 500755512 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 268717714 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 92660799 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 58033544 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2310812595 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 58033544 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 333444734 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 124733131 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 3847 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 298470128 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 389974495 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2217748571 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12521 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 243097280 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 121807098 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2582807342 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5647663149 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5647656949 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 6200 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 696535489 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 103 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 737453259 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 525280959 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 216617119 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 339037703 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 144743699 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1968663502 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 332 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1774132594 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 144752 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 346851970 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 707722705 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1204295068 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.473171 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.418728 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 695912082 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 105 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 105 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 737293343 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 525275195 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 216586351 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 339249104 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 144696192 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1968455796 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 343 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1773948225 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 152074 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 346640912 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 707550278 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 294 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1204659879 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.472572 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.418644 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 354010440 29.40% 29.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 362491598 30.10% 59.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234089313 19.44% 78.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 140647652 11.68% 90.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 60236623 5.00% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 39446291 3.28% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 10873538 0.90% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1896665 0.16% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 602948 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 354366536 29.42% 29.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 362605011 30.10% 59.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234071294 19.43% 78.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 140518579 11.66% 90.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 60300441 5.01% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 39440661 3.27% 98.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 10869049 0.90% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1880938 0.16% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 607370 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1204295068 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1204659879 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 400252 14.21% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2198563 78.06% 92.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 217598 7.73% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 405736 14.35% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2202072 77.90% 92.25% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 219007 7.75% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 46812295 2.64% 2.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1058825283 59.68% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 18980 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 398 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 46812378 2.64% 2.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1058677272 59.68% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 18975 0.00% 62.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 392 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.32% # Type of FU issued @@ -337,84 +426,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.32% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 476287231 26.85% 89.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 192188407 10.83% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 476256932 26.85% 89.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 192182276 10.83% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1774132594 # Type of FU issued -system.cpu.iq.rate 1.472719 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2816413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.001587 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4755521042 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2315690389 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1716753140 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 379 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1840 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1730136533 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 179 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210301951 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1773948225 # Type of FU issued +system.cpu.iq.rate 1.472109 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2826815 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.001594 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4755534756 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2315271702 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1716628380 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 462 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1729962441 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 210357388 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 106238837 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 40588 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 180694 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 28431061 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 106233073 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 38741 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 180751 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 28400293 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2329 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2345 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 48 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 58039825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1222123 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 102210 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1968663834 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63066910 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 525280959 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 216617119 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49147 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2813 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 180694 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1387767 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 24439207 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25826974 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1757694663 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 472697091 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 16437931 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 58033544 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1572366 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 106573 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1968456139 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 63007739 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 525275195 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 216586351 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 94 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49655 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2783 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 180751 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1386811 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 24440636 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25827447 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1757502391 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 472605363 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 16445834 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 664152329 # number of memory reference insts executed -system.cpu.iew.exec_branches 110147604 # Number of branches executed -system.cpu.iew.exec_stores 191455238 # Number of stores executed -system.cpu.iew.exec_rate 1.459074 # Inst execution rate -system.cpu.iew.wb_sent 1717478326 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1716753232 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1259860051 # num instructions producing a value -system.cpu.iew.wb_consumers 1819503625 # num instructions consuming a value +system.cpu.iew.exec_refs 664057082 # number of memory reference insts executed +system.cpu.iew.exec_branches 110136743 # Number of branches executed +system.cpu.iew.exec_stores 191451719 # Number of stores executed +system.cpu.iew.exec_rate 1.458462 # Inst execution rate +system.cpu.iew.wb_sent 1717351615 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1716628496 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1259714523 # num instructions producing a value +system.cpu.iew.wb_consumers 1819339484 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.425088 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692420 # average fanout of values written-back +system.cpu.iew.wb_rate 1.424543 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 347171319 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 346963425 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25699242 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1146255243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.414601 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.834752 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25700222 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1146626335 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.414143 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.834829 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 413178457 36.05% 36.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 412793718 36.01% 72.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 87651437 7.65% 79.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 122127525 10.65% 90.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 23936453 2.09% 92.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25493357 2.22% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 16343741 1.43% 96.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 12104723 1.06% 97.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 32625832 2.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 413585484 36.07% 36.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 412792006 36.00% 72.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 87637452 7.64% 79.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 122098814 10.65% 90.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 23946599 2.09% 92.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25447448 2.22% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 16362955 1.43% 96.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 12115407 1.06% 97.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 32640170 2.85% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1146255243 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1146626335 # Number of insts commited each cycle system.cpu.commit.committedInsts 880025277 # Number of instructions committed system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -425,195 +514,217 @@ system.cpu.commit.branches 107161574 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions. system.cpu.commit.function_calls 1061692 # Number of function calls committed. -system.cpu.commit.bw_lim_events 32625832 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 32640170 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3082294657 # The number of ROB reads -system.cpu.rob.rob_writes 3995391584 # The number of ROB writes -system.cpu.timesIdled 60284 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 369627 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3082443517 # The number of ROB reads +system.cpu.rob.rob_writes 3994969913 # The number of ROB writes +system.cpu.timesIdled 60378 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 378551 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 880025277 # Number of Instructions Simulated system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated -system.cpu.cpi 1.368898 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.368898 # CPI: Total CPI of All Threads -system.cpu.ipc 0.730515 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.730515 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3534938952 # number of integer regfile reads -system.cpu.int_regfile_writes 1966276795 # number of integer regfile writes -system.cpu.fp_regfile_reads 92 # number of floating regfile reads -system.cpu.misc_regfile_reads 906122047 # number of misc regfile reads +system.cpu.cpi 1.369323 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.369323 # CPI: Total CPI of All Threads +system.cpu.ipc 0.730288 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.730288 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3534639638 # number of integer regfile reads +system.cpu.int_regfile_writes 1966129317 # number of integer regfile writes +system.cpu.fp_regfile_reads 116 # number of floating regfile reads +system.cpu.misc_regfile_reads 905981948 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 34 # number of replacements -system.cpu.icache.tagsinuse 799.517991 # Cycle average of tags in use -system.cpu.icache.total_refs 184596362 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 200866.552775 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 93457946 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 204658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 204658 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 428893 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246296 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246296 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1854 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1328951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1330805 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56250752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 56309952 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 56309952 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 868818500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1393500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 675040498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.icache.replacements 41 # number of replacements +system.cpu.icache.tagsinuse 797.090296 # Cycle average of tags in use +system.cpu.icache.total_refs 184711350 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 199687.945946 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 799.517991 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.390390 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.390390 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 184596362 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 184596362 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 184596362 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 184596362 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 184596362 # number of overall hits -system.cpu.icache.overall_hits::total 184596362 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1352 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1352 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1352 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1352 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1352 # number of overall misses -system.cpu.icache.overall_misses::total 1352 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 65001000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 65001000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 65001000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 65001000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 65001000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 65001000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 184597714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 184597714 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 184597714 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 184597714 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 184597714 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 184597714 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48077.662722 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48077.662722 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48077.662722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48077.662722 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 797.090296 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.389204 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.389204 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 184711350 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 184711350 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 184711350 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 184711350 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 184711350 # number of overall hits +system.cpu.icache.overall_hits::total 184711350 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1427 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1427 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1427 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1427 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1427 # number of overall misses +system.cpu.icache.overall_misses::total 1427 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 89875000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 89875000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 89875000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 89875000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 89875000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 89875000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 184712777 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 184712777 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 184712777 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 184712777 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 184712777 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 184712777 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000008 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000008 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000008 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000008 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000008 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000008 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62981.779958 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62981.779958 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62981.779958 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62981.779958 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62981.779958 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62981.779958 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 295 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.250000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 73.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47826000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 47826000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47826000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 47826000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47826000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 47826000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 498 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 498 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 498 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 498 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 498 # 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Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 999.884735 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 960887000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4092.296880 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999096 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999096 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 262033427 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 262033427 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 187939697 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 187939697 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 449973124 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 449973124 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 449973124 # number of overall hits +system.cpu.dcache.overall_hits::total 449973124 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 211198 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 211198 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 246361 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 246361 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 457559 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 457559 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 457559 # number of overall misses +system.cpu.dcache.overall_misses::total 457559 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3104170500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3104170500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4487459000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4487459000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7591629500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7591629500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7591629500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7591629500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 262244625 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 262244625 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 450577836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 450577836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 450577836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 450577836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 450430683 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 450430683 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 450430683 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 450430683 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000805 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000805 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.001016 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.001016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.001016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.001016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14304.482843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14304.482843 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16702.214741 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 16702.214741 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 15594.973785 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15594.973785 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14697.916173 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14697.916173 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18214.973149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 18214.973149 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 16591.586003 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 16591.586003 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.586003 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16591.586003 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.953488 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.702703 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 429005 # number of writebacks -system.cpu.dcache.writebacks::total 429005 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7496 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7496 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 71 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 71 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7567 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7567 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7567 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7567 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203910 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 203910 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246323 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 246323 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 450233 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 450233 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 450233 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 450233 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2529393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2529393000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3622096999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3622096999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6151489999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6151489999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6151489999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6151489999 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 428893 # number of writebacks +system.cpu.dcache.writebacks::total 428893 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7460 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7460 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 70 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 70 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7530 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7530 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7530 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7530 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203738 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 203738 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246291 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 246291 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 450029 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 450029 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 450029 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 450029 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2608561002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2608561002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3994205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3994205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6602766502 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6602766502 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6602766502 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6602766502 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000777 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000777 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses @@ -768,14 +879,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000999 system.cpu.dcache.demand_mshr_miss_rate::total 0.000999 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000999 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12404.457849 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12404.457849 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14704.664197 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14704.664197 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12803.507456 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12803.507456 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16217.423698 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16217.423698 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt index 8d09ee016..1af1a34f9 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 896740221 # Wr system.physmem.bw_total::cpu.inst 9846686428 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2808012957 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12654699384 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 12654699384 # Throughput (bytes/s) +system.membus.data_through_bus 12199037473 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 1927985345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt index 441f669b6..f21ff386d 100644 --- a/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt @@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 89270 # To system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1049487 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 5039 # Transaction distribution +system.membus.trans_dist::ReadResp 5039 # Transaction distribution +system.membus.trans_dist::Writeback 2511 # Transaction distribution +system.membus.trans_dist::ReadExReq 21970 # Transaction distribution +system.membus.trans_dist::ReadExResp 21970 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 56529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 56529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 56529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 56529 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1889280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1889280 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1889280 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 49608000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 243081000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.numCycles 3600386796 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -370,5 +390,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 30778915 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 198048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 198048 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 422980 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 244722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 244722 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1444 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1307076 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 1308520 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55361792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 55408000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 55408000 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 855855000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1083000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 663072000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index b4108b98d..9627a30de 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.026781 # Number of seconds simulated -sim_ticks 26780899500 # Number of ticks simulated -final_tick 26780899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026877 # Number of seconds simulated +sim_ticks 26876770500 # Number of ticks simulated +final_tick 26876770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55932 # Simulator instruction rate (inst/s) -host_op_rate 56334 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16535050 # Simulator tick rate (ticks/s) -host_mem_usage 421208 # Number of bytes of host memory used -host_seconds 1619.64 # Real time elapsed on the host +host_inst_rate 124105 # Simulator instruction rate (inst/s) +host_op_rate 124996 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36820237 # Simulator tick rate (ticks/s) +host_mem_usage 379416 # Number of bytes of host memory used +host_seconds 729.95 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory -system.physmem.bytes_read::total 992640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 992448 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1680003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35385219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37065223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1680003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1680003 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1680003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35385219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 37065223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15510 # Total number of read requests seen +system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1666867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35258998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36925865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1666867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1666867 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1666867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35258998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 36925865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15507 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 15513 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 992640 # Total number of bytes read from memory +system.physmem.cpureqs 15509 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 992448 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 992640 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 992448 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 998 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 999 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1078 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 957 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 876 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 896 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 26780729500 # Total gap between requests +system.physmem.totGap 26876578500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 15510 # Categorize read packet sizes +system.physmem.readPktSize::6 15507 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,13 +85,13 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 10153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5074 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 11266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -149,36 +149,90 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 54693250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 313977000 # Sum of mem lat for all requests -system.physmem.totBusLat 77550000 # Total cycles spent in databus access -system.physmem.totBankLat 181733750 # Total cycles spent in bank access -system.physmem.avgQLat 3526.32 # Average queueing delay per request -system.physmem.avgBankLat 11717.20 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3465.175627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 823.608896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3831.300006 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 21 7.53% 31.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 17 6.09% 37.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 11 3.94% 41.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 11 3.94% 45.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 5 1.79% 47.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1 0.36% 48.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 3 1.08% 49.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 4 1.43% 52.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1 0.36% 53.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1 0.36% 53.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1 0.36% 53.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 2 0.72% 54.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.36% 54.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 1 0.36% 55.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.72% 55.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.36% 56.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.36% 56.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.36% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation +system.physmem.totQLat 33774250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 291406750 # Sum of mem lat for all requests +system.physmem.totBusLat 77535000 # Total cycles spent in databus access +system.physmem.totBankLat 180097500 # Total cycles spent in bank access +system.physmem.avgQLat 2178.00 # Average queueing delay per request +system.physmem.avgBankLat 11613.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20243.52 # Average memory access latency -system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 18791.95 # Average memory access latency +system.physmem.avgRdBW 36.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 36.93 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.29 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 14776 # Number of row buffer hits during reads +system.physmem.readRowHits 15228 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 1726675.02 # Average gap between requests -system.cpu.branchPred.lookups 26686067 # Number of BP lookups -system.cpu.branchPred.condPredicted 22003641 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 842721 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11370784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11281397 # Number of BTB hits +system.physmem.avgGap 1733190.08 # Average gap between requests +system.membus.throughput 36925865 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 969 # Transaction distribution +system.membus.trans_dist::ReadResp 969 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 14538 # Transaction distribution +system.membus.trans_dist::ReadExResp 14538 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 31018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 31018 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 992448 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 992448 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 19245500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 145771998 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu.branchPred.lookups 26679971 # Number of BP lookups +system.cpu.branchPred.condPredicted 21999923 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 841486 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11361779 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11280277 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.213889 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 70454 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.282665 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 69760 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 186 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -222,239 +276,239 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 53561800 # number of cpu cycles simulated +system.cpu.numCycles 53753542 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14175164 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 127899633 # Number of instructions fetch has processed -system.cpu.fetch.Branches 26686067 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11351851 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24037657 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4765030 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11217249 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 14168054 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127857393 # Number of instructions fetch has processed +system.cpu.fetch.Branches 26679971 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11350037 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24029267 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4759146 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 11320906 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13847383 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 331199 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 53336140 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.414591 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.216158 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13839868 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 53419540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.409911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.214764 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 29336778 55.00% 55.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3388806 6.35% 61.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2028790 3.80% 65.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1556293 2.92% 68.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1665637 3.12% 71.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2919109 5.47% 76.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1511505 2.83% 79.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1091219 2.05% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9838003 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 29428601 55.09% 55.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3388763 6.34% 61.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2027589 3.80% 65.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1554197 2.91% 68.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1665441 3.12% 71.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2919869 5.47% 76.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1510771 2.83% 79.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1090381 2.04% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9833928 18.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 53336140 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.498229 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.387889 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16937190 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9066542 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22437695 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 997386 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3897327 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4443416 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 8715 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 126080182 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42547 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3897327 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18717098 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3539811 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 156330 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21553550 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5472024 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 123163469 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 421860 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4589739 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1294 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 143620029 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 536487458 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 536482847 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4611 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 53419540 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.496339 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.378585 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16932063 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9167037 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22428085 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 999775 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3892580 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4442872 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8651 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 126035469 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42652 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3892580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18713289 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3601391 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 176810 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21544043 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5491427 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 123129214 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 413620 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4613636 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1365 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 143579054 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 536328979 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 536324233 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4746 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36205843 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12496499 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29481175 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5524207 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2105622 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1304065 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 118177785 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105170475 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 79267 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26750487 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65594281 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 53336140 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.971843 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.910853 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 36164868 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4608 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4606 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12537284 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29472276 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5518407 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2148723 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1268677 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 118148285 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105144607 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 78560 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26719178 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65548353 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 53419540 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.968280 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.909780 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15308492 28.70% 28.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 11622242 21.79% 50.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8283131 15.53% 66.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6774123 12.70% 78.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4939733 9.26% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2964995 5.56% 93.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2471425 4.63% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 528847 0.99% 99.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 443152 0.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 15372134 28.78% 28.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 11649287 21.81% 50.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8266991 15.48% 66.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6802353 12.73% 78.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4948394 9.26% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2939644 5.50% 93.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2464571 4.61% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 534271 1.00% 99.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 441895 0.83% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 53336140 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 53419540 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45613 6.89% 6.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 340087 51.41% 58.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 275830 41.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45832 6.94% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 339714 51.41% 58.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 275235 41.65% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74428958 70.77% 70.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 145 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 185 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25611753 24.35% 95.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5118456 4.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74415665 70.77% 70.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 126 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 171 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25604813 24.35% 95.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5112854 4.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105170475 # Type of FU issued -system.cpu.iq.rate 1.963535 # Inst issue rate -system.cpu.iq.fu_busy_cnt 661557 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 264417181 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 144941243 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102695992 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 733 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1017 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 321 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 105831667 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 444874 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105144607 # Type of FU issued +system.cpu.iq.rate 1.956050 # Inst issue rate +system.cpu.iq.fu_busy_cnt 660808 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006285 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 264447444 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 144880593 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102675373 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 678 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 959 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 105805083 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 332 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 440146 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6907209 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6633 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6354 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 779363 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6898310 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6801 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6412 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 773563 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 31305 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 31426 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3897327 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 927642 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 126590 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 118198971 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 309734 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29481175 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5524207 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4584 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 66006 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6795 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6354 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 446949 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445983 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892932 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104193042 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25290857 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 977433 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3892580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 959936 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 127408 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 118169460 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 310371 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29472276 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5518407 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 66175 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 6842 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6412 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 445895 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 445553 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 891448 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104166950 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25284184 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 977657 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12714 # number of nop insts executed -system.cpu.iew.exec_refs 30352506 # number of memory reference insts executed -system.cpu.iew.exec_branches 21328586 # Number of branches executed -system.cpu.iew.exec_stores 5061649 # Number of stores executed -system.cpu.iew.exec_rate 1.945286 # Inst execution rate -system.cpu.iew.wb_sent 102976105 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102696313 # cumulative count of insts written-back -system.cpu.iew.wb_producers 62237913 # num instructions producing a value -system.cpu.iew.wb_consumers 104299650 # num instructions consuming a value +system.cpu.iew.exec_nop 12698 # number of nop insts executed +system.cpu.iew.exec_refs 30340262 # number of memory reference insts executed +system.cpu.iew.exec_branches 21325081 # Number of branches executed +system.cpu.iew.exec_stores 5056078 # Number of stores executed +system.cpu.iew.exec_rate 1.937862 # Inst execution rate +system.cpu.iew.wb_sent 102951696 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102675661 # cumulative count of insts written-back +system.cpu.iew.wb_producers 62239721 # num instructions producing a value +system.cpu.iew.wb_consumers 104280591 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.917342 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.596722 # average fanout of values written-back +system.cpu.iew.wb_rate 1.910119 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.596849 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 26949111 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 26919455 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 834092 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 49438813 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.845776 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.541803 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 832928 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 49526960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.842491 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.540649 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19950290 40.35% 40.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13144948 26.59% 66.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4163783 8.42% 75.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3432949 6.94% 82.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1533470 3.10% 85.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 746046 1.51% 86.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 934782 1.89% 88.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 251563 0.51% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5280982 10.68% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20031869 40.45% 40.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13152738 26.56% 67.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4167621 8.41% 75.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3431174 6.93% 82.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1533592 3.10% 85.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 731516 1.48% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 947722 1.91% 88.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 252646 0.51% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5278082 10.66% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 49438813 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 49526960 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -465,200 +519,222 @@ system.cpu.commit.branches 18732304 # Nu system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72525674 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5280982 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5278082 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 162354168 # The number of ROB reads -system.cpu.rob.rob_writes 240321058 # The number of ROB writes -system.cpu.timesIdled 43778 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 225660 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 162415559 # The number of ROB reads +system.cpu.rob.rob_writes 240257118 # The number of ROB writes +system.cpu.timesIdled 46037 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 334002 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated -system.cpu.cpi 0.591256 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.591256 # CPI: Total CPI of All Threads -system.cpu.ipc 1.691314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.691314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 495624515 # number of integer regfile reads -system.cpu.int_regfile_writes 120561799 # number of integer regfile writes -system.cpu.fp_regfile_reads 167 # number of floating regfile reads -system.cpu.fp_regfile_writes 408 # number of floating regfile writes -system.cpu.misc_regfile_reads 29097050 # number of misc regfile reads +system.cpu.cpi 0.593373 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.593373 # CPI: Total CPI of All Threads +system.cpu.ipc 1.685281 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.685281 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 495496517 # number of integer regfile reads +system.cpu.int_regfile_writes 120533542 # number of integer regfile writes +system.cpu.fp_regfile_reads 149 # number of floating regfile reads +system.cpu.fp_regfile_writes 362 # number of floating regfile writes +system.cpu.misc_regfile_reads 29086571 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 630.487158 # Cycle average of tags in use -system.cpu.icache.total_refs 13846398 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 729 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18993.687243 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 4503595847 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 904588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 904588 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942920 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 43775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 43775 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1457 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 2839649 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120995392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 121041920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 121041920 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1888563000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1095499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1421456489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%) +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 627.794494 # Cycle average of tags in use +system.cpu.icache.total_refs 13838883 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 727 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19035.602476 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 630.487158 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.307855 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.307855 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13846398 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13846398 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13846398 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13846398 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13846398 # number of overall hits -system.cpu.icache.overall_hits::total 13846398 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 627.794494 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306540 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306540 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 13838883 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13838883 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13838883 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13838883 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13838883 # number of overall hits +system.cpu.icache.overall_hits::total 13838883 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 984 # number of overall misses system.cpu.icache.overall_misses::total 984 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 49101999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 49101999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 49101999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 49101999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 49101999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 49101999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13847382 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13847382 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13847382 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13847382 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13847382 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13847382 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 66043999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 66043999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 66043999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 66043999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 66043999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 66043999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13839867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13839867 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13839867 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13839867 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13839867 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13839867 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49900.405488 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49900.405488 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49900.405488 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49900.405488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49900.405488 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49900.405488 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67117.885163 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 67117.885163 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 67117.885163 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 67117.885163 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.300000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 251 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 251 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 251 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 733 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 733 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 733 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 733 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 733 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37481499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37481499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37481499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37481499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37481499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37481499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 254 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 254 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 254 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 254 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44069.798507 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40489.713697 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 15507 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40240750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15233500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55474250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 20002 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 714861250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 714861250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40240750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 730094750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 770335500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40240750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 730094750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 770335500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.666667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.666667 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.332107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.332107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016351 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962861 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016351 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57486.785714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56630.111524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57248.968008 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 30800.878258 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 30800.878258 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39124.901849 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31041.039711 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31407.445583 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39124.901849 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31041.039711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31407.445583 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49171.911542 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49171.911542 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57486.785714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49307.405281 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49676.629909 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943501 # number of replacements -system.cpu.dcache.tagsinuse 3674.828518 # Cycle average of tags in use -system.cpu.dcache.total_refs 28143712 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947597 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.700086 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7938430000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3674.828518 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.897175 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.897175 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23598974 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23598974 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4536932 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4536932 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3909 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3909 # number of LoadLockedReq hits +system.cpu.dcache.replacements 943537 # number of replacements +system.cpu.dcache.tagsinuse 3672.136580 # Cycle average of tags in use +system.cpu.dcache.total_refs 28138091 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 947633 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 29.693026 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7986158000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 3672.136580 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.896518 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.896518 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 23597541 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23597541 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4532751 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4532751 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3906 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3906 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28135906 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28135906 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28135906 # number of overall hits -system.cpu.dcache.overall_hits::total 28135906 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1174144 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1174144 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 198049 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 198049 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 6 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 6 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1372193 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1372193 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1372193 # number of overall misses -system.cpu.dcache.overall_misses::total 1372193 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13880291500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13880291500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5594114381 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5594114381 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 247000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 247000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19474405881 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19474405881 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19474405881 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19474405881 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24773118 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24773118 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 28130292 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28130292 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28130292 # number of overall hits +system.cpu.dcache.overall_hits::total 28130292 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1173737 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1173737 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 202230 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 202230 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 7 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 7 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1375967 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1375967 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1375967 # number of overall misses +system.cpu.dcache.overall_misses::total 1375967 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13887682000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13887682000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7842358356 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7842358356 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 236000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 236000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21730040356 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21730040356 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21730040356 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21730040356 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24771278 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24771278 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3915 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3915 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3913 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3913 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29508099 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29508099 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29508099 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29508099 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047396 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.047396 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041827 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041827 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001533 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001533 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.046502 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.046502 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.046502 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.046502 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11821.626223 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11821.626223 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28246.112735 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28246.112735 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 41166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 41166.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14192.176961 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14192.176961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14192.176961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14192.176961 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 152397 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 29506259 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29506259 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29506259 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29506259 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.047383 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.047383 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.042710 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.042710 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001789 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.046633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.046633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.046633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.046633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11832.021995 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11832.021995 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38779.401454 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38779.401454 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 33714.285714 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 33714.285714 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15792.559237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15792.559237 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15792.559237 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 153985 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23857 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 23865 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.387936 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.452336 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942899 # number of writebacks -system.cpu.dcache.writebacks::total 942899 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 270103 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 270103 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154489 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 424592 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 424592 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 424592 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 424592 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 904041 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 904041 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43560 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43560 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947601 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947601 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947601 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947601 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9990058500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9990058500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 983302939 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 983302939 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10973361439 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10973361439 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10973361439 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10973361439 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036493 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036493 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009200 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009200 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032113 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032113 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032113 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032113 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11050.448486 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11050.448486 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22573.529362 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22573.529362 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11580.149703 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11580.149703 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11580.149703 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11580.149703 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 942920 # number of writebacks +system.cpu.dcache.writebacks::total 942920 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 269859 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 269859 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158472 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158472 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 428331 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 428331 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 428331 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 428331 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903878 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903878 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43758 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43758 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947636 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947636 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947636 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947636 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9991782011 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9991782011 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1252450464 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1252450464 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11244232475 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11244232475 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11244232475 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11244232475 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036489 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009241 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.348055 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.348055 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28622.205402 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28622.205402 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index a3d57c71f..397354d07 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240661000 # Number of ticks simulated final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1585065 # Simulator instruction rate (inst/s) -host_op_rate 1596445 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 948925064 # Simulator tick rate (ticks/s) -host_mem_usage 411788 # Number of bytes of host memory used -host_seconds 57.16 # Real time elapsed on the host +host_inst_rate 2267620 # Simulator instruction rate (inst/s) +host_op_rate 2283902 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1357548360 # Simulator tick rate (ticks/s) +host_mem_usage 366572 # Number of bytes of host memory used +host_seconds 39.95 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91252960 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 348597116 # Wr system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9960199711 # Throughput (bytes/s) +system.membus.data_through_bus 540247816 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 866d0f0d0..bffef2d47 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147136 # Nu sim_ticks 147135976000 # Number of ticks simulated final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 836188 # Simulator instruction rate (inst/s) -host_op_rate 842183 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1358330065 # Simulator tick rate (ticks/s) -host_mem_usage 420368 # Number of bytes of host memory used -host_seconds 108.32 # Real time elapsed on the host +host_inst_rate 662214 # Simulator instruction rate (inst/s) +host_op_rate 666963 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1075722156 # Simulator tick rate (ticks/s) +host_mem_usage 375060 # Number of bytes of host memory used +host_seconds 136.78 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 251414 # In system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 6672467 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 792 # Transaction distribution +system.membus.trans_dist::ReadResp 792 # Transaction distribution +system.membus.trans_dist::ReadExReq 14548 # Transaction distribution +system.membus.trans_dist::ReadExResp 14548 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 30680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 30680 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 981760 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 981760 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -414,5 +429,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 821979690 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1198 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2835930 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 2837128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 38336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120904448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 120942784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index e67672782..9196a1276 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.122216 # Nu sim_ticks 122215823500 # Number of ticks simulated final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2097981 # Simulator instruction rate (inst/s) -host_op_rate 2098068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1051599524 # Simulator tick rate (ticks/s) -host_mem_usage 405208 # Number of bytes of host memory used -host_seconds 116.22 # Real time elapsed on the host +host_inst_rate 2226348 # Simulator instruction rate (inst/s) +host_op_rate 2226440 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1115942635 # Simulator tick rate (ticks/s) +host_mem_usage 357000 # Number of bytes of host memory used +host_seconds 109.52 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory @@ -35,6 +35,9 @@ system.physmem.bw_write::total 749543606 # Wr system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11438757576 # Throughput (bytes/s) +system.membus.data_through_bus 1397997177 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 244431648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 40a365e11..b41c1d4fe 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1027753 # Simulator instruction rate (inst/s) -host_op_rate 1027796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1523718944 # Simulator tick rate (ticks/s) -host_mem_usage 413792 # Number of bytes of host memory used -host_seconds 237.24 # Real time elapsed on the host +host_inst_rate 653861 # Simulator instruction rate (inst/s) +host_op_rate 653888 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 969395755 # Simulator tick rate (ticks/s) +host_mem_usage 365508 # Number of bytes of host memory used +host_seconds 372.90 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 155623 # In system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 2762444 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1036 # Transaction distribution +system.membus.trans_dist::ReadResp 1036 # Transaction distribution +system.membus.trans_dist::ReadExReq 14567 # Transaction distribution +system.membus.trans_dist::ReadExResp 14567 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 31206 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 998592 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 722977060 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -384,5 +399,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2814408 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 2816172 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 56448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119989568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 120046016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 5ca506819..a8ad328fe 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.064955 # Number of seconds simulated -sim_ticks 64955437500 # Number of ticks simulated -final_tick 64955437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065490 # Number of seconds simulated +sim_ticks 65489948000 # Number of ticks simulated +final_tick 65489948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70718 # Simulator instruction rate (inst/s) -host_op_rate 124523 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29075113 # Simulator tick rate (ticks/s) -host_mem_usage 434544 # Number of bytes of host memory used -host_seconds 2234.06 # Real time elapsed on the host +host_inst_rate 99083 # Simulator instruction rate (inst/s) +host_op_rate 174470 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41072394 # Simulator tick rate (ticks/s) +host_mem_usage 386708 # Number of bytes of host memory used +host_seconds 1594.50 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 64064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory -system.physmem.bytes_read::total 1946560 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory -system.physmem.bytes_written::total 10432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1001 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30415 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 163 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 986276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28981346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29967622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 986276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 986276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 160602 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 160602 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 160602 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 986276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28981346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30128224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1882624 # Number of bytes read from this memory +system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10112 # Number of bytes written to this memory +system.physmem.bytes_written::total 10112 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29416 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 158 # Number of write requests responded to by this memory +system.physmem.num_writes::total 158 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 975295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28746763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29722057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 154405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 154405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 154405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28746763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 29876463 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 30415 # Total number of read requests seen -system.physmem.writeReqs 163 # Total number of write requests seen -system.physmem.cpureqs 30578 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1946560 # Total number of bytes read from memory -system.physmem.bytesWritten 10432 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 1946560 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 40 # Number of read reqs serviced by write Q +system.physmem.writeReqs 158 # Total number of write requests seen +system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1946496 # Total number of bytes read from memory +system.physmem.bytesWritten 10112 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 10112 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 47 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 1903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 1919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 1935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 1899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 1949 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 1933 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 1946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 1848 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 1827 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 63 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 11 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 1925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 2026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 1927 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 1901 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 1864 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 1931 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 1821 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 12 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 8 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 64955401000 # Total gap between requests +system.physmem.totGap 65489931000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -91,12 +91,12 @@ system.physmem.writePktSize::2 0 # Ca system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 163 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 29875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 158 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 29911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,8 +124,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see @@ -144,9 +144,9 @@ system.physmem.wrQLenPdf::16 7 # Wh system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see @@ -156,126 +156,194 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 11278750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 610070000 # Sum of mem lat for all requests -system.physmem.totBusLat 151875000 # Total cycles spent in databus access -system.physmem.totBankLat 446916250 # Total cycles spent in bank access -system.physmem.avgQLat 371.32 # Average queueing delay per request -system.physmem.avgBankLat 14713.29 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 551 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 3522.090744 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 829.782913 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 3844.695710 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 143 25.95% 25.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 46 8.35% 34.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 23 4.17% 38.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 15 2.72% 41.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 11 2.00% 43.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10 1.81% 45.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 9 1.63% 46.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 5 0.91% 47.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 5 0.91% 48.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 10 1.81% 50.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.73% 51.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 1.09% 52.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 2 0.36% 52.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1 0.18% 52.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.54% 53.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1 0.18% 53.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 1 0.18% 55.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.54% 56.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.36% 56.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.18% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.18% 57.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.36% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.18% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.18% 58.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.18% 58.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.18% 58.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.36% 59.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 1 0.18% 59.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.18% 59.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.18% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 216 39.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 551 # Bytes accessed per row activation +system.physmem.totQLat 7172750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 582609000 # Sum of mem lat for all requests +system.physmem.totBusLat 151840000 # Total cycles spent in databus access +system.physmem.totBankLat 423596250 # Total cycles spent in bank access +system.physmem.avgQLat 236.19 # Average queueing delay per request +system.physmem.avgBankLat 13948.77 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20084.61 # Average memory access latency -system.physmem.avgRdBW 29.97 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 29.97 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 19184.96 # Average memory access latency +system.physmem.avgRdBW 29.72 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 29.72 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.24 # Data bus utilization in percentage +system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.avgRdQLen 0.01 # Average read queue length over time -system.physmem.avgWrQLen 9.38 # Average write queue length over time -system.physmem.readRowHits 29086 # Number of row buffer hits during reads -system.physmem.writeRowHits 90 # Number of row buffer hits during writes -system.physmem.readRowHitRate 95.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 55.21 # Row buffer hit rate for writes -system.physmem.avgGap 2124252.76 # Average gap between requests -system.cpu.branchPred.lookups 33861369 # Number of BP lookups -system.cpu.branchPred.condPredicted 33861369 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 775033 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 19294803 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19205281 # Number of BTB hits +system.physmem.avgWrQLen 0.64 # Average write queue length over time +system.physmem.readRowHits 29867 # Number of row buffer hits during reads +system.physmem.writeRowHits 88 # Number of row buffer hits during writes +system.physmem.readRowHitRate 98.35 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 55.70 # Row buffer hit rate for writes +system.physmem.avgGap 2142083.90 # Average gap between requests +system.membus.throughput 29875486 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1414 # Transaction distribution +system.membus.trans_dist::ReadResp 1412 # Transaction distribution +system.membus.trans_dist::Writeback 158 # Transaction distribution +system.membus.trans_dist::ReadExReq 29001 # Transaction distribution +system.membus.trans_dist::ReadExResp 29001 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 60986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60986 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1956544 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1956544 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 34719000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 283984750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu.branchPred.lookups 33857873 # Number of BP lookups +system.cpu.branchPred.condPredicted 33857873 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 774323 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19304335 # Number of BTB lookups +system.cpu.branchPred.BTBHits 19204317 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.536031 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5016068 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5449 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.481888 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5017100 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5401 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 129910880 # number of cpu cycles simulated +system.cpu.numCycles 130979906 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 26135643 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 182272269 # Number of instructions fetch has processed -system.cpu.fetch.Branches 33861369 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24221349 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 55463274 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5355481 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 43685508 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 275 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 25577909 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 166501 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 129829944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.475075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.321063 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 26132901 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 182254705 # Number of instructions fetch has processed +system.cpu.fetch.Branches 33857873 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24221417 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 55457387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5351238 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 44744671 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 388 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 25573947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 166608 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 130876974 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.455077 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.315032 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76844002 59.19% 59.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1961117 1.51% 60.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2942078 2.27% 62.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3835155 2.95% 65.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7767567 5.98% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4757667 3.66% 75.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2666355 2.05% 77.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1316617 1.01% 78.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 27739386 21.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 77895599 59.52% 59.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1961064 1.50% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2941506 2.25% 63.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3833280 2.93% 66.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7768261 5.94% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4757709 3.64% 75.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2666396 2.04% 77.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1316117 1.01% 78.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27737042 21.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 129829944 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260651 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.403056 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36820018 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 35912600 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 43886713 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8665410 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4545203 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 318850210 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 4545203 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42299380 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8565943 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6540 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 46769687 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27643191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 315014600 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 177 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 37506 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 25780031 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 461 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 317193496 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 836529852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 836528510 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1342 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 130876974 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258497 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.391471 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36825046 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 36962033 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 43884335 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8664000 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4541560 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 318828995 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 4541560 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 42312169 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 9511401 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7346 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 46756594 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 27747904 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 314994654 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26642 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 25895040 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 476 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 317170346 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 836475154 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 836474392 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 762 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37980749 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 37957599 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 473 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 470 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62475342 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 101554999 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 34779465 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 39658435 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5856370 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 311474506 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1648 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 300268759 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 90582 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32704656 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 46105854 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1203 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 129829944 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.312785 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.693578 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 471 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 62618763 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 101546098 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 34776490 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 39628981 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5872628 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 311460641 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1620 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 300263242 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 89194 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32692736 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 46075932 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1175 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 130876974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.294240 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.698248 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23157142 17.84% 17.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23146978 17.83% 35.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25463277 19.61% 55.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 25807307 19.88% 75.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 18888431 14.55% 89.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8277018 6.38% 96.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 3970528 3.06% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 942780 0.73% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 176483 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24131864 18.44% 18.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23200747 17.73% 36.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25515846 19.50% 55.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 25800196 19.71% 75.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18908821 14.45% 89.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8226578 6.29% 96.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 3966533 3.03% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 948269 0.72% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 178120 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 129829944 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 130876974 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 31372 1.52% 1.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 31350 1.52% 1.52% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available @@ -304,118 +372,118 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.52% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1915002 93.02% 94.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 112311 5.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1914118 93.02% 94.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 112203 5.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 169830588 56.56% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11175 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 333 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 97304104 32.41% 88.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 33091251 11.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 31269 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 169831463 56.56% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11173 0.00% 56.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 97296683 32.40% 88.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 33092294 11.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 300268759 # Type of FU issued -system.cpu.iq.rate 2.311344 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2058685 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 732516269 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344212556 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 298017233 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 646 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 145 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302295951 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 216 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 54147980 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 300263242 # Type of FU issued +system.cpu.iq.rate 2.292437 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2057671 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006853 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 733550061 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 344187115 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 298012847 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 328 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 302289511 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 54160833 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 10775614 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 30228 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 33222 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3339713 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10766713 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 30678 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 33261 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3336738 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3234 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8606 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3210 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 8599 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4545203 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1761176 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 160180 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 311476154 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 195955 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 101554999 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 34779465 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3219 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 73682 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33222 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 393210 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 428039 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 821249 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 298868187 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 96891593 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1400572 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4541560 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2575832 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 162156 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 311462261 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 197211 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 101546098 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 34776490 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 463 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2580 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 73528 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 33261 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 393064 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 427262 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 820326 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 298861022 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 96886540 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1402220 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 129818447 # number of memory reference insts executed -system.cpu.iew.exec_branches 30819793 # Number of branches executed -system.cpu.iew.exec_stores 32926854 # Number of stores executed -system.cpu.iew.exec_rate 2.300563 # Inst execution rate -system.cpu.iew.wb_sent 298386144 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 298017378 # cumulative count of insts written-back -system.cpu.iew.wb_producers 218312526 # num instructions producing a value -system.cpu.iew.wb_consumers 296857185 # num instructions consuming a value +system.cpu.iew.exec_refs 129814002 # number of memory reference insts executed +system.cpu.iew.exec_branches 30818579 # Number of branches executed +system.cpu.iew.exec_stores 32927462 # Number of stores executed +system.cpu.iew.exec_rate 2.281732 # Inst execution rate +system.cpu.iew.wb_sent 298381528 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 298012951 # cumulative count of insts written-back +system.cpu.iew.wb_producers 218258094 # num instructions producing a value +system.cpu.iew.wb_consumers 296763752 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.294014 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.735413 # average fanout of values written-back +system.cpu.iew.wb_rate 2.275257 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.735461 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 33296720 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 33282582 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 775062 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 125284741 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.220482 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.978635 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 774373 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 126335414 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.202015 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.972310 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57056182 45.54% 45.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 19092863 15.24% 60.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11627505 9.28% 70.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9458661 7.55% 77.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1851635 1.48% 79.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2083324 1.66% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1287468 1.03% 81.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 696184 0.56% 82.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22130919 17.66% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 58023185 45.93% 45.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 19157211 15.16% 61.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11690918 9.25% 70.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9453779 7.48% 77.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1822705 1.44% 79.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2075367 1.64% 80.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1288633 1.02% 81.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 696301 0.55% 82.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22127315 17.51% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 125284741 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 126335414 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -426,192 +494,212 @@ system.cpu.commit.branches 29309705 # Nu system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.int_insts 278186174 # Number of committed integer instructions. system.cpu.commit.function_calls 4237596 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22130919 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22127315 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 414643006 # The number of ROB reads -system.cpu.rob.rob_writes 627527392 # The number of ROB writes -system.cpu.timesIdled 13814 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 80936 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 415683145 # The number of ROB reads +system.cpu.rob.rob_writes 627495486 # The number of ROB writes +system.cpu.timesIdled 13953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 102932 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated -system.cpu.cpi 0.822280 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.822280 # CPI: Total CPI of All Threads -system.cpu.ipc 1.216130 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.216130 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 590791400 # number of integer regfile reads -system.cpu.int_regfile_writes 298595306 # number of integer regfile writes -system.cpu.fp_regfile_reads 134 # number of floating regfile reads -system.cpu.fp_regfile_writes 70 # number of floating regfile writes -system.cpu.misc_regfile_reads 191828831 # number of misc regfile reads +system.cpu.cpi 0.829047 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.829047 # CPI: Total CPI of All Threads +system.cpu.ipc 1.206204 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.206204 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 590786274 # number of integer regfile reads +system.cpu.int_regfile_writes 298589380 # number of integer regfile writes +system.cpu.fp_regfile_reads 94 # number of floating regfile reads +system.cpu.fp_regfile_writes 64 # number of floating regfile writes +system.cpu.misc_regfile_reads 191820132 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 61 # number of replacements -system.cpu.icache.tagsinuse 820.655975 # Cycle average of tags in use -system.cpu.icache.total_refs 25576619 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1018 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 25124.380157 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 4049838977 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1995271 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995269 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066544 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82308 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2026 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6219674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 6221700 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 64832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 265158912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 265223744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 265223744 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4138605500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1519500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3114846499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 4.8 # Layer utilization (%) +system.cpu.icache.replacements 52 # number of replacements +system.cpu.icache.tagsinuse 824.208577 # Cycle average of tags in use +system.cpu.icache.total_refs 25572646 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1013 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 25244.467917 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 820.655975 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.400711 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.400711 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 25576619 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25576619 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25576619 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25576619 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25576619 # number of overall hits -system.cpu.icache.overall_hits::total 25576619 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1290 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1290 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1290 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1290 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1290 # number of overall misses -system.cpu.icache.overall_misses::total 1290 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64574500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64574500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64574500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64574500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64574500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64574500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25577909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25577909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25577909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25577909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25577909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25577909 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50057.751938 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50057.751938 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50057.751938 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50057.751938 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50057.751938 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50057.751938 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 35 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 824.208577 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.402446 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.402446 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 25572646 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25572646 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25572646 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25572646 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25572646 # number of overall hits +system.cpu.icache.overall_hits::total 25572646 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1301 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1301 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1301 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1301 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1301 # number of overall misses +system.cpu.icache.overall_misses::total 1301 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 86424000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 86424000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 86424000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 86424000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 86424000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 86424000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25573947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25573947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25573947 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25573947 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25573947 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25573947 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000051 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000051 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000051 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000051 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000051 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000051 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66428.900846 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66428.900846 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66428.900846 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66428.900846 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66428.900846 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 115 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 272 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 272 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 272 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 272 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 272 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 272 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1496078750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000209 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352318 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352318 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014165 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014639 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983301 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014165 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 29808.443904 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30105.938682 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.352347 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.352347 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014166 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014640 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985192 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014166 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014640 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55359.218437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56069.711538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55568.246110 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 48877.805938 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 48877.805938 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55359.218437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48979.510147 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49188.845964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55359.218437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48979.510147 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49188.845964 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2072485 # number of replacements -system.cpu.dcache.tagsinuse 4072.522671 # Cycle average of tags in use -system.cpu.dcache.total_refs 71414123 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2076581 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.390242 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 20537505000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.522671 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994268 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994268 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 40072419 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40072419 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31341704 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31341704 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71414123 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71414123 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71414123 # number of overall hits -system.cpu.dcache.overall_hits::total 71414123 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2626925 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2626925 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 98048 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 98048 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2724973 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2724973 # 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number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74139096 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74139096 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74139096 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74139096 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061521 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061521 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 74121368 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74121368 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74121368 # 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average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21486.715649 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12274.733363 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12274.733363 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32679 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.036748 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036748 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036748 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036748 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11952.353160 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11952.353160 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.080504 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.080504 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12500.087010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12500.087010 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32905 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9507 # 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number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 647246 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 647246 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994377 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994377 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82189 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82189 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076566 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076566 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076566 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076566 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994900501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994900501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2389827998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2389827998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24384728499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24384728499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24384728499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24384728499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046727 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046727 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028016 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028016 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.456757 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.456757 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29077.224422 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29077.224422 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 19252022f..fcf1f6acc 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1439319677 # Wr system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 15992825110 # Throughput (bytes/s) +system.membus.data_through_bus 2701988442 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 337900081 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index f8e97e7f1..c0ade68d4 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 17487 # To system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 5272114 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1025 # Transaction distribution +system.membus.trans_dist::ReadResp 1025 # Transaction distribution +system.membus.trans_dist::Writeback 100 # Transaction distribution +system.membus.trans_dist::ReadExReq 29024 # Transaction distribution +system.membus.trans_dist::ReadExResp 29024 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 1929536 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 731978130 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -373,5 +393,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 307c9a306..c00464415 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.199986 # Number of seconds simulated -sim_ticks 199986318000 # Number of ticks simulated -final_tick 199986318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202265 # Number of seconds simulated +sim_ticks 202264702500 # Number of ticks simulated +final_tick 202264702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53828 # Simulator instruction rate (inst/s) -host_op_rate 60688 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21306693 # Simulator tick rate (ticks/s) -host_mem_usage 292380 # Number of bytes of host memory used -host_seconds 9386.08 # Real time elapsed on the host +host_inst_rate 152154 # Simulator instruction rate (inst/s) +host_op_rate 171544 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60912686 # Simulator tick rate (ticks/s) +host_mem_usage 250588 # Number of bytes of host memory used +host_seconds 3320.57 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9268096 # Number of bytes read from this memory -system.physmem.bytes_read::total 9484800 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216704 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6249408 # Number of bytes written to this memory -system.physmem.bytes_written::total 6249408 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144814 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148200 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97647 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97647 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1083594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46343650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47427244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1083594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1083594 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31249178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31249178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31249178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1083594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46343650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 78676422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148200 # Total number of read requests seen -system.physmem.writeReqs 97647 # Total number of write requests seen -system.physmem.cpureqs 245864 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9484800 # Total number of bytes read from memory -system.physmem.bytesWritten 6249408 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9484800 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6249408 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 216000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9260928 # Number of bytes read from this memory +system.physmem.bytes_read::total 9476928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6246016 # Number of bytes written to this memory +system.physmem.bytes_written::total 6246016 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144702 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148077 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97594 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97594 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1067908 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45786180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46854087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1067908 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1067908 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30880405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30880405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30880405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1067908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45786180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77734493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148078 # Total number of read requests seen +system.physmem.writeReqs 97594 # Total number of write requests seen +system.physmem.cpureqs 245687 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9476928 # Total number of bytes read from memory +system.physmem.bytesWritten 6246016 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9476928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6246016 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9533 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9493 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9413 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 9073 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 9057 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 9296 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8842 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9072 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9010 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 9027 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9230 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5978 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6480 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6216 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 6227 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 6024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 6210 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5897 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6059 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6112 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 9583 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9281 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8971 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9774 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8322 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8802 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8932 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9735 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9616 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9782 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 8932 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9434 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6145 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6098 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5882 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6246 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6280 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6041 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5558 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5899 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6350 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6340 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6045 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6130 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry -system.physmem.totGap 199986294500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry +system.physmem.totGap 202264683000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148200 # Categorize read packet sizes +system.physmem.readPktSize::6 148078 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97647 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 138069 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 9399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97594 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 138541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8888 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,68 +124,198 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see -system.physmem.totQLat 1719312500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4989180000 # Sum of mem lat for all requests -system.physmem.totBusLat 740610000 # Total cycles spent in databus access -system.physmem.totBankLat 2529257500 # Total cycles spent in bank access -system.physmem.avgQLat 11607.41 # Average queueing delay per request -system.physmem.avgBankLat 17075.50 # Average bank access latency per request +system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 55927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 281.047508 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.123063 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 688.589570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 27857 49.81% 49.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 10311 18.44% 68.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4742 8.48% 76.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2859 5.11% 81.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1799 3.22% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1160 2.07% 87.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 842 1.51% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 665 1.19% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 468 0.84% 90.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 376 0.67% 91.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 271 0.48% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 239 0.43% 92.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 201 0.36% 92.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 180 0.32% 92.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 171 0.31% 93.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 177 0.32% 93.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 169 0.30% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 170 0.30% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 147 0.26% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 156 0.28% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 167 0.30% 94.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 250 0.45% 95.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 974 1.74% 97.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 239 0.43% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 147 0.26% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 173 0.31% 98.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 101 0.18% 98.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 105 0.19% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 71 0.13% 98.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 56 0.10% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 36 0.06% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 46 0.08% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 27 0.05% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 25 0.04% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 21 0.04% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 22 0.04% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 17 0.03% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 12 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 14 0.03% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 11 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 12 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 9 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 11 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 10 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 4 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 8 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 7 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 5 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 3 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 7 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 4 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 9 0.02% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 3 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 4 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 4 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 55927 # Bytes accessed per row activation +system.physmem.totQLat 1510568250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4629837000 # Sum of mem lat for all requests +system.physmem.totBusLat 740065000 # Total cycles spent in databus access +system.physmem.totBankLat 2379203750 # Total cycles spent in bank access +system.physmem.avgQLat 10205.65 # Average queueing delay per request +system.physmem.avgBankLat 16074.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 33682.91 # Average memory access latency -system.physmem.avgRdBW 47.43 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 47.43 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31279.93 # Average memory access latency +system.physmem.avgRdBW 46.85 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 30.88 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 46.85 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 30.88 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.37 # Average write queue length over time -system.physmem.readRowHits 125428 # Number of row buffer hits during reads -system.physmem.writeRowHits 52865 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 54.14 # Row buffer hit rate for writes -system.physmem.avgGap 813458.35 # Average gap between requests -system.cpu.branchPred.lookups 182823475 # Number of BP lookups -system.cpu.branchPred.condPredicted 143127293 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7270205 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 92181207 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87235258 # Number of BTB hits +system.physmem.avgWrQLen 8.55 # Average write queue length over time +system.physmem.readRowHits 130620 # Number of row buffer hits during reads +system.physmem.writeRowHits 59055 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.51 # Row buffer hit rate for writes +system.physmem.avgGap 823311.91 # Average gap between requests +system.membus.throughput 77734493 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46795 # Transaction distribution +system.membus.trans_dist::ReadResp 46794 # Transaction distribution +system.membus.trans_dist::Writeback 97594 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 101283 # Transaction distribution +system.membus.trans_dist::ReadExResp 101283 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 393767 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 393767 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15722944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 15722944 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15722944 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1079125750 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1399666492 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu.branchPred.lookups 182795351 # Number of BP lookups +system.cpu.branchPred.condPredicted 143107535 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7264975 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93466227 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87209092 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.634537 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12683949 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116293 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.305459 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12678830 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 116057 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +359,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 399972637 # number of cpu cycles simulated +system.cpu.numCycles 404529406 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119392306 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761693904 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182823475 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99919207 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170173986 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35705843 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 75415774 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 554 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114545284 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2440918 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 392617380 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.175996 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.990505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119370904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761561247 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182795351 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99887922 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170134463 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35678521 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77150212 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 98 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 455 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114522843 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2439505 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394266586 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166435 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.987414 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222455990 56.66% 56.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14183959 3.61% 60.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22907819 5.83% 66.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22738821 5.79% 71.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20904503 5.32% 77.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11594029 2.95% 80.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13063211 3.33% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12002083 3.06% 86.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52766965 13.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224144737 56.85% 56.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14179887 3.60% 60.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22893161 5.81% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22745024 5.77% 72.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20894474 5.30% 77.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11598135 2.94% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13057002 3.31% 83.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11992402 3.04% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52761764 13.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 392617380 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.457090 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.904365 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129046079 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70945312 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158884174 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6181299 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27560516 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26130325 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76946 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825690179 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 295591 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27560516 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135633063 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 9642191 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46463188 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158301033 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15017389 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800753920 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1207 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3038316 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8776785 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 223 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954449423 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3501232166 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3501230756 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1410 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394266586 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.451872 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.882586 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129061208 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 72641827 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158799298 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6227893 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27536360 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26125699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76608 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825532349 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 291942 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27536360 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135656827 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10155018 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47441534 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158249633 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15227214 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800580004 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1401 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3056484 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8970861 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 208 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954230970 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500428728 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500427418 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1310 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 288197132 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2293078 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2293075 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41509096 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170293066 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73496638 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28553519 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15543647 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755184516 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775403 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665423791 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1392561 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187499467 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 480050290 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797771 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 392617380 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.694840 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.736370 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 287978679 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292969 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41852604 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170255884 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73472812 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28582851 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15746500 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755022174 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775311 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665301102 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1380692 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187339157 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479760666 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797679 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394266586 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.687440 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.735091 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 137266683 34.96% 34.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69764327 17.77% 52.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71469341 18.20% 70.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53405229 13.60% 84.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31142767 7.93% 92.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16033920 4.08% 96.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8799646 2.24% 98.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2917185 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1818282 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 138747020 35.19% 35.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69982581 17.75% 52.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71470863 18.13% 71.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53423224 13.55% 84.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31142023 7.90% 92.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16022250 4.06% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8747194 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2906831 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1824600 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 392617380 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394266586 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479464 4.97% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6557477 68.01% 72.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2605087 27.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 480987 5.01% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6546208 68.16% 73.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2577471 26.84% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447824113 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383504 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447771708 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383310 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 98 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -384,84 +514,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153397745 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63818328 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153352638 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63793353 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665423791 # Type of FU issued -system.cpu.iq.rate 1.663673 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9642028 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014490 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1734499320 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 947266498 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646124282 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 310 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665301102 # Type of FU issued +system.cpu.iq.rate 1.644630 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9604666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014437 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1735853933 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 946943275 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646028886 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 675065702 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8583068 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674905659 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8552862 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44263511 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 42384 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 811218 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16636161 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44226329 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41059 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810522 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16612335 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19502 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4251 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19495 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 7104 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27560516 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5033845 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 374098 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760518622 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1117950 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170293066 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73496638 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286861 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 218393 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 11953 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 811218 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4001637 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8344571 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655982546 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150110737 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9441245 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27536360 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5290664 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 387489 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760356154 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1118953 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170255884 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73472812 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286769 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219863 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12400 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810522 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4337912 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4002750 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8340662 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655875003 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150077564 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9426099 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558703 # number of nop insts executed -system.cpu.iew.exec_refs 212627196 # number of memory reference insts executed -system.cpu.iew.exec_branches 138502657 # Number of branches executed -system.cpu.iew.exec_stores 62516459 # Number of stores executed -system.cpu.iew.exec_rate 1.640069 # Inst execution rate -system.cpu.iew.wb_sent 651101010 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646124298 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374793054 # num instructions producing a value -system.cpu.iew.wb_consumers 646490687 # num instructions consuming a value +system.cpu.iew.exec_nop 1558669 # number of nop insts executed +system.cpu.iew.exec_refs 212570616 # number of memory reference insts executed +system.cpu.iew.exec_branches 138493352 # Number of branches executed +system.cpu.iew.exec_stores 62493052 # Number of stores executed +system.cpu.iew.exec_rate 1.621328 # Inst execution rate +system.cpu.iew.wb_sent 650999754 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646028902 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374692861 # num instructions producing a value +system.cpu.iew.wb_consumers 646290036 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.615421 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579735 # average fanout of values written-back +system.cpu.iew.wb_rate 1.596989 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189577075 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189414626 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7196029 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 365056864 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.564053 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233130 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7190929 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 366730226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.556916 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.230567 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 157408999 43.12% 43.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98427012 26.96% 70.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33819592 9.26% 79.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18764553 5.14% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16211195 4.44% 88.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7486266 2.05% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7003829 1.92% 92.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3174116 0.87% 93.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22761302 6.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 159030510 43.36% 43.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98471088 26.85% 70.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33850160 9.23% 79.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18801710 5.13% 84.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16194042 4.42% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7449344 2.03% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6951093 1.90% 92.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3196049 0.87% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22786230 6.21% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 365056864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 366730226 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,199 +602,225 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22761302 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22786230 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1102833666 # The number of ROB reads -system.cpu.rob.rob_writes 1548772691 # The number of ROB writes -system.cpu.timesIdled 308172 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7355257 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104319651 # The number of ROB reads +system.cpu.rob.rob_writes 1548423446 # The number of ROB writes +system.cpu.timesIdled 327931 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10262820 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.791652 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.791652 # CPI: Total CPI of All Threads -system.cpu.ipc 1.263181 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.263181 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3059089015 # number of integer regfile reads -system.cpu.int_regfile_writes 752056601 # number of integer regfile writes +system.cpu.cpi 0.800671 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.800671 # CPI: Total CPI of All Threads +system.cpu.ipc 1.248952 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.248952 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058568749 # number of integer regfile reads +system.cpu.int_regfile_writes 751946172 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210873671 # number of misc regfile reads +system.cpu.misc_regfile_reads 210826056 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.icache.replacements 14975 # number of replacements -system.cpu.icache.tagsinuse 1101.758220 # Cycle average of tags in use -system.cpu.icache.total_refs 114524199 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16829 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6805.169588 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 735267470 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1110556 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 92 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 92 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348774 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348774 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33891 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3536981 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1081088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147630784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148711872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148711872 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 6784 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2272470744 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 25507479 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1794320975 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.replacements 15058 # number of replacements +system.cpu.icache.tagsinuse 1102.051233 # Cycle average of tags in use +system.cpu.icache.total_refs 114501571 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16910 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6771.234240 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1101.758220 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.537968 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.537968 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114524201 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114524201 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114524201 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114524201 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114524201 # number of overall hits -system.cpu.icache.overall_hits::total 114524201 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21083 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21083 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21083 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21083 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21083 # number of overall misses -system.cpu.icache.overall_misses::total 21083 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 513115000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 513115000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 513115000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 513115000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 513115000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 513115000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114545284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114545284 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114545284 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114545284 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114545284 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114545284 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24337.855144 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24337.855144 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24337.855144 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24337.855144 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24337.855144 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24337.855144 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 507 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1102.051233 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.538111 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.538111 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114501582 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114501582 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114501582 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114501582 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114501582 # number of overall hits +system.cpu.icache.overall_hits::total 114501582 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21259 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21259 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21259 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21259 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21259 # number of overall misses +system.cpu.icache.overall_misses::total 21259 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 595415500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 595415500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 595415500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 595415500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 595415500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 595415500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114522841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114522841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114522841 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114522841 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114522841 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114522841 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28007.690860 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28007.690860 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28007.690860 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28007.690860 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28007.690860 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28007.690860 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2365 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.090909 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 181.923077 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4176 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4176 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 373240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 373240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 373240000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 373240000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4260 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4260 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4260 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4260 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4260 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4260 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16999 # 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number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3376 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43419 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46795 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101303 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101303 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3386 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144814 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148200 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3386 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144814 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148200 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 179125175 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2382731950 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2561857125 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 90009 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 90009 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3956091381 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3956091381 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 179125175 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6338823331 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6517948506 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 179125175 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6338823331 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6517948506 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.201296 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051330 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054248 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.113924 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.113924 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290435 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290435 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.201296 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121034 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122147 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.201296 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121034 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122147 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52901.705552 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54761.599366 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54627.313581 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39052.065398 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39052.065398 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52901.705552 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43772.172104 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43980.759150 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52901.705552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43772.172104 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43980.759150 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3376 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144702 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148078 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3376 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144702 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148078 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 231774000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3104828000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3336602000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 94508 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 94508 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5779215000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5779215000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 231774000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8884043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9115817000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 231774000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8884043000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9115817000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051238 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054142 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097826 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097826 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122069 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122069 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68653.436019 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71508.510099 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71302.532322 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10500.888889 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10500.888889 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57060.069311 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57060.069311 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68653.436019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61395.440284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61560.913843 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68653.436019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61395.440284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.913843 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192373 # number of replacements -system.cpu.dcache.tagsinuse 4058.219651 # Cycle average of tags in use -system.cpu.dcache.total_refs 190179591 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196469 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.950705 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4058.219651 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990776 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990776 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136210299 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136210299 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50991632 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50991632 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488823 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488823 # number of LoadLockedReq hits +system.cpu.dcache.replacements 1192079 # number of replacements +system.cpu.dcache.tagsinuse 4057.787384 # Cycle average of tags in use +system.cpu.dcache.total_refs 190170418 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196175 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.982104 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4220492000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4057.787384 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990671 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990671 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136204469 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136204469 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50988281 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50988281 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488831 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488831 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187201931 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187201931 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187201931 # number of overall hits -system.cpu.dcache.overall_hits::total 187201931 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1698949 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1698949 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3247674 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3247674 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4946623 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4946623 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4946623 # number of overall misses -system.cpu.dcache.overall_misses::total 4946623 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26713032500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26713032500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57280936446 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57280936446 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 664500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 664500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83993968946 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83993968946 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83993968946 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83993968946 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137909248 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137909248 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187192750 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187192750 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187192750 # number of overall hits +system.cpu.dcache.overall_hits::total 187192750 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1701442 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1701442 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3251025 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3251025 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4952467 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4952467 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4952467 # number of overall misses +system.cpu.dcache.overall_misses::total 4952467 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29643398500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29643398500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 68982804444 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 68982804444 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 639500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 639500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 98626202944 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98626202944 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 98626202944 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98626202944 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137905911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137905911 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488864 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488864 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488869 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488869 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192148554 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192148554 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192148554 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192148554 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012319 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012319 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15723.269209 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15723.269209 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17637.526564 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 17637.526564 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16207.317073 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16207.317073 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 16980.062751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16980.062751 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15427 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 16116 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1677 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 607 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.199165 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26.550247 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192145217 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192145217 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192145217 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192145217 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012338 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012338 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000026 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000026 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025775 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025775 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025775 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025775 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17422.514843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17422.514843 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21218.786212 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21218.786212 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16828.947368 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16828.947368 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19914.560348 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19914.560348 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17857 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40598 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1694 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 662 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.541322 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 61.326284 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110717 # number of writebacks -system.cpu.dcache.writebacks::total 1110717 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850753 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 850753 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899322 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2899322 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3750075 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3750075 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3750075 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3750075 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848196 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 848196 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348352 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348352 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196548 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196548 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196548 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196548 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11853689000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11853689000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8094107996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8094107996 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19947796996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 19947796996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19947796996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 19947796996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13975.176728 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13975.176728 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23235.428521 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23235.428521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1110556 # number of writebacks +system.cpu.dcache.writebacks::total 1110556 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 853509 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 853509 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902691 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2902691 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3756200 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3756200 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3756200 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3756200 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 847933 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 847933 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348334 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348334 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196267 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196267 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196267 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196267 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12570935024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12570935024 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9915738995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9915738995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22486674019 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22486674019 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22486674019 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22486674019 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006149 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006226 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006226 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14825.387176 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14825.387176 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28466.181869 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28466.181869 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index d2bcd7c59..14e1e1ee2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu sim_ticks 290498967000 # Number of ticks simulated final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1613323 # Simulator instruction rate (inst/s) -host_op_rate 1818377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 925159382 # Simulator tick rate (ticks/s) -host_mem_usage 282068 # Number of bytes of host memory used -host_seconds 314.00 # Real time elapsed on the host +host_inst_rate 1591705 # Simulator instruction rate (inst/s) +host_op_rate 1794011 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 912762441 # Simulator tick rate (ticks/s) +host_mem_usage 237748 # Number of bytes of host memory used +host_seconds 318.26 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 570968167 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 743781041 # Wr system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9312824252 # Throughput (bytes/s) +system.membus.data_through_bus 2705365825 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 264bc47b4..0fce97b03 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.717366 # Nu sim_ticks 717366012000 # Number of ticks simulated final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 858996 # Simulator instruction rate (inst/s) -host_op_rate 967944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220258898 # Simulator tick rate (ticks/s) -host_mem_usage 290524 # Number of bytes of host memory used -host_seconds 587.88 # Real time elapsed on the host +host_inst_rate 611042 # Simulator instruction rate (inst/s) +host_op_rate 688541 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 868024183 # Simulator tick rate (ticks/s) +host_mem_usage 246240 # Number of bytes of host memory used +host_seconds 826.44 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 8560472 # To system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 21286941 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 41855 # Transaction distribution +system.membus.trans_dist::ReadResp 41855 # Transaction distribution +system.membus.trans_dist::Writeback 95953 # Transaction distribution +system.membus.trans_dist::ReadExReq 100794 # Transaction distribution +system.membus.trans_dist::ReadExResp 100794 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 381251 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 381251 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 15270528 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15270528 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23042 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3342741 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3365783 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 737344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 141044672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 141782016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 2c49dab74..ab0625bed 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451833 # Number of seconds simulated -sim_ticks 451832922000 # Number of ticks simulated -final_tick 451832922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.458090 # Number of seconds simulated +sim_ticks 458090415000 # Number of ticks simulated +final_tick 458090415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67045 # Simulator instruction rate (inst/s) -host_op_rate 123974 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36635806 # Simulator tick rate (ticks/s) -host_mem_usage 390776 # Number of bytes of host memory used -host_seconds 12333.10 # Real time elapsed on the host +host_inst_rate 96465 # Simulator instruction rate (inst/s) +host_op_rate 178374 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53441498 # Simulator tick rate (ticks/s) +host_mem_usage 343040 # Number of bytes of host memory used +host_seconds 8571.81 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24482112 # Number of bytes read from this memory -system.physmem.bytes_read::total 24684928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18794304 # Number of bytes written to this memory -system.physmem.bytes_written::total 18794304 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385702 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293661 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293661 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 448874 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54183993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54632867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 448874 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 448874 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41595694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41595694 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41595694 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 448874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54183993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96228561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385702 # Total number of read requests seen -system.physmem.writeReqs 293661 # Total number of write requests seen -system.physmem.cpureqs 815428 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 24684928 # Total number of bytes read from memory -system.physmem.bytesWritten 18794304 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 24684928 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 18794304 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 136028 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 23108 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 24460 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 23977 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 22639 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23451 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24452 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 24479 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 24189 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 24310 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 25055 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 24328 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 24340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 23420 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 24898 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 23991 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 17770 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 18792 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 18332 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 17557 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 18441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 18303 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 18298 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 18726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 19016 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 18442 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 18563 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 17871 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 18864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 18115 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 202496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24476544 # Number of bytes read from this memory +system.physmem.bytes_read::total 24679040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18790272 # Number of bytes written to this memory +system.physmem.bytes_written::total 18790272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382446 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385610 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293598 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293598 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53431688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53873731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41018697 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41018697 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41018697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53431688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94892429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385610 # Total number of read requests seen +system.physmem.writeReqs 293598 # Total number of write requests seen +system.physmem.cpureqs 811581 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 24679040 # Total number of bytes read from memory +system.physmem.bytesWritten 18790272 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 24679040 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 18790272 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 158 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 132366 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 26444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 24671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 24517 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 23227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 23669 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 24418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 24212 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 23834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 24778 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24050 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 23243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 22960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 23768 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 23988 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 18530 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 18950 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 18922 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 18033 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 18412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 18983 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 18945 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 18535 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 18118 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 17707 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 16952 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 17709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 17824 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 37 # Number of times wr buffer was full causing retry -system.physmem.totGap 451832896000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry +system.physmem.totGap 458090389000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 385702 # Categorize read packet sizes +system.physmem.readPktSize::6 385610 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 293661 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 380831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4356 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 329 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293598 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 380772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,195 +124,347 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 12719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 12722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 12723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 12725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 12728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 12729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 12768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 39 # What write queue length does an incoming req see -system.physmem.totQLat 3445991500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12040169000 # Sum of mem lat for all requests -system.physmem.totBusLat 1927820000 # Total cycles spent in databus access -system.physmem.totBankLat 6666357500 # Total cycles spent in bank access -system.physmem.avgQLat 8937.53 # Average queueing delay per request -system.physmem.avgBankLat 17289.89 # Average bank access latency per request +system.physmem.wrQLenPdf::0 12721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 12733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 12738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 12746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 12748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 12751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 12755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 12756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 126022 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 344.851534 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.962358 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 666.348366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 54057 42.89% 42.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 23501 18.65% 61.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 10538 8.36% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 6321 5.02% 74.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 4049 3.21% 78.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 2993 2.37% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 2158 1.71% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1750 1.39% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 1435 1.14% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 1167 0.93% 85.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 1218 0.97% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 1087 0.86% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 749 0.59% 88.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 671 0.53% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 595 0.47% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 568 0.45% 89.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 568 0.45% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 525 0.42% 90.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 573 0.45% 90.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 736 0.58% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 592 0.47% 91.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 743 0.59% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 6177 4.90% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 481 0.38% 97.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 330 0.26% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 288 0.23% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 210 0.17% 98.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 190 0.15% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 142 0.11% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 147 0.12% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 96 0.08% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 92 0.07% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 69 0.05% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 52 0.04% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 45 0.04% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 44 0.03% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 35 0.03% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 33 0.03% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 28 0.02% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 24 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 31 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 21 0.02% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 18 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 25 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 20 0.02% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 17 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 13 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 15 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 13 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 16 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 6 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 9 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 7 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 17 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 9 0.01% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 8 0.01% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 13 0.01% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 9 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 5 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 13 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 4 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 8 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 5 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 4 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 8 0.01% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 6 0.00% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 7 0.01% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 9 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 3 0.00% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 8 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 11 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 5 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 5 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 5 0.00% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 4 0.00% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 373 0.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 126022 # Bytes accessed per row activation +system.physmem.totQLat 3040953000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11219526750 # Sum of mem lat for all requests +system.physmem.totBusLat 1927260000 # Total cycles spent in databus access +system.physmem.totBankLat 6251313750 # Total cycles spent in bank access +system.physmem.avgQLat 7889.32 # Average queueing delay per request +system.physmem.avgBankLat 16218.14 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31227.42 # Average memory access latency -system.physmem.avgRdBW 54.63 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 41.60 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 54.63 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 41.60 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 29107.46 # Average memory access latency +system.physmem.avgRdBW 53.87 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 41.02 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 41.02 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 0.75 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 8.94 # Average write queue length over time -system.physmem.readRowHits 331871 # Number of row buffer hits during reads -system.physmem.writeRowHits 191829 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes -system.physmem.avgGap 665083.17 # Average gap between requests -system.cpu.branchPred.lookups 205621718 # Number of BP lookups -system.cpu.branchPred.condPredicted 205621718 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9907083 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117077740 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114695478 # Number of BTB hits +system.physmem.busUtil 0.74 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.02 # Average read queue length over time +system.physmem.avgWrQLen 10.25 # Average write queue length over time +system.physmem.readRowHits 346179 # Number of row buffer hits during reads +system.physmem.writeRowHits 206846 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 70.45 # Row buffer hit rate for writes +system.physmem.avgGap 674447.87 # Average gap between requests +system.membus.throughput 94892429 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178764 # Transaction distribution +system.membus.trans_dist::ReadResp 178764 # Transaction distribution +system.membus.trans_dist::Writeback 293598 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132366 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132366 # Transaction distribution +system.membus.trans_dist::ReadExReq 206846 # Transaction distribution +system.membus.trans_dist::ReadExResp 206846 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1329550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1329550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1329550 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43469312 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43469312 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 3305392000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 3861844643 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.branchPred.lookups 205596082 # Number of BP lookups +system.cpu.branchPred.condPredicted 205596082 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9898225 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117113450 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114684719 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.965231 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25073647 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1800250 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.926172 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25065236 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1793499 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903825131 # number of cpu cycles simulated +system.cpu.numCycles 916341755 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167418043 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1132282338 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205621718 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139769125 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352430400 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71153000 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 297148174 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 48797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 255592 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162064992 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2572532 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 878293133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.398381 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.331165 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167380851 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131684299 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205596082 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139749955 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352238514 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71080243 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 303608780 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 49221 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 257762 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162013900 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2533511 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 884463501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380571 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325217 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 529920988 60.34% 60.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23389932 2.66% 63.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25306191 2.88% 65.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27947555 3.18% 69.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17765128 2.02% 71.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22905202 2.61% 73.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29375609 3.34% 77.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26663527 3.04% 80.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175019001 19.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536297540 60.64% 60.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23375974 2.64% 63.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25249823 2.85% 66.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27885460 3.15% 69.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17746776 2.01% 71.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22912915 2.59% 73.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29432713 3.33% 77.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26649868 3.01% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174912432 19.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 878293133 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.227502 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.252767 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222360951 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 252528998 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295744531 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46666559 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60992094 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071948592 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 60992094 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 255743691 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 109858014 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 17204 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306968990 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 144713140 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035757004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14813 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25048489 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 104458594 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 180 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2138803025 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5151932301 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5151817228 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 115073 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 884463501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224366 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.235002 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222590662 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258678079 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295142458 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 47123970 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60928332 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071292159 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60928332 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256060013 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 114129471 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 17113 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306672128 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146656444 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035150603 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19208 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24905685 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106527720 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 191 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2137983634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150411981 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5150294631 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 117350 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 524762171 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1163 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1096 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 344343454 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 496005535 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194479256 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195803959 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 55147463 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975947809 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 16072 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772430246 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 489293 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 442088890 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 735772933 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15520 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 878293133 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.018040 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.884895 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 523942780 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1169 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 347123881 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495862419 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194434977 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195681210 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 55050050 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975391803 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13688 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772107860 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 473436 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441529176 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 734849750 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13136 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 884463501 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.003596 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883133 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 263200988 29.97% 29.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 149900664 17.07% 47.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137095286 15.61% 62.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132054982 15.04% 77.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91669420 10.44% 88.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 56193413 6.40% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34492530 3.93% 98.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11912661 1.36% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1773189 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 267821241 30.28% 30.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151877147 17.17% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137227346 15.52% 62.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131884953 14.91% 77.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91607169 10.36% 88.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55986805 6.33% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34422638 3.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11866983 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1769219 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 878293133 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 884463501 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4998230 32.74% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7655755 50.14% 82.88% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2613853 17.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4968361 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7638299 50.16% 82.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2620527 17.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2627910 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165981895 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352516 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880818 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2623300 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165765153 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 352884 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880872 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -339,84 +491,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429341212 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170245895 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429256529 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170229122 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772430246 # Type of FU issued -system.cpu.iq.rate 1.961032 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15267838 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008614 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4438895750 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2418277528 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1745063548 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15006 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 33162 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3630 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1785062995 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7179 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172239839 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772107860 # Type of FU issued +system.cpu.iq.rate 1.933894 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15227187 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008593 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4444363529 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417156929 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744871940 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 16315 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 34548 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3820 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784704039 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7708 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172523009 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111903378 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 383433 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 329474 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45320259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111760262 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 384025 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328721 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45275855 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14682 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 568 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 15305 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 564 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60992094 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 64075051 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7111223 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975963881 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 801543 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 496005535 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194480445 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3509 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4460880 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 329474 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5903386 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4417104 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10320490 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1753197001 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424204757 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19233245 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60928332 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 66654454 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7158115 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975405491 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 788328 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495862419 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194436041 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3451 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4460839 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82816 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328721 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5900080 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4426535 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10326615 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1752972690 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424121378 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19135170 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 591004689 # number of memory reference insts executed -system.cpu.iew.exec_branches 167488871 # Number of branches executed -system.cpu.iew.exec_stores 166799932 # Number of stores executed -system.cpu.iew.exec_rate 1.939752 # Inst execution rate -system.cpu.iew.wb_sent 1749947599 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1745067178 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1326505641 # num instructions producing a value -system.cpu.iew.wb_consumers 1948512890 # num instructions consuming a value +system.cpu.iew.exec_refs 590916604 # number of memory reference insts executed +system.cpu.iew.exec_branches 167471832 # Number of branches executed +system.cpu.iew.exec_stores 166795226 # Number of stores executed +system.cpu.iew.exec_rate 1.913012 # Inst execution rate +system.cpu.iew.wb_sent 1749734148 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744875760 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1325266031 # num instructions producing a value +system.cpu.iew.wb_consumers 1946145137 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.930758 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680778 # average fanout of values written-back +system.cpu.iew.wb_rate 1.904176 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680970 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 447002783 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446445392 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9936450 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 817301039 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.870778 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.444599 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9927956 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 823535169 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.856616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.436023 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 326881530 40.00% 40.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 191845418 23.47% 63.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 62847977 7.69% 71.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92272413 11.29% 82.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25036529 3.06% 85.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27653799 3.38% 88.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9274477 1.13% 90.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11343051 1.39% 91.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70145845 8.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 331309797 40.23% 40.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193436575 23.49% 63.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63121599 7.66% 71.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92647186 11.25% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25073312 3.04% 85.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27553603 3.35% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9217324 1.12% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11404021 1.38% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69771752 8.47% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 817301039 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 823535169 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -427,204 +579,226 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1528317561 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 70145845 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69771752 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2723146678 # The number of ROB reads -system.cpu.rob.rob_writes 4013137574 # The number of ROB writes -system.cpu.timesIdled 3358951 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25531998 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2729197510 # The number of ROB reads +system.cpu.rob.rob_writes 4011957603 # The number of ROB writes +system.cpu.timesIdled 3360338 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31878254 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.093059 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.093059 # CPI: Total CPI of All Threads -system.cpu.ipc 0.914864 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.914864 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3313860690 # number of integer regfile reads -system.cpu.int_regfile_writes 1826087017 # number of integer regfile writes -system.cpu.fp_regfile_reads 3611 # number of floating regfile reads -system.cpu.fp_regfile_writes 20 # number of floating regfile writes -system.cpu.misc_regfile_reads 964797382 # number of misc regfile reads +system.cpu.cpi 1.108196 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108196 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902368 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902368 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3313525285 # number of integer regfile reads +system.cpu.int_regfile_writes 1825886137 # number of integer regfile writes +system.cpu.fp_regfile_reads 3803 # number of floating regfile reads +system.cpu.fp_regfile_writes 18 # number of floating regfile writes +system.cpu.misc_regfile_reads 964657168 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 5491 # number of replacements -system.cpu.icache.tagsinuse 1036.603099 # Cycle average of tags in use -system.cpu.icache.total_refs 161916606 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 7071 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 22898.685617 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 699341277 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1903111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1903110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330801 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 133805 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 133805 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771738 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771738 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 147545 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7666657 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7814202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 436416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 311355136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 311791552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311791552 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8569984 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4904454883 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 211090494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3868088996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.cpu.icache.replacements 5303 # number of replacements +system.cpu.icache.tagsinuse 1039.981291 # Cycle average of tags in use +system.cpu.icache.total_refs 161869191 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6885 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 23510.412636 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1036.603099 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.506154 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.506154 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161918575 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161918575 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161918575 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161918575 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161918575 # number of overall hits -system.cpu.icache.overall_hits::total 161918575 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 146417 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 146417 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 146417 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 146417 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 146417 # number of overall misses -system.cpu.icache.overall_misses::total 146417 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 875142000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 875142000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 875142000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 875142000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 875142000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 875142000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162064992 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162064992 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162064992 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162064992 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162064992 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162064992 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000903 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000903 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000903 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000903 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000903 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000903 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5977.051845 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 5977.051845 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 5977.051845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 5977.051845 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 5977.051845 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1375 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1039.981291 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.507803 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.507803 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 161871216 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161871216 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161871216 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161871216 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161871216 # number of overall hits +system.cpu.icache.overall_hits::total 161871216 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 142683 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 142683 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 142683 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 142683 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 142683 # number of overall misses +system.cpu.icache.overall_misses::total 142683 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 931781000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 931781000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 931781000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 931781000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 931781000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 931781000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162013899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162013899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162013899 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162013899 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162013899 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162013899 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000881 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000881 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000881 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000881 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000881 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000881 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6530.427591 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6530.427591 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6530.427591 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6530.427591 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6530.427591 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 250 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 229.166667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 250 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 144572 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 144572 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 144572 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 144572 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 144572 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 144572 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 521583500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 521583500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 521583500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 521583500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 521583500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 521583500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000892 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000892 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000892 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000892 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3607.776748 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3607.776748 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3607.776748 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3607.776748 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3607.776748 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3607.776748 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1957 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1957 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1957 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1957 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1957 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1957 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 140726 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 140726 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 140726 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 140726 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 140726 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 140726 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 559745506 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 559745506 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 559745506 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 559745506 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 559745506 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 559745506 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000869 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000869 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000869 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000869 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3977.555718 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3977.555718 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3977.555718 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3977.555718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3977.555718 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3977.555718 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 353019 # number of replacements -system.cpu.l2cache.tagsinuse 29665.542211 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3698954 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 385379 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 9.598224 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 196543776500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 21121.895278 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 226.041869 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 8317.605064 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.644589 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.006898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.253833 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.905321 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3851 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1587691 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1591542 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2331818 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2331818 # 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number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 135999 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 135999 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 206937 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206937 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3170 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 382562 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 385732 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 382562 # number of overall misses -system.cpu.l2cache.overall_misses::total 385732 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 197656000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10096367454 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150927 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151768 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.464076 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150927 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151768 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65108.767773 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62563.391002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62608.456409 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.562194 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.562194 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56169.333933 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56169.333933 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65108.767773 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59104.995011 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59154.269686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65108.767773 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59104.995011 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59154.269686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 2531750 # number of replacements -system.cpu.dcache.tagsinuse 4088.641557 # Cycle average of tags in use -system.cpu.dcache.total_refs 396440107 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2535846 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 156.334457 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 1679431000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4088.641557 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.998204 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.998204 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 247707841 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 247707841 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148233543 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148233543 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 395941384 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 395941384 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 395941384 # number of overall hits -system.cpu.dcache.overall_hits::total 395941384 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2871315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2871315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 926659 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 926659 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3797974 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3797974 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3797974 # number of overall misses -system.cpu.dcache.overall_misses::total 3797974 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 51373394500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 51373394500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21994238500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21994238500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 73367633000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 73367633000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 73367633000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 73367633000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250579156 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250579156 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 2530027 # number of replacements +system.cpu.dcache.tagsinuse 4088.382661 # Cycle average of tags in use +system.cpu.dcache.total_refs 396086661 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2534123 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 156.301277 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 1759751000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4088.382661 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.998140 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.998140 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 247356702 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247356702 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148237858 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148237858 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395594560 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 395594560 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 395594560 # number of overall hits +system.cpu.dcache.overall_hits::total 395594560 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2862804 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2862804 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 922344 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 922344 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3785148 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3785148 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3785148 # number of overall misses +system.cpu.dcache.overall_misses::total 3785148 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57011675000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57011675000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 25670326998 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 25670326998 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 82682001998 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 82682001998 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 82682001998 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 82682001998 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250219506 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250219506 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399739358 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399739358 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399739358 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399739358 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011459 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011459 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006213 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006213 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009501 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009501 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009501 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009501 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.939582 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.939582 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23734.986117 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23734.986117 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19317.571158 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19317.571158 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19317.571158 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6008 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 399379708 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 399379708 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 399379708 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 399379708 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011441 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011441 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006184 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006184 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009478 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009478 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009478 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009478 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19914.627407 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19914.627407 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27831.619220 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 27831.619220 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21843.796332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21843.796332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21843.796332 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6595 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 680 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 671 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.835294 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.828614 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2331818 # number of writebacks -system.cpu.dcache.writebacks::total 2331818 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1107712 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1107712 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16962 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16962 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1124674 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1124674 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1124674 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1124674 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1763603 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1763603 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 909697 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 909697 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2673300 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2673300 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2673300 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2673300 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27774523500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27774523500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972622500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972622500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47747146000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47747146000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47747146000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47747146000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007038 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007038 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006688 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006688 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006688 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15748.739087 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15748.739087 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21955.247187 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21955.247187 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17860.751132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17860.751132 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330801 # number of writebacks +system.cpu.dcache.writebacks::total 2330801 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1100153 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1100153 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17067 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17067 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1117220 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1117220 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1117220 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1117220 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762651 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762651 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 905277 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 905277 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2667928 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2667928 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2667928 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2667928 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30822255503 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30822255503 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23648350501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23648350501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 54470606004 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 54470606004 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 54470606004 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 54470606004 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007044 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007044 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006069 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006680 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006680 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006680 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17486.306423 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17486.306423 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26122.778444 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26122.778444 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 6867203d8..0326dde96 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1120443517 # Wr system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13357308966 # Throughput (bytes/s) +system.membus.data_through_bus 11824281640 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 1770458657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 7c0f3a039..3dc840346 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 11351788 # To system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 26154600 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 174452 # Transaction distribution +system.membus.trans_dist::ReadResp 174452 # Transaction distribution +system.membus.trans_dist::Writeback 292286 # Transaction distribution +system.membus.trans_dist::ReadExReq 206691 # Transaction distribution +system.membus.trans_dist::ReadExResp 206691 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43099456 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 3295745698 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -373,5 +393,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 5628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7360439 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7366067 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 180096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309886784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 310066880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 188ee6566..dfb21513b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.139855 # Number of seconds simulated -sim_ticks 139855372500 # Number of ticks simulated -final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.139913 # Number of seconds simulated +sim_ticks 139912878500 # Number of ticks simulated +final_tick 139912878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118034 # Simulator instruction rate (inst/s) -host_op_rate 118034 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41407532 # Simulator tick rate (ticks/s) -host_mem_usage 230404 # Number of bytes of host memory used -host_seconds 3377.53 # Real time elapsed on the host +host_inst_rate 81894 # Simulator instruction rate (inst/s) +host_op_rate 81894 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28740964 # Simulator tick rate (ticks/s) +host_mem_usage 231128 # Number of bytes of host memory used +host_seconds 4868.07 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 214976 # Nu system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1537131 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1816276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3353407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1537131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1537131 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1537131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1816276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3353407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1536499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1815530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3352029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1536499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1536499 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1536499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1815530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3352029 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7328 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 468992 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 442 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 430 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 467 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 578 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 528 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 597 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 451 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 466 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 394 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 394 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 459 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 423 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 509 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 513 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 395 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 336 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 304 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 416 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 534 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 371 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 139855320500 # Total gap between requests +system.physmem.totGap 139912806500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1856 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,14 +149,84 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 47654000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 197332750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 702 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 659.145299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 261.737271 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1246.496021 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 193 27.49% 27.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 99 14.10% 41.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 67 9.54% 51.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 56 7.98% 59.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 35 4.99% 64.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 20 2.85% 66.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 23 3.28% 70.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 21 2.99% 73.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 15 2.14% 75.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 12 1.71% 77.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 9 1.28% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 4 0.57% 78.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 12 1.71% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 8 1.14% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 4 0.57% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.71% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 15 2.14% 85.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.71% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 6 0.85% 86.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1 0.14% 86.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 4 0.57% 87.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.57% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.57% 88.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.43% 89.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 6 0.85% 89.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 6 0.85% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 3 0.43% 91.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.14% 91.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.43% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.57% 93.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 2 0.28% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.28% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.14% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.43% 94.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 3 0.43% 95.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.14% 95.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.14% 95.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.14% 95.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.28% 96.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.28% 96.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.14% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.14% 97.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.14% 97.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.14% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.14% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.14% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.14% 98.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.14% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 1 0.14% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.14% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.14% 98.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.14% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation +system.physmem.totQLat 37727500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 172831250 # Sum of mem lat for all requests system.physmem.totBusLat 36640000 # Total cycles spent in databus access -system.physmem.totBankLat 113038750 # Total cycles spent in bank access -system.physmem.avgQLat 6503.00 # Average queueing delay per request -system.physmem.avgBankLat 15425.59 # Average bank access latency per request +system.physmem.totBankLat 98463750 # Total cycles spent in bank access +system.physmem.avgQLat 5148.40 # Average queueing delay per request +system.physmem.avgBankLat 13436.65 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26928.60 # Average memory access latency +system.physmem.avgMemAccLat 23585.05 # Average memory access latency system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s @@ -165,40 +235,55 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6132 # Number of row buffer hits during reads +system.physmem.readRowHits 6626 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.68 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19085060.11 # Average gap between requests -system.cpu.branchPred.lookups 53489671 # Number of BP lookups -system.cpu.branchPred.condPredicted 30685392 # Number of conditional branches predicted +system.physmem.avgGap 19092904.82 # Average gap between requests +system.membus.throughput 3352029 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4183 # Transaction distribution +system.membus.trans_dist::ReadResp 4183 # Transaction distribution +system.membus.trans_dist::ReadExReq 3145 # Transaction distribution +system.membus.trans_dist::ReadExResp 3145 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 14656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14656 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 468992 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 8784000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 68408750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 53489761 # Number of BP lookups +system.cpu.branchPred.condPredicted 30685482 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 32882438 # Number of BTB lookups system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 46.263416 # BTB Hit Percentage system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754610 # DTB read hits +system.cpu.dtb.read_hits 94754611 # DTB read hits system.cpu.dtb.read_misses 21 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754631 # DTB read accesses -system.cpu.dtb.write_hits 73521101 # DTB write hits +system.cpu.dtb.read_accesses 94754632 # DTB read accesses +system.cpu.dtb.write_hits 73521122 # DTB write hits system.cpu.dtb.write_misses 35 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73521136 # DTB write accesses -system.cpu.dtb.data_hits 168275711 # DTB hits +system.cpu.dtb.write_accesses 73521157 # DTB write accesses +system.cpu.dtb.data_hits 168275733 # DTB hits system.cpu.dtb.data_misses 56 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275767 # DTB accesses -system.cpu.itb.fetch_hits 48611339 # ITB hits +system.cpu.dtb.data_accesses 168275789 # DTB accesses +system.cpu.itb.fetch_hits 48611325 # ITB hits system.cpu.itb.fetch_misses 44520 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 48655859 # ITB accesses +system.cpu.itb.fetch_accesses 48655845 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,18 +297,18 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 279710746 # number of cpu cycles simulated +system.cpu.numCycles 279825758 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 280386586 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 24259255 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 439722445 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 119631956 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 100484559 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.floatRegFileAccesses 219828437 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 100484572 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 168485322 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken). @@ -234,12 +319,12 @@ system.cpu.execution_unit.executions 205475782 # Nu system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 279400786 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 279401420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7707 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13404116 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 266306630 # Number of cycles cpu stages are processed. -system.cpu.activity 95.207865 # Percentage of cycles cpu is active +system.cpu.timesIdled 7883 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13519017 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 266306741 # Number of cycles cpu stages are processed. +system.cpu.activity 95.168773 # Percentage of cycles cpu is active system.cpu.comLoads 94754489 # Number of Load instructions committed system.cpu.comStores 73520729 # Number of Store instructions committed system.cpu.comBranches 44587532 # Number of Branches instructions committed @@ -251,124 +336,144 @@ system.cpu.committedInsts 398664595 # Nu system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total) -system.cpu.cpi 0.701619 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.701908 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.701619 # CPI: Total CPI of All Threads -system.cpu.ipc 1.425275 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.701908 # CPI: Total CPI of All Threads +system.cpu.ipc 1.424689 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.425275 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 77963056 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 201747690 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 72.127257 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 107059011 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 172651735 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 61.725099 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 102495582 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 177215164 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 63.356581 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 180966170 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 98744576 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 35.302389 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 90242832 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 189467914 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 67.737088 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 1.424689 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 78078009 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 201747749 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 72.097633 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 107174029 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 61.699727 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 102610556 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 177215202 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 63.330554 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 181081179 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 98744579 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 35.287880 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 90357849 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 189467909 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 67.709245 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1975 # number of replacements -system.cpu.icache.tagsinuse 1831.214739 # Cycle average of tags in use -system.cpu.icache.total_refs 48606831 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1830.982662 # Cycle average of tags in use +system.cpu.icache.total_refs 48606794 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12453.710223 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 12453.700743 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1831.214739 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.894148 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.894148 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 48606831 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 48606831 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 48606831 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 48606831 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 48606831 # number of overall hits -system.cpu.icache.overall_hits::total 48606831 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4508 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4508 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4508 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4508 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4508 # number of overall misses -system.cpu.icache.overall_misses::total 4508 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 205410000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 205410000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 205410000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 205410000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 205410000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 205410000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 48611339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 48611339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 48611339 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 48611339 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 48611339 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 48611339 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1830.982662 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894035 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894035 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 48606794 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 48606794 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 48606794 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 48606794 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 48606794 # number of overall hits +system.cpu.icache.overall_hits::total 48606794 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses +system.cpu.icache.overall_misses::total 4531 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 268165000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 268165000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 268165000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 268165000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 268165000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 268165000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 48611325 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 48611325 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 48611325 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 48611325 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 48611325 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 48611325 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45565.661047 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45565.661047 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45565.661047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45565.661047 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45565.661047 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 206 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59184.506731 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59184.506731 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59184.506731 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59184.506731 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 326 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 68.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 108.666667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 605 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 605 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 605 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 605 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 605 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 605 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 628 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 628 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 628 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 628 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 628 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179905000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 179905000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179905000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 179905000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179905000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 179905000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234852500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 234852500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234852500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 234852500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234852500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 234852500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 46094.030233 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 46094.030233 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 46094.030233 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 46094.030233 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60172.303356 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60172.303356 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 3981449 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7806 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 16759 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 249792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 557056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 5854500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6228499 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 3907.659379 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 3906.975758 # Cycle average of tags in use system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 370.655862 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 2909.305713 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 627.697804 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011312 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.088785 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.019156 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.119252 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 370.554458 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 2908.829780 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 627.591520 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.119231 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -393,17 +498,17 @@ system.cpu.l2cache.demand_misses::total 7328 # nu system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 170516000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45771500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 216287500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 159323000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 159323000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 170516000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 205094500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 375610500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 170516000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 205094500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 375610500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 225463500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 58932500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 284396000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 213301500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 213301500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 225463500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 272234000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 497697500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 225463500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 272234000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 497697500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses) @@ -428,17 +533,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.909745 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50763.917833 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55547.936893 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51706.311260 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50659.141494 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50659.141494 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51256.891376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50763.917833 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51674.099269 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51256.891376 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67122.208991 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71520.024272 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67988.524982 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67822.416534 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67822.416534 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67917.235262 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67917.235262 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -458,17 +563,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7328 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128894552 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 35549355 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 164443907 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 120757665 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 120757665 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128894552 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 156307020 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 285201572 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128894552 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 156307020 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 285201572 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183879500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 48740750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 232620250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 174684500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 174684500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183879500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 223425250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 407304750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183879500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 223425250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 407304750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses @@ -480,51 +585,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38372.894314 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43142.421117 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39312.432943 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38396.713831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38396.713831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38372.894314 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39381.965231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38919.428493 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54742.334028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59151.395631 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55610.865408 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55543.561208 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55543.561208 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 764 # number of replacements -system.cpu.dcache.tagsinuse 3285.521075 # Cycle average of tags in use -system.cpu.dcache.total_refs 168254397 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3284.992544 # Cycle average of tags in use +system.cpu.dcache.total_refs 168254254 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 40523.698699 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40523.664258 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3285.521075 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.802129 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.802129 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 94753186 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753186 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501211 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501211 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168254397 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168254397 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168254397 # number of overall hits -system.cpu.dcache.overall_hits::total 168254397 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1303 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1303 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19518 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19518 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 20821 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20821 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 20821 # number of overall misses -system.cpu.dcache.overall_misses::total 20821 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65740000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65740000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 753340000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 753340000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 819080000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 819080000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 819080000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 819080000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 3284.992544 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.802000 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.802000 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501073 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501073 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168254254 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168254254 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168254254 # number of overall hits +system.cpu.dcache.overall_hits::total 168254254 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19656 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19656 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 20964 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20964 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 20964 # number of overall misses +system.cpu.dcache.overall_misses::total 20964 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84017000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84017000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1065172500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1065172500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1149189500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1149189500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1149189500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1149189500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) @@ -535,38 +640,38 @@ system.cpu.dcache.overall_accesses::cpu.data 168275218 system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000265 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000124 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000124 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000124 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000124 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50452.801228 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50452.801228 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38597.192335 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38597.192335 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39339.128764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39339.128764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39339.128764 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18390 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000267 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000267 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64233.180428 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 64233.180428 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54190.705128 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54190.705128 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54817.282007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54817.282007 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 28818 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 537 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 562 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.245810 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.277580 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 649 # number of writebacks system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 353 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 353 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16316 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16316 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16669 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16669 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16669 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16669 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16454 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16454 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 16812 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 16812 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 16812 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 16812 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses @@ -575,14 +680,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4152 system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 48200500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 48200500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 163094000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 163094000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 211294500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 211294500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211294500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 211294500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61415001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 61415001 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 217011500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 217011500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278426501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 278426501 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278426501 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 278426501 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -591,14 +696,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50737.368421 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50737.368421 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50935.040600 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50935.040600 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64647.369474 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64647.369474 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67773.735166 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67773.735166 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index d33a7960b..73956e98a 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.077334 # Number of seconds simulated -sim_ticks 77333664500 # Number of ticks simulated -final_tick 77333664500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.077363 # Number of seconds simulated +sim_ticks 77363103500 # Number of ticks simulated +final_tick 77363103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71983 # Simulator instruction rate (inst/s) -host_op_rate 71983 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14821773 # Simulator tick rate (ticks/s) -host_mem_usage 278592 # Number of bytes of host memory used -host_seconds 5217.57 # Real time elapsed on the host +host_inst_rate 219490 # Simulator instruction rate (inst/s) +host_op_rate 219490 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45211856 # Simulator tick rate (ticks/s) +host_mem_usage 233160 # Number of bytes of host memory used +host_seconds 1711.12 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255552 # Number of bytes read from this memory -system.physmem.bytes_read::total 476672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221120 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3455 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3993 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7448 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2859298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3304538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6163836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2859298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2859298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2859298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3304538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6163836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7448 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 220864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory +system.physmem.bytes_read::total 476224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 220864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 220864 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7441 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2854901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3300798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6155699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2854901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2854901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2854901 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3300798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6155699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7441 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7448 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 476672 # Total number of bytes read from memory +system.physmem.cpureqs 7441 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 476224 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 476672 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 476224 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 449 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 474 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 462 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 533 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 518 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 418 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 475 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 425 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 654 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 599 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 455 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 516 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 524 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 435 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 405 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 305 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 543 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 453 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 379 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 77333596000 # Total gap between requests +system.physmem.totGap 77363015000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7448 # Categorize read packet sizes +system.physmem.readPktSize::6 7441 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,13 +85,13 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2084 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4419 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -149,14 +149,81 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 53843750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 206982500 # Sum of mem lat for all requests -system.physmem.totBusLat 37240000 # Total cycles spent in databus access -system.physmem.totBankLat 115898750 # Total cycles spent in bank access -system.physmem.avgQLat 7229.29 # Average queueing delay per request -system.physmem.avgBankLat 15561.06 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 761 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 617.293035 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 239.548208 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1200.351847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 242 31.80% 31.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 107 14.06% 45.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 65 8.54% 54.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 58 7.62% 62.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 31 4.07% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 22 2.89% 68.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 22 2.89% 71.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 17 2.23% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 13 1.71% 75.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 18 2.37% 78.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 4 0.53% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 12 1.58% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 9 1.18% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 10 1.31% 82.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.66% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.66% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 18 2.37% 86.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 3 0.39% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 7 0.92% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 4 0.53% 90.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.39% 90.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 5 0.66% 91.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 7 0.92% 92.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.39% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.39% 94.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 3 0.39% 94.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.13% 95.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.13% 95.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 3 0.39% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.13% 96.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.26% 96.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.13% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.13% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.13% 98.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 7 0.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 761 # Bytes accessed per row activation +system.physmem.totQLat 39473750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 177700000 # Sum of mem lat for all requests +system.physmem.totBusLat 37205000 # Total cycles spent in databus access +system.physmem.totBankLat 101021250 # Total cycles spent in bank access +system.physmem.avgQLat 5304.90 # Average queueing delay per request +system.physmem.avgBankLat 13576.30 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27790.35 # Average memory access latency +system.physmem.avgMemAccLat 23881.20 # Average memory access latency system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s @@ -165,40 +232,55 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6188 # Number of row buffer hits during reads +system.physmem.readRowHits 6680 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads +system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10383135.88 # Average gap between requests -system.cpu.branchPred.lookups 50250164 # Number of BP lookups -system.cpu.branchPred.condPredicted 29237478 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1200857 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25926393 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23227731 # Number of BTB hits +system.physmem.avgGap 10396857.28 # Average gap between requests +system.membus.throughput 6155699 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4309 # Transaction distribution +system.membus.trans_dist::ReadResp 4309 # Transaction distribution +system.membus.trans_dist::ReadExReq 3132 # Transaction distribution +system.membus.trans_dist::ReadExResp 3132 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 14882 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14882 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476224 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 476224 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 476224 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 9093000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 69496500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.branchPred.lookups 50225543 # Number of BP lookups +system.cpu.branchPred.condPredicted 29217666 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1195897 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 25687498 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23216118 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.591063 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9011908 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1071 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 90.379055 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9009525 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1024 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 101791407 # DTB read hits -system.cpu.dtb.read_misses 78057 # DTB read misses +system.cpu.dtb.read_hits 101778798 # DTB read hits +system.cpu.dtb.read_misses 78056 # DTB read misses system.cpu.dtb.read_acv 48605 # DTB read access violations -system.cpu.dtb.read_accesses 101869464 # DTB read accesses -system.cpu.dtb.write_hits 78427886 # DTB write hits -system.cpu.dtb.write_misses 1487 # DTB write misses -system.cpu.dtb.write_acv 4 # DTB write access violations -system.cpu.dtb.write_accesses 78429373 # DTB write accesses -system.cpu.dtb.data_hits 180219293 # DTB hits -system.cpu.dtb.data_misses 79544 # DTB misses -system.cpu.dtb.data_acv 48609 # DTB access violations -system.cpu.dtb.data_accesses 180298837 # DTB accesses -system.cpu.itb.fetch_hits 50219856 # ITB hits -system.cpu.itb.fetch_misses 371 # ITB misses +system.cpu.dtb.read_accesses 101856854 # DTB read accesses +system.cpu.dtb.write_hits 78401927 # DTB write hits +system.cpu.dtb.write_misses 1498 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 78403425 # DTB write accesses +system.cpu.dtb.data_hits 180180725 # DTB hits +system.cpu.dtb.data_misses 79554 # DTB misses +system.cpu.dtb.data_acv 48607 # DTB access violations +system.cpu.dtb.data_accesses 180260279 # DTB accesses +system.cpu.itb.fetch_hits 50199009 # ITB hits +system.cpu.itb.fetch_misses 367 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 50220227 # ITB accesses +system.cpu.itb.fetch_accesses 50199376 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,139 +294,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 154667331 # number of cpu cycles simulated +system.cpu.numCycles 154726209 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 51106135 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 448668997 # Number of instructions fetch has processed -system.cpu.fetch.Branches 50250164 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 78764976 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 19721558 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 50219856 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 154473494 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 51083952 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 448497930 # Number of instructions fetch has processed +system.cpu.fetch.Branches 50225543 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 32225643 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 78739470 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6093368 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 19754761 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 10148 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 50199009 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 408107 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 154447023 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.903895 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.325218 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 75708518 49.01% 49.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11737510 7.60% 67.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7816086 5.06% 72.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5610591 3.63% 75.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1829118 1.18% 77.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35257808 22.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 75707553 49.02% 49.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4276532 2.77% 51.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6874422 4.45% 56.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5367897 3.48% 59.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11734775 7.60% 67.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 7804305 5.05% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5608156 3.63% 76.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1827762 1.18% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35245621 22.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154473494 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 56459568 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15066335 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74129389 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9471000 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4301 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 444763316 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 59590781 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4877606 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 403368 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 75043533 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9691219 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 440325289 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19776 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8008631 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 287258502 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 578891140 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 306269617 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 272621523 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 154447023 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.324609 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.898655 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 56435005 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 15098519 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74108370 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3950827 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4854302 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9469599 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4266 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 444616188 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 12118 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4854302 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 59563357 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4893725 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 414604 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 75021983 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 9699052 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 440177556 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 167 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 18387 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8017745 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 287187239 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 578692114 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 306192880 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 272499234 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27726173 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 27858969 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 408090089 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 966819 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 32383171 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154473494 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27654910 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 36841 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 27864767 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104645789 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80545124 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 8910343 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 6399312 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 408008914 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 401637302 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 964402 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 32300806 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15167317 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 71 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154447023 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.600486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.995525 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 28241556 18.28% 18.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 25850500 16.73% 35.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25557992 16.55% 51.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 24263581 15.71% 67.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 21289314 13.78% 81.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8473784 5.49% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28234595 18.28% 18.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 25848670 16.74% 35.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25579083 16.56% 51.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 24239826 15.69% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 21261159 13.77% 81.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15485386 10.03% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8478015 5.49% 96.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3990980 2.58% 99.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1329309 0.86% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154473494 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154447023 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 34111 0.29% 0.29% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 34190 0.29% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 56920 0.48% 0.77% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 5994 0.05% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 5359 0.05% 0.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 1948290 16.45% 17.32% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1748478 14.77% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5072340 42.83% 74.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 57000 0.48% 0.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 5570 0.05% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 1934681 16.39% 17.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1747492 14.80% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.05% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5061407 42.87% 74.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2960127 25.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 155713730 38.76% 38.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 155697269 38.77% 38.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2126268 0.53% 39.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7493329 1.87% 49.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2792591 0.70% 50.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16555292 4.12% 54.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1575667 0.39% 54.54% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 32795718 8.17% 47.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7492895 1.87% 49.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2793275 0.70% 50.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16555197 4.12% 54.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1576539 0.39% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued @@ -366,84 +448,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.54% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 103367730 25.73% 80.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 103353833 25.73% 80.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 79212727 19.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued -system.cpu.iq.rate 2.597191 # Inst issue rate -system.cpu.iq.fu_busy_cnt 11841749 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 633918873 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 260111128 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 234694703 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 241419357 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 15066518 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 401637302 # Type of FU issued +system.cpu.iq.rate 2.595794 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11805850 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.029394 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 633814426 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 260039391 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 234669938 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 336677453 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 180319624 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 161314335 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 241373993 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 172035578 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15061229 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 9904869 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112431 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 48929 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7055780 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 9891302 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 112335 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 49025 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7024395 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 260879 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3733 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2513893 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 367538 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 432875839 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130047 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 95 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 48929 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 945508 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101918111 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4854302 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2516728 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 369298 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 432783708 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 121887 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104645789 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80545124 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 286 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 93 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 98 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 49025 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 940065 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 405593 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1345658 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 398139116 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101905490 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3498186 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24785465 # number of nop insts executed -system.cpu.iew.exec_refs 180347521 # number of memory reference insts executed -system.cpu.iew.exec_branches 46544583 # Number of branches executed -system.cpu.iew.exec_stores 78429410 # Number of stores executed -system.cpu.iew.exec_rate 2.574493 # Inst execution rate -system.cpu.iew.wb_sent 396666493 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 396036592 # cumulative count of insts written-back -system.cpu.iew.wb_producers 193534239 # num instructions producing a value -system.cpu.iew.wb_consumers 271064266 # num instructions consuming a value +system.cpu.iew.exec_nop 24774508 # number of nop insts executed +system.cpu.iew.exec_refs 180308945 # number of memory reference insts executed +system.cpu.iew.exec_branches 46542252 # Number of branches executed +system.cpu.iew.exec_stores 78403455 # Number of stores executed +system.cpu.iew.exec_rate 2.573185 # Inst execution rate +system.cpu.iew.wb_sent 396614980 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 395984273 # cumulative count of insts written-back +system.cpu.iew.wb_producers 193530512 # num instructions producing a value +system.cpu.iew.wb_consumers 271082574 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back +system.cpu.iew.wb_rate 2.559258 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.713917 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34241399 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 34145749 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149606507 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1191710 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149592721 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.665000 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.996623 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 55299800 36.96% 36.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22506363 15.04% 52.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13038979 8.72% 60.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8182423 5.47% 73.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 5460459 3.65% 77.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3276423 2.19% 83.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 25215068 16.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 55286060 36.96% 36.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22516991 15.05% 52.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13020116 8.70% 60.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11469174 7.67% 68.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8183204 5.47% 73.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 5453733 3.65% 77.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5164454 3.45% 80.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3280279 2.19% 83.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 25218710 16.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149606507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 149592721 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -454,192 +536,212 @@ system.cpu.commit.branches 44587533 # Nu system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. system.cpu.commit.int_insts 316365839 # Number of committed integer instructions. system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.bw_lim_events 25215068 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 25218710 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 557294444 # The number of ROB reads -system.cpu.rob.rob_writes 870687583 # The number of ROB writes -system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 193837 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 557181366 # The number of ROB reads +system.cpu.rob.rob_writes 870483842 # The number of ROB writes +system.cpu.timesIdled 3633 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 279186 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated -system.cpu.cpi 0.411815 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.411815 # CPI: Total CPI of All Threads -system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 398027050 # number of integer regfile reads -system.cpu.int_regfile_writes 170092717 # number of integer regfile writes -system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads -system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes +system.cpu.cpi 0.411972 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.411972 # CPI: Total CPI of All Threads +system.cpu.ipc 2.427351 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.427351 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 397971851 # number of integer regfile reads +system.cpu.int_regfile_writes 170072905 # number of integer regfile writes +system.cpu.fp_regfile_reads 156478965 # number of floating regfile reads +system.cpu.fp_regfile_writes 104018276 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 2144 # number of replacements -system.cpu.icache.tagsinuse 1832.992784 # Cycle average of tags in use -system.cpu.icache.total_refs 50214379 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12334.654630 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 7367647 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3191 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3191 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8148 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9009 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 17157 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 260736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 569984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 569984 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 5108000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 6111000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6265500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 2147 # number of replacements +system.cpu.icache.tagsinuse 1831.625379 # Cycle average of tags in use +system.cpu.icache.total_refs 50193388 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4074 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12320.419244 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1832.992784 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 50214379 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 50214379 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 50214379 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 50214379 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 50214379 # number of overall hits -system.cpu.icache.overall_hits::total 50214379 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5477 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5477 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5477 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses -system.cpu.icache.overall_misses::total 5477 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 242149500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 242149500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 242149500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 242149500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 242149500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 242149500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 50219856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 50219856 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 50219856 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 50219856 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 50219856 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 50219856 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000109 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000109 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000109 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44212.068651 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44212.068651 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44212.068651 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44212.068651 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44212.068651 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44212.068651 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1831.625379 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.894348 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.894348 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 50193388 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 50193388 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 50193388 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 50193388 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 50193388 # number of overall hits +system.cpu.icache.overall_hits::total 50193388 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5621 # number of overall misses +system.cpu.icache.overall_misses::total 5621 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 317313500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 317313500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 317313500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 317313500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 317313500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 317313500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 50199009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 50199009 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 50199009 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 50199009 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 50199009 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 50199009 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000112 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000112 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000112 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000112 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000112 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000112 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56451.432130 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56451.432130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56451.432130 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56451.432130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56451.432130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56451.432130 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 403 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 138.400000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.571429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1406 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1406 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1406 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1406 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1406 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1406 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4071 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4071 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4071 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4071 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4071 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 185114500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 185114500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 185114500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 185114500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 185114500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 185114500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1547 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1547 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1547 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1547 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1547 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1547 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4074 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4074 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4074 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4074 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4074 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4074 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 240569000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 240569000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 240569000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 240569000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 240569000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 240569000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45471.505773 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45471.505773 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45471.505773 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 45471.505773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45471.505773 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 45471.505773 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59049.828179 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59049.828179 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59049.828179 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 59049.828179 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59049.828179 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 59049.828179 # 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Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 661.628139 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.011369 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.090898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.020191 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.122458 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 616 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 129 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 745 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 657 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 657 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 616 # 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number of overall hits -system.cpu.dcache.overall_hits::total 159960711 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1811 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1811 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19769 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19769 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21580 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21580 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21580 # number of overall misses -system.cpu.dcache.overall_misses::total 21580 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89987500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89987500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 779566110 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 779566110 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 869553610 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 869553610 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 869553610 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 869553610 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86461562 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86461562 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 159952386 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 159952386 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 159952386 # number of overall hits +system.cpu.dcache.overall_hits::total 159952386 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1809 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1809 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19942 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19942 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21751 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21751 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21751 # number of overall misses +system.cpu.dcache.overall_misses::total 21751 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 111333000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 111333000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1028184585 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1028184585 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1139517585 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1139517585 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1139517585 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1139517585 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86453408 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86453408 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 159982291 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 159982291 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 159982291 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 159982291 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 159974137 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 159974137 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 159974137 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 159974137 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000135 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000135 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000135 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000135 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49689.398123 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49689.398123 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39433.765491 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39433.765491 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40294.421223 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40294.421223 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40294.421223 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40294.421223 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 28157 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61543.946932 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61543.946932 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51558.749624 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51558.749624 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52389.204404 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52389.204404 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52389.204404 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52389.204404 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 37387 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 631 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 654 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.622821 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.166667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 657 # number of writebacks -system.cpu.dcache.writebacks::total 657 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 821 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 821 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16577 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16577 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17398 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17398 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17398 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17398 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 990 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 990 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3192 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3192 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4182 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4182 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4182 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 53865000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 53865000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167256500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 167256500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 221121500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 221121500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 221121500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 221121500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 655 # number of writebacks +system.cpu.dcache.writebacks::total 655 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 823 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 823 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16751 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16751 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17574 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17574 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17574 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17574 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4177 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4177 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4177 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4177 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66792500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 66792500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 216966500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 216966500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 283759000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 283759000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 283759000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 283759000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -796,14 +898,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000026 system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54409.090909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54409.090909 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67740.872211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67740.872211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67993.262300 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67993.262300 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index a976b0a99..721e957fa 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2294613 # Simulator instruction rate (inst/s) -host_op_rate 2294613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1147307033 # Simulator tick rate (ticks/s) -host_mem_usage 269948 # Number of bytes of host memory used -host_seconds 173.74 # Real time elapsed on the host +host_inst_rate 1715563 # Simulator instruction rate (inst/s) +host_op_rate 1715563 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 857781835 # Simulator tick rate (ticks/s) +host_mem_usage 222488 # Number of bytes of host memory used +host_seconds 232.38 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 2470028804 # Wr system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13793364824 # Throughput (bytes/s) +system.membus.data_through_bus 2749464673 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 39d4d27ed..ff5b38f2f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu sim_ticks 567335093000 # Number of ticks simulated final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 853902 # Simulator instruction rate (inst/s) -host_op_rate 853902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1215178011 # Simulator tick rate (ticks/s) -host_mem_usage 278532 # Number of bytes of host memory used -host_seconds 466.87 # Real time elapsed on the host +host_inst_rate 1715092 # Simulator instruction rate (inst/s) +host_op_rate 1715091 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2440727076 # Simulator tick rate (ticks/s) +host_mem_usage 230984 # Number of bytes of host memory used +host_seconds 232.45 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 361550 # In system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 809285 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4032 # Transaction distribution +system.membus.trans_dist::ReadResp 4032 # Transaction distribution +system.membus.trans_dist::ReadExReq 3142 # Transaction distribution +system.membus.trans_dist::ReadExResp 3142 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14348 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 459136 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -396,5 +411,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 955936 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 16299 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 235072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 542336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 93b8d4fc1..3fe39b26c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.068258 # Number of seconds simulated -sim_ticks 68258363000 # Number of ticks simulated -final_tick 68258363000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.068340 # Number of seconds simulated +sim_ticks 68340072000 # Number of ticks simulated +final_tick 68340072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73419 # Simulator instruction rate (inst/s) -host_op_rate 93863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18354583 # Simulator tick rate (ticks/s) -host_mem_usage 296524 # Number of bytes of host memory used -host_seconds 3718.87 # Real time elapsed on the host +host_inst_rate 97727 # Simulator instruction rate (inst/s) +host_op_rate 124939 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24460648 # Simulator tick rate (ticks/s) +host_mem_usage 254748 # Number of bytes of host memory used +host_seconds 2793.88 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 272192 # Number of bytes read from this memory -system.physmem.bytes_read::total 465984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4253 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7281 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2839095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3987673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6826768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2839095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2839095 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2839095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3987673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6826768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7281 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 193856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272320 # Number of bytes read from this memory +system.physmem.bytes_read::total 466176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 193856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193856 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4255 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7284 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2836637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3984778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6821415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2836637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2836637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2836637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3984778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6821415 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7284 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 7284 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 465984 # Total number of bytes read from memory +system.physmem.cpureqs 7289 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 466176 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 465984 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 466176 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 412 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 509 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 487 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 544 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 590 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 432 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 417 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 450 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 416 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 803 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 607 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 525 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 354 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 414 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 530 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 686 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 68258164000 # Total gap between requests +system.physmem.totGap 68339875000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 7281 # Categorize read packet sizes +system.physmem.readPktSize::6 7284 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4420 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 561 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,36 +149,119 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 45271500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 191126500 # Sum of mem lat for all requests -system.physmem.totBusLat 36405000 # Total cycles spent in databus access -system.physmem.totBankLat 109450000 # Total cycles spent in bank access -system.physmem.avgQLat 6217.76 # Average queueing delay per request -system.physmem.avgBankLat 15032.28 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 639.642957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 236.501213 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1328.325684 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 231 32.22% 32.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 96 13.39% 45.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 63 8.79% 54.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 56 7.81% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 30 4.18% 66.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 30 4.18% 70.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 16 2.23% 72.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 21 2.93% 75.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 13 1.81% 77.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 17 2.37% 79.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 8 1.12% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 12 1.67% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.42% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 9 1.26% 84.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 5 0.70% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 7 0.98% 86.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 0.70% 86.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 5 0.70% 87.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.56% 88.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.28% 88.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 4 0.56% 89.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3 0.42% 89.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 4 0.56% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.56% 90.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 2 0.28% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.14% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.28% 93.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.14% 97.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.14% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation +system.physmem.totQLat 39275000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 171092500 # Sum of mem lat for all requests +system.physmem.totBusLat 36420000 # Total cycles spent in databus access +system.physmem.totBankLat 95397500 # Total cycles spent in bank access +system.physmem.avgQLat 5391.95 # Average queueing delay per request +system.physmem.avgBankLat 13096.86 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26250.03 # Average memory access latency -system.physmem.avgRdBW 6.83 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 23488.81 # Average memory access latency +system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 6.83 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 6071 # Number of row buffer hits during reads +system.physmem.readRowHits 6567 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9374833.68 # Average gap between requests -system.cpu.branchPred.lookups 35375534 # Number of BP lookups -system.cpu.branchPred.condPredicted 21203624 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1636565 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18693932 # Number of BTB lookups -system.cpu.branchPred.BTBHits 16765511 # Number of BTB hits +system.physmem.avgGap 9382190.42 # Average gap between requests +system.membus.throughput 6821415 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4461 # Transaction distribution +system.membus.trans_dist::ReadResp 4461 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 2823 # Transaction distribution +system.membus.trans_dist::ReadExResp 2823 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 14578 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 14578 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466176 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 466176 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 466176 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 8863500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 67994996 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.branchPred.lookups 35386289 # Number of BP lookups +system.cpu.branchPred.condPredicted 21204879 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1638532 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 19153921 # Number of BTB lookups +system.cpu.branchPred.BTBHits 16759106 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.684241 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6786649 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 8328 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.496999 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6781793 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 8488 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -222,100 +305,100 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 136516727 # number of cpu cycles simulated +system.cpu.numCycles 136680145 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 38896982 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 317376259 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35375534 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23552160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 70779245 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6771648 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 21491054 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1891 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 37519444 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 509386 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 136293047 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.985311 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.454516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 38911514 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 317585001 # Number of instructions fetch has processed +system.cpu.fetch.Branches 35386289 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23540899 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 70801219 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6795871 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 21500027 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 100 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1484 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 37522622 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 503492 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 136360129 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.984944 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454705 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 66138904 48.53% 48.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 6767660 4.97% 53.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5699163 4.18% 57.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6081886 4.46% 62.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4905828 3.60% 65.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4088301 3.00% 68.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3176914 2.33% 71.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4135950 3.03% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35298441 25.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 66188924 48.54% 48.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 6771554 4.97% 53.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5692762 4.17% 57.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6083969 4.46% 62.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4907326 3.60% 65.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4077145 2.99% 68.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3184432 2.34% 71.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4135342 3.03% 74.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35318675 25.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 136293047 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259130 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.324816 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45396979 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16650013 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 66644263 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2546649 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5055143 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7329146 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 69002 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 400901285 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 213083 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5055143 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50932623 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1928706 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 309700 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 63595700 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14471175 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 393334802 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 54 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1658050 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10199893 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1072 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 431829381 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2328856465 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1256465206 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1072391259 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 136360129 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258899 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.323564 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45414780 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16659439 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 66663560 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2545187 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5077163 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7331349 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 68935 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401047467 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 212517 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5077163 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50947779 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1931381 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 327570 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 63615860 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14460376 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 393522571 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1660698 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10177766 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1066 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 432139045 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2330040462 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1257112117 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1072928345 # Number of floating rename lookups system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 47263188 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11836 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11835 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 36477776 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 103434690 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 91236939 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4267637 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5260584 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 383959282 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 373920129 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1206190 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 34165918 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 85628063 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 136293047 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.743501 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.023111 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 47572852 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11802 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11801 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 36468583 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 103474945 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 91276854 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4259608 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5261316 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 384098955 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22768 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 373971213 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1208914 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 34303040 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 86231470 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 136360129 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.742526 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.023578 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24835944 18.22% 18.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19923821 14.62% 32.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20538519 15.07% 47.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18169219 13.33% 61.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24028277 17.63% 78.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15701712 11.52% 90.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8800214 6.46% 96.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3374067 2.48% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 921274 0.68% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24894566 18.26% 18.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19912259 14.60% 32.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20562905 15.08% 47.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18156426 13.32% 61.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24028186 17.62% 78.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15708589 11.52% 90.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8792760 6.45% 96.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3383887 2.48% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 920551 0.68% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 136293047 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 136360129 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8902 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4689 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8941 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -334,127 +417,127 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 46241 0.26% 0.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 46063 0.26% 0.34% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7650 0.04% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 432 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7630 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.38% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 190629 1.08% 1.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 3972 0.02% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241372 1.36% 2.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 190949 1.08% 1.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 4204 0.02% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 241086 1.36% 2.84% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9278872 52.34% 55.18% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7944742 44.82% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9286535 52.36% 55.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 7946359 44.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 126315653 33.78% 33.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2175866 0.58% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6776888 1.81% 36.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 126344065 33.78% 33.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2175771 0.58% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6778681 1.81% 36.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8468895 2.26% 38.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3427953 0.92% 39.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1595639 0.43% 39.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20851093 5.58% 45.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7171347 1.92% 47.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7126740 1.91% 49.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101555976 27.16% 76.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88278790 23.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8473226 2.27% 38.44% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3428816 0.92% 39.36% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1595959 0.43% 39.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20861053 5.58% 45.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172627 1.92% 47.28% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127553 1.91% 49.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101561380 27.16% 76.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88276793 23.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 373920129 # Type of FU issued -system.cpu.iq.rate 2.739006 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17727503 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047410 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 653684952 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 287885544 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 249920404 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 249382046 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 130276634 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118031995 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 263048449 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 128599183 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11100195 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 373971213 # Type of FU issued +system.cpu.iq.rate 2.736105 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17736902 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047429 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653872242 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 288125780 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 249960786 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 249376129 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 130313231 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118044740 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 263109864 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 128598251 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 11095244 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 8785942 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 109607 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14276 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8861356 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 8826197 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 108953 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14410 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8901271 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 182774 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1441 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 178209 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1806 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5055143 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 284926 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 36749 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 383983637 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 873190 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 103434690 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 91236939 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 337 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14276 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1271835 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 367005 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1638840 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 369984044 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100253903 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3936085 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 5077163 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 281172 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 37033 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 384123288 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 853132 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 103474945 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 91276854 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11734 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 343 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 352 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14410 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1275078 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 370888 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1645966 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 370028321 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100269572 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3942892 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1567 # number of nop insts executed -system.cpu.iew.exec_refs 187478745 # number of memory reference insts executed -system.cpu.iew.exec_branches 32002404 # Number of branches executed -system.cpu.iew.exec_stores 87224842 # Number of stores executed -system.cpu.iew.exec_rate 2.710174 # Inst execution rate -system.cpu.iew.wb_sent 368608393 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 367952399 # cumulative count of insts written-back -system.cpu.iew.wb_producers 182920147 # num instructions producing a value -system.cpu.iew.wb_consumers 363541669 # num instructions consuming a value +system.cpu.iew.exec_nop 1565 # number of nop insts executed +system.cpu.iew.exec_refs 187470029 # number of memory reference insts executed +system.cpu.iew.exec_branches 32001457 # Number of branches executed +system.cpu.iew.exec_stores 87200457 # Number of stores executed +system.cpu.iew.exec_rate 2.707257 # Inst execution rate +system.cpu.iew.wb_sent 368660932 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 368005526 # cumulative count of insts written-back +system.cpu.iew.wb_producers 182984682 # num instructions producing a value +system.cpu.iew.wb_consumers 363667286 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.695292 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.503161 # average fanout of values written-back +system.cpu.iew.wb_rate 2.692458 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.503165 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 34918645 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 35058333 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1567905 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 131237904 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.659788 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.659697 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1569963 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 131282966 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.658875 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.659705 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 34480622 26.27% 26.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 28416799 21.65% 47.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13301568 10.14% 58.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11461353 8.73% 66.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13768973 10.49% 77.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7415781 5.65% 82.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3872079 2.95% 85.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3892036 2.97% 88.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14628693 11.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 34515611 26.29% 26.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 28430867 21.66% 47.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13310132 10.14% 58.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11454615 8.73% 66.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13758236 10.48% 77.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7411224 5.65% 82.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3878786 2.95% 85.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3899655 2.97% 88.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14623840 11.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 131237904 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 131282966 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037337 # Number of instructions committed system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -465,198 +548,220 @@ system.cpu.commit.branches 30563497 # Nu system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. system.cpu.commit.int_insts 279584611 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14628693 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14623840 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 500590394 # The number of ROB reads -system.cpu.rob.rob_writes 773026490 # The number of ROB writes -system.cpu.timesIdled 6380 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223680 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 500779997 # The number of ROB reads +system.cpu.rob.rob_writes 773327958 # The number of ROB writes +system.cpu.timesIdled 6728 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320016 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273036725 # Number of Instructions Simulated system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated -system.cpu.cpi 0.499994 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.499994 # CPI: Total CPI of All Threads -system.cpu.ipc 2.000024 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.000024 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1768667875 # number of integer regfile reads -system.cpu.int_regfile_writes 232756138 # number of integer regfile writes -system.cpu.fp_regfile_reads 188077365 # number of floating regfile reads -system.cpu.fp_regfile_writes 132460015 # number of floating regfile writes -system.cpu.misc_regfile_reads 566729148 # number of misc regfile reads +system.cpu.cpi 0.500593 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.500593 # CPI: Total CPI of All Threads +system.cpu.ipc 1.997633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.997633 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1768864956 # number of integer regfile reads +system.cpu.int_regfile_writes 232856502 # number of integer regfile writes +system.cpu.fp_regfile_reads 188105910 # number of floating regfile reads +system.cpu.fp_regfile_writes 132495512 # number of floating regfile writes +system.cpu.misc_regfile_reads 566780330 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.icache.replacements 13935 # number of replacements -system.cpu.icache.tagsinuse 1853.031974 # Cycle average of tags in use -system.cpu.icache.total_refs 37502330 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15827 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2369.516017 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 20129917 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17615 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17615 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2840 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31680 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10272 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 41952 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 1375168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1375168 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 512 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11790000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 23771988 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6938461 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 13951 # number of replacements +system.cpu.icache.tagsinuse 1844.969918 # Cycle average of tags in use +system.cpu.icache.total_refs 37505309 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15840 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2367.759407 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1853.031974 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.904801 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.904801 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37502330 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37502330 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37502330 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37502330 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37502330 # number of overall hits -system.cpu.icache.overall_hits::total 37502330 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 17113 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 17113 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 17113 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 17113 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 17113 # number of overall misses -system.cpu.icache.overall_misses::total 17113 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 362885498 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 362885498 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 362885498 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 362885498 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 362885498 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 362885498 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37519443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37519443 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37519443 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37519443 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37519443 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37519443 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000456 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000456 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000456 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000456 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000456 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000456 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21205.253199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21205.253199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21205.253199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21205.253199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21205.253199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21205.253199 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 563 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1844.969918 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.900864 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.900864 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37505309 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37505309 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37505309 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37505309 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37505309 # number of overall hits +system.cpu.icache.overall_hits::total 37505309 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 17311 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 17311 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 17311 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 17311 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 17311 # number of overall misses +system.cpu.icache.overall_misses::total 17311 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 438177497 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 438177497 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 438177497 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 438177497 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 438177497 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 438177497 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37522620 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37522620 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37522620 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37522620 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37522620 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37522620 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000461 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000461 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000461 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000461 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000461 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000461 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25312.084628 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25312.084628 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25312.084628 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25312.084628 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25312.084628 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 919 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 23 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.277778 # 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number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 53 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3028 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1456 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4484 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2797 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 2797 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3028 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 101531232 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 114750827 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 163127352 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 277878179 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 114750827 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 163127352 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 277878179 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191355 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.807543 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254382 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_hits::cpu.data 39 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 51 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3029 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1432 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4461 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2823 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2823 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4255 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7284 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4255 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7284 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168121750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 81472500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 249594250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 51504 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 51504 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 153947250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 153947250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168121750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235419750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 403541500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168121750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235419750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 403541500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.253365 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993959 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993959 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191355 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.921161 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.356196 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191355 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.921161 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.356196 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37896.574306 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42305.027473 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39328.043488 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36300.047193 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36300.047193 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37896.574306 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38355.831648 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38164.837110 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37896.574306 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38355.831648 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38164.837110 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994014 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356238 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191273 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922793 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356238 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55504.044239 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56894.203911 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55950.291414 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10300.800000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10300.800000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54533.209352 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54533.209352 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55504.044239 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55327.790834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55401.084569 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1423 # number of replacements -system.cpu.dcache.tagsinuse 3104.940004 # Cycle average of tags in use -system.cpu.dcache.total_refs 170839954 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4617 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37002.372536 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1417 # number of replacements +system.cpu.dcache.tagsinuse 3105.227160 # Cycle average of tags in use +system.cpu.dcache.total_refs 170865642 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4611 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37056.092388 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3104.940004 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.758042 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.758042 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 88786548 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88786548 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031492 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031492 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11005 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11005 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 3105.227160 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.758112 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.758112 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 88812489 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88812489 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031226 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031226 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11012 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11012 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 170818040 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 170818040 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 170818040 # number of overall hits -system.cpu.dcache.overall_hits::total 170818040 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4058 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4058 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21173 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21173 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 170843715 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 170843715 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 170843715 # number of overall hits +system.cpu.dcache.overall_hits::total 170843715 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3995 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3995 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 21439 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 21439 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 25231 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 25231 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 25231 # number of overall misses -system.cpu.dcache.overall_misses::total 25231 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177480000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177480000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 877819657 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 877819657 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 116000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1055299657 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1055299657 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1055299657 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1055299657 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 88790606 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 88790606 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 25434 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25434 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25434 # number of overall misses +system.cpu.dcache.overall_misses::total 25434 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 218203000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 218203000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1190820596 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1190820596 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 155000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1409023596 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1409023596 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1409023596 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1409023596 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88816484 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88816484 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11007 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11007 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11014 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11014 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 170843271 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 170843271 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 170843271 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 170843271 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 170869149 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 170869149 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 170869149 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 170869149 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43735.830458 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43735.830458 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389647 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389647 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41825.518489 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41825.518489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41825.518489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41825.518489 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 15191 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 833 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 436 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54619.023780 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54619.023780 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55544.596110 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55544.596110 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55399.213494 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55399.213494 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 24937 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1182 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 461 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.841743 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 64.076923 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.093275 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 90.923077 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks -system.cpu.dcache.writebacks::total 1043 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2254 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2254 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18357 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18357 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks +system.cpu.dcache.writebacks::total 1040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2223 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2223 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18595 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18595 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20611 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20611 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20611 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 20611 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1804 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1804 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2816 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2816 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4620 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4620 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4620 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4620 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86261000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 86261000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 138898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225159000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 225159000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225159000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 225159000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 20818 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 20818 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 20818 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 20818 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1772 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1772 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2844 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2844 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106478039 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 106478039 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191753000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 191753000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298231039 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 298231039 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298231039 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 298231039 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47816.518847 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47816.518847 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49324.573864 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49324.573864 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48735.714286 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48735.714286 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48735.714286 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48735.714286 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60089.186795 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60089.186795 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67423.699015 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67423.699015 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index b6c5c1209..590c33ff6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu sim_ticks 212344043000 # Number of ticks simulated final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1130367 # Simulator instruction rate (inst/s) -host_op_rate 1445119 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 879097302 # Simulator tick rate (ticks/s) -host_mem_usage 286212 # Number of bytes of host memory used -host_seconds 241.55 # Real time elapsed on the host +host_inst_rate 1381175 # Simulator instruction rate (inst/s) +host_op_rate 1765765 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1074152891 # Simulator tick rate (ticks/s) +host_mem_usage 241892 # Number of bytes of host memory used +host_seconds 197.69 # Real time elapsed on the host sim_insts 273037663 # Number of instructions simulated sim_ops 349065399 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1883960470 # Wr system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10715621794 # Throughput (bytes/s) +system.membus.data_through_bus 2275398455 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 2a42325c9..03f82082e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525834 # Nu sim_ticks 525834342000 # Number of ticks simulated final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 589682 # Simulator instruction rate (inst/s) -host_op_rate 753887 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1136891744 # Simulator tick rate (ticks/s) -host_mem_usage 294668 # Number of bytes of host memory used -host_seconds 462.52 # Real time elapsed on the host +host_inst_rate 442791 # Simulator instruction rate (inst/s) +host_op_rate 566092 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 853689730 # Simulator tick rate (ticks/s) +host_mem_usage 250392 # Number of bytes of host memory used +host_seconds 615.96 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 317545 # In system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 831532 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3976 # Transaction distribution +system.membus.trans_dist::ReadResp 3976 # Transaction distribution +system.membus.trans_dist::ReadExReq 2856 # Transaction distribution +system.membus.trans_dist::ReadExResp 2856 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 13664 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 13664 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 437248 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 437248 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -414,5 +429,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31206 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 41160 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 350464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 1349056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 201d8d939..c480587dc 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.626015 # Number of seconds simulated -sim_ticks 626014950000 # Number of ticks simulated -final_tick 626014950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.631301 # Number of seconds simulated +sim_ticks 631300530000 # Number of ticks simulated +final_tick 631300530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71515 # Simulator instruction rate (inst/s) -host_op_rate 71515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24557485 # Simulator tick rate (ticks/s) -host_mem_usage 282608 # Number of bytes of host memory used -host_seconds 25491.82 # Real time elapsed on the host +host_inst_rate 153163 # Simulator instruction rate (inst/s) +host_op_rate 153163 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53038574 # Simulator tick rate (ticks/s) +host_mem_usage 237176 # Number of bytes of host memory used +host_seconds 11902.67 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 175936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30295808 # Number of bytes read from this memory -system.physmem.bytes_read::total 30471744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 175936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30295296 # Number of bytes read from this memory +system.physmem.bytes_read::total 30472576 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2749 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 473372 # Number of read requests responded to by this memory -system.physmem.num_reads::total 476121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 473364 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476134 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 281041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48394704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48675745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 281041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 281041 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6840271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6840271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6840271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 281041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48394704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55516016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 476121 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 280817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47988707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48269524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 280817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 280817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6783001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6783001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6783001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 280817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 47988707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55052525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476134 # Total number of read requests seen system.physmem.writeReqs 66908 # Total number of write requests seen -system.physmem.cpureqs 543029 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30471744 # Total number of bytes read from memory +system.physmem.cpureqs 543042 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30472576 # Total number of bytes read from memory system.physmem.bytesWritten 4282112 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30471744 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30472576 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 95 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29662 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29647 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29658 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29696 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29714 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29813 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29790 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29697 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29781 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29859 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29815 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4149 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4110 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4214 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4228 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4213 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4166 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4191 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4205 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 29446 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29796 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29856 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29790 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29772 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29863 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29774 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29887 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29919 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29585 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29511 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29633 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4164 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4160 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4142 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4099 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4262 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4226 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4233 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4335 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4247 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4241 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4100 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4157 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 626014887500 # Total gap between requests +system.physmem.totGap 631300447500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 476121 # Categorize read packet sizes +system.physmem.readPktSize::6 476134 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,12 +92,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 66908 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 406557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 408382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,7 +124,7 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see @@ -147,7 +147,7 @@ system.physmem.wrQLenPdf::19 2909 # Wh system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -156,56 +156,150 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3500552500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 21508187500 # Sum of mem lat for all requests -system.physmem.totBusLat 2380155000 # Total cycles spent in databus access -system.physmem.totBankLat 15627480000 # Total cycles spent in bank access -system.physmem.avgQLat 7353.62 # Average queueing delay per request -system.physmem.avgBankLat 32828.70 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 166615 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 208.530564 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 137.079554 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 536.352711 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 52781 31.68% 31.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 42583 25.56% 57.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 39981 24.00% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 25354 15.22% 96.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 274 0.16% 96.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 129 0.08% 96.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 97 0.06% 96.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 83 0.05% 96.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 81 0.05% 96.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 95 0.06% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 108 0.06% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 114 0.07% 97.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 86 0.05% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 90 0.05% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 79 0.05% 97.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 79 0.05% 97.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 75 0.05% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 77 0.05% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 76 0.05% 97.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 81 0.05% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3443 2.07% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 36 0.02% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 3 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 4 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 586 0.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 166615 # Bytes accessed per row activation +system.physmem.totQLat 1512536000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14445141000 # Sum of mem lat for all requests +system.physmem.totBusLat 2380195000 # Total cycles spent in databus access +system.physmem.totBankLat 10552410000 # Total cycles spent in bank access +system.physmem.avgQLat 3177.34 # Average queueing delay per request +system.physmem.avgBankLat 22167.11 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45182.33 # Average memory access latency -system.physmem.avgRdBW 48.68 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.84 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.68 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.84 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 30344.45 # Average memory access latency +system.physmem.avgRdBW 48.27 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.27 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.78 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 11.00 # Average write queue length over time -system.physmem.readRowHits 143853 # Number of row buffer hits during reads -system.physmem.writeRowHits 46182 # Number of row buffer hits during writes -system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.02 # Row buffer hit rate for writes -system.physmem.avgGap 1152820.36 # Average gap between requests -system.cpu.branchPred.lookups 388875863 # Number of BP lookups -system.cpu.branchPred.condPredicted 256999007 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 25264722 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 310547770 # Number of BTB lookups -system.cpu.branchPred.BTBHits 257563099 # Number of BTB hits +system.physmem.avgRdQLen 0.02 # Average read queue length over time +system.physmem.avgWrQLen 10.99 # Average write queue length over time +system.physmem.readRowHits 326147 # Number of row buffer hits during reads +system.physmem.writeRowHits 50184 # Number of row buffer hits during writes +system.physmem.readRowHitRate 68.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.00 # Row buffer hit rate for writes +system.physmem.avgGap 1162526.01 # Average gap between requests +system.membus.throughput 55052525 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 409284 # Transaction distribution +system.membus.trans_dist::ReadResp 409284 # Transaction distribution +system.membus.trans_dist::Writeback 66908 # Transaction distribution +system.membus.trans_dist::ReadExReq 66850 # Transaction distribution +system.membus.trans_dist::ReadExResp 66850 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 1019176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1019176 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34754688 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 34754688 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34754688 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1238262500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4532735250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu.branchPred.lookups 388673605 # Number of BP lookups +system.cpu.branchPred.condPredicted 255878326 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 25733265 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 278525299 # Number of BTB lookups +system.cpu.branchPred.BTBHits 258256723 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.938319 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 56744188 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 6782 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.722896 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 57195432 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 6738 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 519038391 # DTB read hits -system.cpu.dtb.read_misses 606346 # DTB read misses +system.cpu.dtb.read_hits 521844087 # DTB read hits +system.cpu.dtb.read_misses 593644 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 519644737 # DTB read accesses -system.cpu.dtb.write_hits 282491025 # DTB write hits -system.cpu.dtb.write_misses 50159 # DTB write misses +system.cpu.dtb.read_accesses 522437731 # DTB read accesses +system.cpu.dtb.write_hits 282954606 # DTB write hits +system.cpu.dtb.write_misses 50165 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 282541184 # DTB write accesses -system.cpu.dtb.data_hits 801529416 # DTB hits -system.cpu.dtb.data_misses 656505 # DTB misses +system.cpu.dtb.write_accesses 283004771 # DTB write accesses +system.cpu.dtb.data_hits 804798693 # DTB hits +system.cpu.dtb.data_misses 643809 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 802185921 # DTB accesses -system.cpu.itb.fetch_hits 390623308 # ITB hits -system.cpu.itb.fetch_misses 546 # ITB misses +system.cpu.dtb.data_accesses 805442502 # DTB accesses +system.cpu.itb.fetch_hits 394528514 # ITB hits +system.cpu.itb.fetch_misses 534 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390623854 # ITB accesses +system.cpu.itb.fetch_accesses 394529048 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,238 +313,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 39 # Number of system calls -system.cpu.numCycles 1252029901 # number of cpu cycles simulated +system.cpu.numCycles 1262601061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 405523870 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3256215701 # Number of instructions fetch has processed -system.cpu.fetch.Branches 388875863 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 314307287 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 626203619 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 155794648 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 73991596 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6471 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390623308 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 10992432 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1235766511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.634976 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.141364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 409498007 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3272810217 # Number of instructions fetch has processed +system.cpu.fetch.Branches 388673605 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 315452155 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 629699645 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 157846800 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 75851008 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 147 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7336 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 394528514 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11392908 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1246680714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.625219 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.138755 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 609562892 49.33% 49.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 56929322 4.61% 53.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 42752934 3.46% 57.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 71333026 5.77% 63.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 128895698 10.43% 73.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 44916877 3.63% 77.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 41222080 3.34% 80.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8947680 0.72% 81.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 231206002 18.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 616981069 49.49% 49.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57198279 4.59% 54.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 43039078 3.45% 57.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 71977388 5.77% 63.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129322230 10.37% 73.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46258105 3.71% 77.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 41218514 3.31% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7777319 0.62% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 232908732 18.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1235766511 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310596 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.600749 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 434050234 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 59825791 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 602225660 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9636107 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 130028719 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 31692009 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12420 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3180730731 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 46427 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 130028719 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 463334620 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 24461750 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 27280 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 582229724 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 35684418 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3082031269 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 15345 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 29415634 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2044995723 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3566316890 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3445638932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 120677958 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1246680714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307836 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.592117 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 437789893 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 62140482 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 606005534 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9132317 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 131612488 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 31510475 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12424 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3192799837 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 46361 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 131612488 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 467284900 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 27231873 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 27253 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 585294370 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 35229830 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3093290625 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 14758 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 28928557 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2053350484 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3577730264 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3457415406 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 120314858 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 660026653 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4235 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 97 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 110158163 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 738560803 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 349770872 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 68005426 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8800641 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2612267018 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2153832750 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17944057 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 789157528 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 720017007 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1235766511 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.742912 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.802932 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 668381414 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4231 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 109772702 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 743605283 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 351355021 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 69106055 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8779755 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2622263880 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2159577480 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 17944946 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 799158217 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 726204094 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1246680714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.732262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.802997 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 442318037 35.79% 35.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 194738197 15.76% 51.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 250284254 20.25% 71.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 121277806 9.81% 81.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 105807762 8.56% 90.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 77171137 6.24% 96.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 25347258 2.05% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 17054134 1.38% 99.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1767926 0.14% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 450451444 36.13% 36.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 196386892 15.75% 51.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 251435205 20.17% 72.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120817476 9.69% 81.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 104827933 8.41% 90.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 79080340 6.34% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 24383702 1.96% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 17529670 1.41% 99.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1768052 0.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1235766511 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1246680714 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1146289 3.17% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 25061435 69.20% 72.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 10007223 27.63% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1146168 3.12% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 25530327 69.57% 72.69% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 10022787 27.31% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1231694482 57.19% 57.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 17093 0.00% 57.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 27851386 1.29% 58.48% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 8254692 0.38% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 586233325 27.22% 86.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 292574368 13.58% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1233812197 57.13% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 27851163 1.29% 58.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 7204652 0.33% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 589396274 27.29% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 293038648 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2153832750 # Type of FU issued -system.cpu.iq.rate 1.720273 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36214947 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016814 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5446489367 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3313484734 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1984683423 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 151101648 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 88013502 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 73610007 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2112595001 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 77449944 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62149579 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2159577480 # Type of FU issued +system.cpu.iq.rate 1.710420 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36699282 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016994 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5469378913 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3334207188 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1989129090 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 151100989 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 87288283 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 73609749 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2118824418 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 77449592 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62141857 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 227490777 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 22685 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76128 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 138975976 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 232535257 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18630 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 75784 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 140560125 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4415 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2362 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4408 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 2802 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 130028719 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10422536 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 524259 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2975772151 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 731348 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 738560803 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 349770872 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 195346 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1466 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76128 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 25258103 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 28541 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 25286644 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2060237153 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 519644898 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 93595597 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 131612488 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 13139012 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 539946 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2986122932 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 725503 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 743605283 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 351355021 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 196101 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1503 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 75784 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 25727396 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 27151 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 25754547 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2065136857 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 522437892 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 94440623 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363505042 # number of nop insts executed -system.cpu.iew.exec_refs 802186536 # number of memory reference insts executed -system.cpu.iew.exec_branches 277071948 # Number of branches executed -system.cpu.iew.exec_stores 282541638 # Number of stores executed -system.cpu.iew.exec_rate 1.645518 # Inst execution rate -system.cpu.iew.wb_sent 2060115451 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2058293430 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1179460731 # num instructions producing a value -system.cpu.iew.wb_consumers 1750814151 # num instructions consuming a value +system.cpu.iew.exec_nop 363858964 # number of nop insts executed +system.cpu.iew.exec_refs 805443124 # number of memory reference insts executed +system.cpu.iew.exec_branches 277347977 # Number of branches executed +system.cpu.iew.exec_stores 283005232 # Number of stores executed +system.cpu.iew.exec_rate 1.635621 # Inst execution rate +system.cpu.iew.wb_sent 2065019944 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2062738839 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1180752690 # num instructions producing a value +system.cpu.iew.wb_consumers 1753366082 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.643965 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.673664 # average fanout of values written-back +system.cpu.iew.wb_rate 1.633722 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.673421 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 949829893 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 960178624 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 25252672 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1105737792 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.816875 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.519271 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 25721232 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1115068226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.801672 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.508434 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 488711252 44.20% 44.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 226575390 20.49% 64.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120398789 10.89% 75.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 59423757 5.37% 80.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 48998760 4.43% 85.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24145631 2.18% 87.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 18552721 1.68% 89.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 16148092 1.46% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102783400 9.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 496151769 44.50% 44.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 228465229 20.49% 64.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 119927421 10.76% 75.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 58951874 5.29% 81.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 50411669 4.52% 85.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 24161138 2.17% 87.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19007626 1.70% 89.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 16618211 1.49% 90.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 101373289 9.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1105737792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1115068226 # Number of insts commited each cycle system.cpu.commit.committedInsts 2008987604 # Number of instructions committed system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,192 +555,212 @@ system.cpu.commit.branches 266706457 # Nu system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions. system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions. system.cpu.commit.function_calls 39955347 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102783400 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 101373289 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3956135479 # The number of ROB reads -system.cpu.rob.rob_writes 6047665736 # The number of ROB writes -system.cpu.timesIdled 331504 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16263390 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3977224755 # The number of ROB reads +system.cpu.rob.rob_writes 6069947076 # The number of ROB writes +system.cpu.timesIdled 341189 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 15920347 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.686780 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.686780 # CPI: Total CPI of All Threads -system.cpu.ipc 1.456070 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.456070 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2621566555 # number of integer regfile reads -system.cpu.int_regfile_writes 1491832809 # number of integer regfile writes -system.cpu.fp_regfile_reads 78811406 # number of floating regfile reads -system.cpu.fp_regfile_writes 52661103 # number of floating regfile writes +system.cpu.cpi 0.692579 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.692579 # CPI: Total CPI of All Threads +system.cpu.ipc 1.443879 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.443879 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2627113034 # number of integer regfile reads +system.cpu.int_regfile_writes 1496009216 # number of integer regfile writes +system.cpu.fp_regfile_reads 78810922 # number of floating regfile reads +system.cpu.fp_regfile_writes 52660839 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 8325 # number of replacements -system.cpu.icache.tagsinuse 1657.564105 # Cycle average of tags in use -system.cpu.icache.total_refs 390610507 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 10037 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 38917.057587 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 166051525 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1470336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1470335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 71638 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 71638 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 20109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3159809 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3179918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 643456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104184960 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 104828416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 104828416 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 914943500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 15081000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2297878500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu.icache.replacements 8339 # number of replacements +system.cpu.icache.tagsinuse 1660.409803 # Cycle average of tags in use +system.cpu.icache.total_refs 394515611 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 10054 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 39239.666899 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1657.564105 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.809357 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.809357 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390610507 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390610507 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390610507 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390610507 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390610507 # number of overall hits -system.cpu.icache.overall_hits::total 390610507 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12801 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12801 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12801 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12801 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12801 # number of overall misses -system.cpu.icache.overall_misses::total 12801 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 308797999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 308797999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 308797999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 308797999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 308797999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 308797999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390623308 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390623308 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390623308 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390623308 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390623308 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390623308 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1660.409803 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.810747 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.810747 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 394515611 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 394515611 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 394515611 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 394515611 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 394515611 # number of overall hits +system.cpu.icache.overall_hits::total 394515611 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12903 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12903 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12903 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12903 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12903 # number of overall misses +system.cpu.icache.overall_misses::total 12903 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 381736499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 381736499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 381736499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 381736499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 381736499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 381736499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 394528514 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 394528514 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 394528514 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 394528514 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 394528514 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 394528514 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000033 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000033 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000033 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000033 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000033 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000033 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24122.959066 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24122.959066 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24122.959066 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24122.959066 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24122.959066 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24122.959066 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1026 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29585.096412 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29585.096412 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29585.096412 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29585.096412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29585.096412 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29585.096412 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 820 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 85.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 51.250000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2763 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2763 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2763 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2763 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2763 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2763 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10038 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 10038 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 10038 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 10038 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 10038 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 10038 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 233558499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 233558499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 233558499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 233558499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 233558499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 233558499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000026 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000026 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23267.433652 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23267.433652 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23267.433652 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23267.433652 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23267.433652 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23267.433652 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2848 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2848 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2848 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2848 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2848 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2848 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10055 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 10055 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 10055 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 10055 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 10055 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 10055 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281131499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 281131499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281131499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 281131499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281131499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 281131499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27959.373347 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27959.373347 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27959.373347 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27959.373347 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27959.373347 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27959.373347 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 443343 # number of replacements -system.cpu.l2cache.tagsinuse 32701.945922 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1090021 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 476079 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.289580 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 443356 # number of replacements +system.cpu.l2cache.tagsinuse 32690.931292 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1090076 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 476092 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 2.289633 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 1310.047547 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 33.839791 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31358.058585 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.039979 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.001033 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.956972 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.997984 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 7288 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1053694 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1060982 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 95989 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 95989 # number of Writeback hits +system.cpu.l2cache.occ_blocks::writebacks 1331.519382 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 35.398256 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31324.013654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.040635 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.001080 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.955933 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.997648 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7284 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1053767 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1061051 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 95971 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 95971 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 4788 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 4788 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 7288 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1058482 # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1541892 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 10038 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1531854 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1541892 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.273959 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278397 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.278366 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933168 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.933168 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.273959 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.309019 # 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average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68353.593197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54772.909091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68432.488614 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68353.593197 # average overall miss latency +system.cpu.l2cache.demand_hits::cpu.inst 7284 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1058555 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1065839 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 7284 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1058555 # number of overall hits +system.cpu.l2cache.overall_hits::total 1065839 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2771 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 406514 # 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number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5010236500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5010236500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 198230500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 34833756500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35031987000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 198230500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 34833756500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35031987000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 10055 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1460281 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1470336 # 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miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.278362 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933164 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.933164 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.275584 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.309001 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.308783 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.275584 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.309001 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.308783 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71537.531577 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73364.066182 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73351.699916 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74947.442034 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74947.442034 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71537.531577 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73587.675658 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73575.744274 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71537.531577 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73587.675658 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73575.744274 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -657,162 +771,180 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66908 # number of writebacks system.cpu.l2cache.writebacks::total 66908 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2750 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406518 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 409268 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2750 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 473372 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 476122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2750 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 473372 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 476122 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 116465465 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23520724104 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23637189569 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2970386425 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2970386425 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 116465465 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26491110529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26607575994 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 116465465 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26491110529 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26607575994 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.273959 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278397 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278366 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933168 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933168 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.273959 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309019 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.308791 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.273959 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309019 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.308791 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42351.078182 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57858.997889 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57754.795315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44430.945418 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44430.945418 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42351.078182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55962.563331 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55883.945699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42351.078182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55962.563331 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55883.945699 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2771 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406514 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 409285 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66850 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66850 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2771 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 473364 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476135 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2771 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 473364 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 476135 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163863750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 24701594750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24865458500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4205391250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4205391250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163863750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28906986000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29070849750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163863750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28906986000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29070849750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.275584 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.278381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.278362 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933164 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.933164 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.275584 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.309001 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.308783 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.275584 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.309001 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.308783 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59135.239986 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60764.438002 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60753.407772 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62907.872102 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62907.872102 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59135.239986 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61067.140720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61055.897487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59135.239986 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61067.140720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61055.897487 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1527758 # number of replacements -system.cpu.dcache.tagsinuse 4094.851524 # Cycle average of tags in use -system.cpu.dcache.total_refs 664689576 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1531854 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 433.911832 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 314426000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.851524 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999720 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999720 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 454956433 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454956433 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 209733120 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 209733120 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 23 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 23 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 664689553 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 664689553 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 664689553 # number of overall hits -system.cpu.dcache.overall_hits::total 664689553 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1925751 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1925751 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1061776 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1061776 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2987527 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2987527 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2987527 # number of overall misses -system.cpu.dcache.overall_misses::total 2987527 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65916980500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65916980500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 35408599379 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 35408599379 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 101325579879 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 101325579879 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 101325579879 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 101325579879 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 456882184 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 456882184 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1527823 # number of replacements +system.cpu.dcache.tagsinuse 4094.615904 # Cycle average of tags in use +system.cpu.dcache.total_refs 667502438 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1531919 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 435.729590 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 397277000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.615904 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999662 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999662 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 457769415 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 457769415 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 209733001 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 209733001 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 667502416 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 667502416 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 667502416 # number of overall hits +system.cpu.dcache.overall_hits::total 667502416 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1925774 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1925774 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1061895 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1061895 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2987669 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2987669 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2987669 # number of overall misses +system.cpu.dcache.overall_misses::total 2987669 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 75679638000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 75679638000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 45101799853 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 45101799853 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 133500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 133500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 120781437853 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 120781437853 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 120781437853 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 120781437853 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 459695189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 459695189 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 23 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 23 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 667677080 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 667677080 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 667677080 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 667677080 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004215 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004215 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005037 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005037 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004475 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004475 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004475 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004475 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34229.233426 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34229.233426 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33348.464628 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33348.464628 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33916.205570 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33916.205570 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33916.205570 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33916.205570 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13719 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 382 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 670490085 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 670490085 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 670490085 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 670490085 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004189 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004189 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.083333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.083333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004456 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004456 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004456 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004456 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39298.296685 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39298.296685 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42472.937393 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42472.937393 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40426.646276 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40426.646276 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17832 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 107 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 375 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.913613 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.552000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks -system.cpu.dcache.writebacks::total 95989 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465539 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 465539 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990134 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 990134 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1455673 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1455673 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1455673 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1455673 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460212 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1460212 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1531854 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1531854 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1531854 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1531854 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40615263000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 40615263000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3896657000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3896657000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44511920000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44511920000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44511920000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44511920000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks +system.cpu.dcache.writebacks::total 95971 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465494 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 465494 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990257 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 990257 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1455751 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1455751 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1455751 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1455751 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460280 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1460280 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1531918 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1531918 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1531918 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1531918 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41822016500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 41822016500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5130364000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130364000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46952380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46952380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46952380500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46952380500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003177 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003177 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002294 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002294 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002294 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002294 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27814.634450 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27814.634450 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54390.678652 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54390.678652 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29057.547260 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29057.547260 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29057.547260 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29057.547260 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002285 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002285 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28639.724231 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28639.724231 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71615.120467 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71615.120467 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index 7637d378a..e66382473 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.004711 # Nu sim_ticks 1004710587000 # Number of ticks simulated final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2509174 # Simulator instruction rate (inst/s) -host_op_rate 2509174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1254857691 # Simulator tick rate (ticks/s) -host_mem_usage 273968 # Number of bytes of host memory used -host_seconds 800.66 # Real time elapsed on the host +host_inst_rate 3493388 # Simulator instruction rate (inst/s) +host_op_rate 3493388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1747070946 # Simulator tick rate (ticks/s) +host_mem_usage 225488 # Number of bytes of host memory used +host_seconds 575.08 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1578689409 # Wr system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13131370496 # Throughput (bytes/s) +system.membus.data_through_bus 13193226959 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index f8a5c16cd..217f3cee7 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.769740 # Nu sim_ticks 2769739533000 # Number of ticks simulated final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 964642 # Simulator instruction rate (inst/s) -host_op_rate 964642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1329927483 # Simulator tick rate (ticks/s) -host_mem_usage 281524 # Number of bytes of host memory used -host_seconds 2082.62 # Real time elapsed on the host +host_inst_rate 1559352 # Simulator instruction rate (inst/s) +host_op_rate 1559352 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2149839105 # Simulator tick rate (ticks/s) +host_mem_usage 233980 # Number of bytes of host memory used +host_seconds 1288.35 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 1546034 # To system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 12529860 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408476 # Transaction distribution +system.membus.trans_dist::ReadResp 408476 # Transaction distribution +system.membus.trans_dist::Writeback 66908 # Transaction distribution +system.membus.trans_dist::ReadExReq 66873 # Transaction distribution +system.membus.trans_dist::ReadExResp 66873 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 1017606 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1017606 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34704448 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 34704448 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34704448 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4278141000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -405,5 +421,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 37822912 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1468788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 21192 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3156417 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3177609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 678144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104081472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 104759616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 15894000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2295216000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 3af1f1574..54c03f73f 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.627426 # Number of seconds simulated -sim_ticks 627426486000 # Number of ticks simulated -final_tick 627426486000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.629145 # Number of seconds simulated +sim_ticks 629144850500 # Number of ticks simulated +final_tick 629144850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65805 # Simulator instruction rate (inst/s) -host_op_rate 89618 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29824381 # Simulator tick rate (ticks/s) -host_mem_usage 297136 # Number of bytes of host memory used -host_seconds 21037.37 # Real time elapsed on the host +host_inst_rate 104232 # Simulator instruction rate (inst/s) +host_op_rate 141949 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47369420 # Simulator tick rate (ticks/s) +host_mem_usage 254336 # Number of bytes of host memory used +host_seconds 13281.67 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 154240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 30242112 # Number of bytes read from this memory -system.physmem.bytes_read::total 30396352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 154240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 154240 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 155072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 30241984 # Number of bytes read from this memory +system.physmem.bytes_read::total 30397056 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 155072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 155072 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2410 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 472533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 474943 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 472531 # Number of read requests responded to by this memory +system.physmem.num_reads::total 474954 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 245830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 48200248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 48446077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 245830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 245830 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 6742259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6742259 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 6742259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 245830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 48200248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 55188336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 474944 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 246481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48068396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 48314877 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 246481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 246481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6723844 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6723844 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6723844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 246481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48068396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55038721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 474954 # Total number of read requests seen system.physmem.writeReqs 66098 # Total number of write requests seen -system.physmem.cpureqs 545373 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30396352 # Total number of bytes read from memory +system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30397056 # Total number of bytes read from memory system.physmem.bytesWritten 4230272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30396352 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30397056 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4331 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 29709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 29700 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 29689 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 29719 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 29749 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 29652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 29638 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29679 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 29629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 29599 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 29623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 29684 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 29651 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 4159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 4130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 4128 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 4130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 4131 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 4119 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 4145 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 4136 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 4104 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 4108 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 4104 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 4133 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis +system.physmem.servicedByWrQ 163 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4296 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 29676 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 29740 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 29705 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 29805 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 29834 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 29631 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 29439 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 29482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 29490 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29536 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 29644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 29703 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 29631 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29795 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 627426443000 # Total gap between requests +system.physmem.totGap 629144781500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 474944 # Categorize read packet sizes +system.physmem.readPktSize::6 474954 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 66098 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 405886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 66680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 407688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -156,36 +156,115 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3439648250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 21418222000 # Sum of mem lat for all requests -system.physmem.totBusLat 2373960000 # Total cycles spent in databus access -system.physmem.totBankLat 15604613750 # Total cycles spent in bank access -system.physmem.avgQLat 7244.54 # Average queueing delay per request -system.physmem.avgBankLat 32866.21 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 173211 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 199.837655 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.549683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 508.405937 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 59600 34.41% 34.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 42691 24.65% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 39909 23.04% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 25367 14.65% 96.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 276 0.16% 96.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 104 0.06% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 98 0.06% 97.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 91 0.05% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 88 0.05% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 83 0.05% 97.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 78 0.05% 97.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 81 0.05% 97.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 73 0.04% 97.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 74 0.04% 97.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 79 0.05% 97.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 80 0.05% 97.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 80 0.05% 97.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 73 0.04% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 73 0.04% 97.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3309 1.91% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 4 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 3 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 173211 # Bytes accessed per row activation +system.physmem.totQLat 2060605250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15116660250 # Sum of mem lat for all requests +system.physmem.totBusLat 2373955000 # Total cycles spent in databus access +system.physmem.totBankLat 10682100000 # Total cycles spent in bank access +system.physmem.avgQLat 4340.03 # Average queueing delay per request +system.physmem.avgBankLat 22498.53 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 45110.75 # Average memory access latency -system.physmem.avgRdBW 48.45 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 48.45 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31838.56 # Average memory access latency +system.physmem.avgRdBW 48.31 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 48.31 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.72 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.43 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.03 # Average read queue length over time -system.physmem.avgWrQLen 17.42 # Average write queue length over time -system.physmem.readRowHits 143318 # Number of row buffer hits during reads -system.physmem.writeRowHits 45505 # Number of row buffer hits during writes -system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes -system.physmem.avgGap 1159663.10 # Average gap between requests -system.cpu.branchPred.lookups 441070019 # Number of BP lookups -system.cpu.branchPred.condPredicted 353935839 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 30635394 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 253577570 # Number of BTB lookups -system.cpu.branchPred.BTBHits 230740155 # Number of BTB hits +system.physmem.avgRdQLen 0.02 # Average read queue length over time +system.physmem.avgWrQLen 17.41 # Average write queue length over time +system.physmem.readRowHits 318020 # Number of row buffer hits during reads +system.physmem.writeRowHits 49639 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.10 # Row buffer hit rate for writes +system.physmem.avgGap 1162817.59 # Average gap between requests +system.membus.throughput 55038619 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408879 # Transaction distribution +system.membus.trans_dist::ReadResp 408878 # Transaction distribution +system.membus.trans_dist::Writeback 66098 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution +system.membus.trans_dist::ReadExReq 66075 # Transaction distribution +system.membus.trans_dist::ReadExResp 66075 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 1024597 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1024597 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34627264 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 34627264 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34627264 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1206768500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4481136954 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu.branchPred.lookups 441633744 # Number of BP lookups +system.cpu.branchPred.condPredicted 353245820 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 30626910 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 253291175 # Number of BTB lookups +system.cpu.branchPred.BTBHits 229518524 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 90.993914 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 51827244 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2806499 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 90.614497 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 52707299 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2806413 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +308,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1254852973 # number of cpu cycles simulated +system.cpu.numCycles 1258289702 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 354891147 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2286425176 # Number of instructions fetch has processed -system.cpu.fetch.Branches 441070019 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 282567399 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 601918215 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 156601137 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 130017521 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 563 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 11246 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 335797832 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11972922 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1212752602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.588148 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.180737 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 355059035 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2281679265 # Number of instructions fetch has processed +system.cpu.fetch.Branches 441633744 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 282225823 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 601500993 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 156584245 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 133257591 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 11034 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 167 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 335655020 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11657170 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1215734936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.578441 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.176596 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 610879185 50.37% 50.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42915841 3.54% 53.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 96172627 7.93% 61.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 57091199 4.71% 66.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 71993232 5.94% 72.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 43518781 3.59% 76.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 30912276 2.55% 78.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 32947513 2.72% 81.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226321948 18.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 614278728 50.53% 50.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 43031217 3.54% 54.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 96058050 7.90% 61.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55653458 4.58% 66.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 73683625 6.06% 72.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 43835223 3.61% 76.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31015132 2.55% 78.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 32844314 2.70% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 225335189 18.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1212752602 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.351491 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.822066 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 405845320 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 102427093 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 561818768 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 16761536 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 125899885 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 44789430 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 14217 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3028082478 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30107 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 125899885 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 441818256 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 34409054 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 439229 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 540562916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 69623262 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2944183318 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4821524 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 54501316 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2929324563 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14012451828 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13441344414 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 571107414 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1215734936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.350979 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.813318 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 405408112 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105525155 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 562197495 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 16710779 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 125893395 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 45735070 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12243 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3027450313 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 24999 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 125893395 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 441381944 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 37599884 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 466637 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 540742593 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 69650483 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2947282074 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 91 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4813438 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 54199144 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2931640163 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14025190740 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13455020985 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 570169755 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 936184473 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 21713 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19183 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 177423093 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 969808911 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 487407647 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 36223294 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40155637 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2791556624 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29091 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2432817301 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13264046 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 893693392 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2309057295 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7707 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1212752602 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.006029 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.872054 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 938500073 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 22029 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19516 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 179002715 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 971623898 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 487434291 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36825257 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 41359268 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2792194659 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28248 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2432796766 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13281338 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 894337134 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2316040320 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 6864 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1215734936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.001091 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 376736827 31.06% 31.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 183745627 15.15% 46.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 204018800 16.82% 63.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 169675350 13.99% 77.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 132825359 10.95% 87.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 92323584 7.61% 95.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 37944626 3.13% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 12438520 1.03% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3043909 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 379743334 31.24% 31.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 183587297 15.10% 46.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 204204940 16.80% 63.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 169567149 13.95% 77.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 132821991 10.93% 88.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 92473374 7.61% 95.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37933065 3.12% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12385370 1.02% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 3018416 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1212752602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1215734936 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 715136 0.82% 0.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 55109735 62.90% 63.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 31764891 36.26% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 717080 0.82% 0.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 24380 0.03% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55165781 62.93% 63.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 31749638 36.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1103878887 45.37% 45.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11223380 0.46% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1103940359 45.38% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11224025 0.46% 45.84% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued @@ -375,93 +453,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876473 0.28% 46.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5503230 0.23% 46.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5502268 0.23% 46.40% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23422628 0.96% 47.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.36% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 838195655 34.45% 81.82% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 442341757 18.18% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23395329 0.96% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 838660213 34.47% 81.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 441822804 18.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2432817301 # Type of FU issued -system.cpu.iq.rate 1.938727 # Inst issue rate -system.cpu.iq.fu_busy_cnt 87614143 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.036013 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6056711081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3602481479 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2248827251 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122554312 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 82864717 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 56458852 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2457090579 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 63340865 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84315452 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2432796766 # Type of FU issued +system.cpu.iq.rate 1.933415 # Inst issue rate +system.cpu.iq.fu_busy_cnt 87656879 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036031 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6059775624 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3603986878 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2248220965 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 122491061 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 82640163 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56428970 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2457145320 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63308325 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 84445856 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 338421730 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8530 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1429952 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 210412350 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 340236717 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 10068 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1429873 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 210438994 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 257 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 345 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 125899885 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12642453 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1559188 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2791598235 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1393439 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 969808911 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 487407647 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19105 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1555218 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1429952 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 32462166 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1535020 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 33997186 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2358042615 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 792538170 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 74774686 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 125893395 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 15644195 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1562618 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2792235356 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1396921 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 971623898 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 487434291 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18262 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1558827 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2523 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1429873 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 32450935 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1518228 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 33969163 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2357455643 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 792848546 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 75341123 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12520 # number of nop insts executed -system.cpu.iew.exec_refs 1216339727 # number of memory reference insts executed -system.cpu.iew.exec_branches 319851158 # Number of branches executed -system.cpu.iew.exec_stores 423801557 # Number of stores executed -system.cpu.iew.exec_rate 1.879139 # Inst execution rate -system.cpu.iew.wb_sent 2331014082 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2305286103 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1347320139 # num instructions producing a value -system.cpu.iew.wb_consumers 2523004414 # num instructions consuming a value +system.cpu.iew.exec_nop 12449 # number of nop insts executed +system.cpu.iew.exec_refs 1216025241 # number of memory reference insts executed +system.cpu.iew.exec_branches 319732380 # Number of branches executed +system.cpu.iew.exec_stores 423176695 # Number of stores executed +system.cpu.iew.exec_rate 1.873540 # Inst execution rate +system.cpu.iew.wb_sent 2330413186 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2304649935 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1347862197 # num instructions producing a value +system.cpu.iew.wb_consumers 2523443205 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.837097 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.534014 # average fanout of values written-back +system.cpu.iew.wb_rate 1.831573 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.534136 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 906262003 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 906899118 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 30621444 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1086852717 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.734675 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.398797 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 30614902 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1089841541 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.729918 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.397219 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 446522418 41.08% 41.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288653852 26.56% 67.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 95098505 8.75% 76.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 70200543 6.46% 82.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 46464549 4.28% 87.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 22199454 2.04% 89.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 15846996 1.46% 90.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 10984775 1.01% 91.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 90881625 8.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 449517068 41.25% 41.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 288638854 26.48% 67.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 95107207 8.73% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 70204085 6.44% 82.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 46459856 4.26% 87.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 22200640 2.04% 89.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15848625 1.45% 90.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10985187 1.01% 91.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 90880019 8.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1086852717 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1089841541 # Number of insts commited each cycle system.cpu.commit.committedInsts 1384381606 # Number of instructions committed system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,200 +550,222 @@ system.cpu.commit.branches 298259106 # Nu system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 90881625 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 90880019 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3787551108 # The number of ROB reads -system.cpu.rob.rob_writes 5709107671 # The number of ROB writes -system.cpu.timesIdled 353124 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 42100371 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3791178653 # The number of ROB reads +system.cpu.rob.rob_writes 5710375191 # The number of ROB writes +system.cpu.timesIdled 353026 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 42554766 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1384370590 # Number of Instructions Simulated system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated -system.cpu.cpi 0.906443 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.906443 # CPI: Total CPI of All Threads -system.cpu.ipc 1.103213 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.103213 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11756785732 # number of integer regfile reads -system.cpu.int_regfile_writes 2218462767 # number of integer regfile writes -system.cpu.fp_regfile_reads 68799116 # number of floating regfile reads -system.cpu.fp_regfile_writes 49570496 # number of floating regfile writes -system.cpu.misc_regfile_reads 1364149303 # number of misc regfile reads +system.cpu.cpi 0.908925 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.908925 # CPI: Total CPI of All Threads +system.cpu.ipc 1.100200 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.100200 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11755248902 # number of integer regfile reads +system.cpu.int_regfile_writes 2218571084 # number of integer regfile writes +system.cpu.fp_regfile_reads 68795959 # number of floating regfile reads +system.cpu.fp_regfile_writes 49541079 # number of floating regfile writes +system.cpu.misc_regfile_reads 1363718123 # number of misc regfile reads system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes -system.cpu.icache.replacements 22544 # number of replacements -system.cpu.icache.tagsinuse 1643.593682 # Cycle average of tags in use -system.cpu.icache.total_refs 335759855 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 24228 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13858.339731 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 169026080 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1492742 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1492741 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96335 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72516 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72516 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52382 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178768 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3231150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1538688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104528128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 106066816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 106066816 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 929281000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 42510998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2307535978 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu.icache.replacements 22361 # number of replacements +system.cpu.icache.tagsinuse 1639.588858 # Cycle average of tags in use +system.cpu.icache.total_refs 335620121 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 24041 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13960.322824 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1643.593682 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.802536 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.802536 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 335766423 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 335766423 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 335766423 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 335766423 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 335766423 # number of overall hits -system.cpu.icache.overall_hits::total 335766423 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 31408 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 31408 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 31408 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 31408 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 31408 # number of overall misses -system.cpu.icache.overall_misses::total 31408 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 477378999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 477378999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 477378999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 477378999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 477378999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 477378999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 335797831 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 335797831 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 335797831 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 335797831 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 335797831 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 335797831 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000094 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,193 +776,193 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 20 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 20 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 20 # 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number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10000 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10000 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 969916794 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 969916794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 969916794 # number of overall hits -system.cpu.dcache.overall_hits::total 969916794 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1953499 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1953499 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 842027 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 842027 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 970083263 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 970083263 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 970083263 # number of overall hits +system.cpu.dcache.overall_hits::total 970083263 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1953007 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1953007 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 842413 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 842413 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2795526 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2795526 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2795526 # number of overall misses -system.cpu.dcache.overall_misses::total 2795526 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 66742188500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 66742188500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 39429860969 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 39429860969 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 216000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 216000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 106172049469 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 106172049469 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 106172049469 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 106172049469 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 695776642 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 695776642 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2795420 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795420 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795420 # number of overall misses +system.cpu.dcache.overall_misses::total 2795420 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 79048557500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 79048557500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 56325650469 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 56325650469 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 203500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 203500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 135374207969 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 135374207969 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 135374207969 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 135374207969 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 695943005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 695943005 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972712320 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972712320 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972712320 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972712320 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002808 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002808 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003041 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003041 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972878683 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972878683 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972878683 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972878683 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002806 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002806 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002874 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002874 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002874 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002874 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34165.458237 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34165.458237 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46827.311914 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46827.311914 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37979.274551 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37979.274551 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37979.274551 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37979.274551 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1535 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 741 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 54 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.002873 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002873 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002873 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002873 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40475.306796 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40475.306796 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66862.275949 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 66862.275949 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67833.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48427.144389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48427.144389 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2558 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 879 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.425926 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.325843 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.103448 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9.876404 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 96322 # number of writebacks -system.cpu.dcache.writebacks::total 96322 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488793 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 488793 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765175 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 765175 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 96335 # number of writebacks +system.cpu.dcache.writebacks::total 96335 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488604 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 488604 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765599 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 765599 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1253968 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1253968 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1253968 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1253968 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464706 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464706 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76852 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76852 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1541558 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1541558 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1541558 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1541558 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41088591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41088591000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3410048000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3410048000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44498639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44498639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44498639000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44498639000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28052.449434 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28052.449434 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44371.623380 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44371.623380 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 1254203 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1254203 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1254203 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1254203 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464403 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464403 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541217 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541217 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541217 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541217 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42813858522 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 42813858522 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4818359000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4818359000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47632217522 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 47632217522 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47632217522 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 47632217522 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002104 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29236.390886 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29236.390886 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62727.614758 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62727.614758 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 72ddef8e3..ae323b307 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu sim_ticks 945613126000 # Number of ticks simulated final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1270703 # Simulator instruction rate (inst/s) -host_op_rate 1730522 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 867964073 # Simulator tick rate (ticks/s) -host_mem_usage 286692 # Number of bytes of host memory used -host_seconds 1089.46 # Real time elapsed on the host +host_inst_rate 1181509 # Simulator instruction rate (inst/s) +host_op_rate 1609052 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 807039161 # Simulator tick rate (ticks/s) +host_mem_usage 242488 # Number of bytes of host memory used +host_seconds 1171.71 # Real time elapsed on the host sim_insts 1384381606 # Number of instructions simulated sim_ops 1885336358 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1188602786 # Wr system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9675679644 # Throughput (bytes/s) +system.membus.data_through_bus 9149449674 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index dc10302b1..6e9e09ef8 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.326119 # Nu sim_ticks 2326118592000 # Number of ticks simulated final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 664911 # Simulator instruction rate (inst/s) -host_op_rate 901999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1119467924 # Simulator tick rate (ticks/s) -host_mem_usage 296296 # Number of bytes of host memory used -host_seconds 2077.88 # Real time elapsed on the host +host_inst_rate 575384 # Simulator instruction rate (inst/s) +host_op_rate 780549 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 968736790 # Simulator tick rate (ticks/s) +host_mem_usage 250996 # Number of bytes of host memory used +host_seconds 2401.19 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 1818624 # To system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 14864384 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 408063 # Transaction distribution +system.membus.trans_dist::ReadResp 408063 # Transaction distribution +system.membus.trans_dist::Writeback 66099 # Transaction distribution +system.membus.trans_dist::ReadExReq 66093 # Transaction distribution +system.membus.trans_dist::ReadExResp 66093 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 1014411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 1014411 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34576320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 34576320 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 34576320 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 39606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3163563 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3203169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1267392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104314240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 105581632 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index 62028d00d..9b354cbb8 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,90 +1,90 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.042726 # Number of seconds simulated -sim_ticks 42725646500 # Number of ticks simulated -final_tick 42725646500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.043732 # Number of seconds simulated +sim_ticks 43731802500 # Number of ticks simulated +final_tick 43731802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44211 # Simulator instruction rate (inst/s) -host_op_rate 44211 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21382391 # Simulator tick rate (ticks/s) -host_mem_usage 280712 # Number of bytes of host memory used -host_seconds 1998.17 # Real time elapsed on the host +host_inst_rate 69429 # Simulator instruction rate (inst/s) +host_op_rate 69429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34369620 # Simulator tick rate (ticks/s) +host_mem_usage 233240 # Number of bytes of host memory used +host_seconds 1272.40 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 454528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory -system.physmem.bytes_read::total 10592896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 454528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 454528 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10592960 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 454592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 454592 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7102 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 7103 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165514 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10638294 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 237289985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 247928279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10638294 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10638294 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 170759452 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 170759452 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 170759452 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10638294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 237289985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 418687731 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165514 # Total number of read requests seen +system.physmem.bw_read::cpu.inst 10394998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 231830554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 242225552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 10394998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 10394998 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 166830718 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 166830718 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 166830718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 10394998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 231830554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 409056270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165515 # Total number of read requests seen system.physmem.writeReqs 113997 # Total number of write requests seen -system.physmem.cpureqs 279511 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10592896 # Total number of bytes read from memory +system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10592960 # Total number of bytes read from memory system.physmem.bytesWritten 7295808 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10592896 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10572 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10768 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10442 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10202 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10515 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10376 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10439 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10013 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10363 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10187 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10594 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6998 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7226 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6938 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6964 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7283 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 42725626000 # Total gap between requests +system.physmem.totGap 43731782000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 165514 # Categorize read packet sizes +system.physmem.readPktSize::6 165515 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -92,11 +92,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 113997 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 62488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 76381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 72899 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,12 +124,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see @@ -147,65 +147,209 @@ system.physmem.wrQLenPdf::19 4956 # Wh system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 7078163250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9669555750 # Sum of mem lat for all requests -system.physmem.totBusLat 827570000 # Total cycles spent in databus access -system.physmem.totBankLat 1763822500 # Total cycles spent in bank access -system.physmem.avgQLat 42764.74 # Average queueing delay per request -system.physmem.avgBankLat 10656.64 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 48863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 366.074289 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.394514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 748.149039 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 19835 40.59% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7665 15.69% 56.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4199 8.59% 64.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2953 6.04% 70.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2157 4.41% 75.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1715 3.51% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1297 2.65% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1110 2.27% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 804 1.65% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 685 1.40% 86.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 483 0.99% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 536 1.10% 88.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 409 0.84% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 338 0.69% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 255 0.52% 90.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 348 0.71% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 228 0.47% 92.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 211 0.43% 92.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 159 0.33% 92.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 209 0.43% 93.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 394 0.81% 94.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 305 0.62% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 602 1.23% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 201 0.41% 97.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 151 0.31% 97.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 39 0.08% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 155 0.32% 97.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 66 0.14% 97.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 55 0.11% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 29 0.06% 98.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 79 0.16% 98.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 46 0.09% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 24 0.05% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 45 0.09% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 30 0.06% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 23 0.05% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 17 0.03% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 14 0.03% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 23 0.05% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 11 0.02% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 12 0.02% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 11 0.02% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 10 0.02% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 6 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 12 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 5 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 7 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 6 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 6 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 9 0.02% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 6 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 6 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 5 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48863 # Bytes accessed per row activation +system.physmem.totQLat 6289978250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8777494500 # Sum of mem lat for all requests +system.physmem.totBusLat 827575000 # Total cycles spent in databus access +system.physmem.totBankLat 1659941250 # Total cycles spent in bank access +system.physmem.avgQLat 38002.47 # Average queueing delay per request +system.physmem.avgBankLat 10028.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58421.38 # Average memory access latency -system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53031.41 # Average memory access latency +system.physmem.avgRdBW 242.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 166.83 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 242.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 166.83 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.27 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.23 # Average read queue length over time -system.physmem.avgWrQLen 10.41 # Average write queue length over time -system.physmem.readRowHits 148885 # Number of row buffer hits during reads -system.physmem.writeRowHits 71702 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.90 # Row buffer hit rate for writes -system.physmem.avgGap 152858.48 # Average gap between requests -system.cpu.branchPred.lookups 18741806 # Number of BP lookups -system.cpu.branchPred.condPredicted 12317440 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4774691 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 15571063 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4663219 # Number of BTB hits +system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time +system.physmem.avgWrQLen 10.42 # Average write queue length over time +system.physmem.readRowHits 153768 # Number of row buffer hits during reads +system.physmem.writeRowHits 76872 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.90 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.43 # Row buffer hit rate for writes +system.physmem.avgGap 156457.62 # Average gap between requests +system.membus.throughput 409056270 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 34624 # Transaction distribution +system.membus.trans_dist::ReadResp 34624 # Transaction distribution +system.membus.trans_dist::Writeback 113997 # Transaction distribution +system.membus.trans_dist::ReadExReq 130891 # Transaction distribution +system.membus.trans_dist::ReadExResp 130891 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 445027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 445027 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17888768 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17888768 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17888768 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1215256500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 1522914250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.5 # Layer utilization (%) +system.cpu.branchPred.lookups 18742056 # Number of BP lookups +system.cpu.branchPred.condPredicted 12318265 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4775163 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 15487144 # Number of BTB lookups +system.cpu.branchPred.BTBHits 4660091 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 29.947981 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1660960 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 30.090061 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1660966 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20277542 # DTB read hits +system.cpu.dtb.read_hits 20277593 # DTB read hits system.cpu.dtb.read_misses 90148 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20367690 # DTB read accesses -system.cpu.dtb.write_hits 14728781 # DTB write hits +system.cpu.dtb.read_accesses 20367741 # DTB read accesses +system.cpu.dtb.write_hits 14728959 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14736033 # DTB write accesses -system.cpu.dtb.data_hits 35006323 # DTB hits +system.cpu.dtb.write_accesses 14736211 # DTB write accesses +system.cpu.dtb.data_hits 35006552 # DTB hits system.cpu.dtb.data_misses 97400 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 35103723 # DTB accesses -system.cpu.itb.fetch_hits 12368482 # ITB hits -system.cpu.itb.fetch_misses 10998 # ITB misses +system.cpu.dtb.data_accesses 35103952 # DTB accesses +system.cpu.itb.fetch_hits 12367361 # ITB hits +system.cpu.itb.fetch_misses 10891 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 12379480 # ITB accesses +system.cpu.itb.fetch_accesses 12378252 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,34 +363,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 85451294 # number of cpu cycles simulated +system.cpu.numCycles 87463606 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 8073687 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 10668119 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 74170009 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 8070350 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 10671706 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 74169774 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 126489259 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 66071 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 126489024 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 66036 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 293701 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 14164942 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 35060353 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 4447581 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 216610 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4664191 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 9108383 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 33.865790 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 44777788 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 293666 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 14166320 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 35060384 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 4447706 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 216957 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4664663 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 9107934 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 33.869161 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 44778070 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 77182336 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 77195811 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 229187 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 15880194 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 69571100 # Number of cycles cpu stages are processed. -system.cpu.activity 81.416087 # Percentage of cycles cpu is active +system.cpu.timesIdled 233969 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17892398 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 69571208 # Number of cycles cpu stages are processed. +system.cpu.activity 79.543036 # Percentage of cycles cpu is active system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.comBranches 13754477 # Number of Branches instructions committed @@ -258,194 +402,214 @@ system.cpu.committedInsts 88340673 # Nu system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total) -system.cpu.cpi 0.967293 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.990072 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.967293 # CPI: Total CPI of All Threads -system.cpu.ipc 1.033813 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.990072 # CPI: Total CPI of All Threads +system.cpu.ipc 1.010028 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.033813 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32800214 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 52651080 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 61.615310 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 42999576 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 42451718 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 49.679433 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 42421796 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 43029498 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 50.355584 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 63338785 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 22112509 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 25.877325 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 39402182 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 46049112 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 53.889309 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 84283 # number of replacements -system.cpu.icache.tagsinuse 1908.281182 # Cycle average of tags in use -system.cpu.icache.total_refs 12251335 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 86329 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 141.914478 # Average number of references to valid blocks. +system.cpu.ipc_total 1.010028 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 34814257 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 52649349 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 60.195722 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 45010578 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 42453028 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 48.537935 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 44433795 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 43029811 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 49.197390 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65350614 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 22112992 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 25.282507 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 41414421 # 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number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1898913500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1898913500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1898913500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1898913500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12368472 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12368472 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12368472 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12368472 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12368472 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12368472 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009471 # 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average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 28 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1906.561640 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.930938 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.930938 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12250118 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12250118 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12250118 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12250118 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12250118 # number of overall hits +system.cpu.icache.overall_hits::total 12250118 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 117235 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12367353 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12367353 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12367353 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12367353 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12367353 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009479 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.009479 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.009479 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.009479 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.009479 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.009479 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17397.112637 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 17397.112637 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 17397.112637 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 17397.112637 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 17397.112637 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 17397.112637 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 661 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 188 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 46.812500 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 36.722222 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30808 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 30808 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 30808 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 30808 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 30808 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 30808 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86329 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 86329 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 86329 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 86329 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 86329 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 86329 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1336106500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1336106500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1336106500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1336106500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1336106500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1336106500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006980 # 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number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574580 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 33754860 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 33754860 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 33754860 # number of overall hits +system.cpu.dcache.overall_hits::total 33754860 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 96358 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 96358 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1038797 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1038797 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1135155 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1135155 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1135155 # number of overall misses +system.cpu.dcache.overall_misses::total 1135155 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4970252500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4970252500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 87207912000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 87207912000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92178164500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92178164500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92178164500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92178164500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -542,56 +706,56 @@ system.cpu.dcache.demand_accesses::cpu.data 34890015 # system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004754 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004754 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.707255 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.707255 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73908.778388 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73908.778388 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71041.115168 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71041.115168 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5035459 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 116380 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004752 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071085 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.032535 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032535 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032535 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032535 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51581.108989 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51581.108989 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83950.870093 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 83950.870093 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81203.152433 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81203.152433 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5824366 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 116607 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.267391 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.948682 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks -system.cpu.dcache.writebacks::total 168351 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35632 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 35632 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895187 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895187 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930819 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930819 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930819 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930819 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks +system.cpu.dcache.writebacks::total 168352 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35591 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 35591 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895217 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895217 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930808 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930808 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930808 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930808 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910017000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910017000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12290144000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12290144000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14200161000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14200161000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14200161000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14200161000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2407208517 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2407208517 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14006251501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14006251501 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16413460018 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16413460018 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16413460018 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16413460018 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -600,14 +764,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31432.330580 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31432.330580 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85597.882713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85597.882713 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39613.746227 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39613.746227 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97550.156714 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97550.156714 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 8eb5d8593..42c254d5a 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023932 # Number of seconds simulated -sim_ticks 23931821000 # Number of ticks simulated -final_tick 23931821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024943 # Number of seconds simulated +sim_ticks 24942850000 # Number of ticks simulated +final_tick 24942850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61921 # Simulator instruction rate (inst/s) -host_op_rate 61921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18618559 # Simulator tick rate (ticks/s) -host_mem_usage 281736 # Number of bytes of host memory used -host_seconds 1285.37 # Real time elapsed on the host +host_inst_rate 187895 # Simulator instruction rate (inst/s) +host_op_rate 187895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58883311 # Simulator tick rate (ticks/s) +host_mem_usage 236320 # Number of bytes of host memory used +host_seconds 423.60 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10154048 # Number of bytes read from this memory -system.physmem.bytes_read::total 10644032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158657 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166313 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 20474163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 424290655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 444764818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 20474163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 20474163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 304906175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 304906175 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 304906175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 20474163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 424290655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 749670992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166313 # Total number of read requests seen -system.physmem.writeReqs 114015 # Total number of write requests seen -system.physmem.cpureqs 280328 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 10644032 # Total number of bytes read from memory -system.physmem.bytesWritten 7296960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 10644032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 490496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10153472 # Number of bytes read from this memory +system.physmem.bytes_read::total 10643968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 490496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 490496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296640 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296640 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7664 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158648 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166312 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114010 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114010 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 19664794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 407069441 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 426734234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 19664794 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 19664794 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 292534333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 292534333 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 292534333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 19664794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 407069441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 719268568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166312 # Total number of read requests seen +system.physmem.writeReqs 114010 # Total number of write requests seen +system.physmem.cpureqs 280322 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 10643968 # Total number of bytes read from memory +system.physmem.bytesWritten 7296640 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 10643968 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296640 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 10648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 10525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 10321 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 10258 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 10407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 10349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 10491 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 10476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 10257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9976 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 10401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 10114 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 7242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 6837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 7024 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 7009 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 7276 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 10433 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 10460 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 10315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 10055 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 10429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 10401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 10323 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 10623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 10639 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 10547 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 10232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 10278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 10621 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 10623 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7257 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7176 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6941 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6990 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6966 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23931788000 # Total gap between requests +system.physmem.totGap 24942817000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 166313 # Categorize read packet sizes +system.physmem.readPktSize::6 166312 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 114015 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 67890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114010 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 73936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5644 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,12 +124,12 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 4387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see @@ -146,66 +146,208 @@ system.physmem.wrQLenPdf::18 4957 # Wh system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 7245305500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 9792324250 # Sum of mem lat for all requests -system.physmem.totBusLat 831555000 # Total cycles spent in databus access -system.physmem.totBankLat 1715463750 # Total cycles spent in bank access -system.physmem.avgQLat 43564.80 # Average queueing delay per request -system.physmem.avgBankLat 10314.79 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 49789 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 360.286489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.159256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 741.433360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 20689 41.55% 41.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 7785 15.64% 57.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4196 8.43% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 3037 6.10% 71.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 2069 4.16% 75.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1703 3.42% 79.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1326 2.66% 81.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 1152 2.31% 84.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 751 1.51% 85.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 622 1.25% 87.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 468 0.94% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 538 1.08% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 428 0.86% 89.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 311 0.62% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 271 0.54% 91.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 335 0.67% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 282 0.57% 92.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 173 0.35% 92.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 131 0.26% 92.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 297 0.60% 93.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 411 0.83% 94.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 172 0.35% 94.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 311 0.62% 95.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 639 1.28% 96.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 258 0.52% 97.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 81 0.16% 97.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 48 0.10% 97.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 163 0.33% 97.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 101 0.20% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 35 0.07% 97.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 33 0.07% 98.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 83 0.17% 98.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 54 0.11% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 28 0.06% 98.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 37 0.07% 98.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 43 0.09% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 20 0.04% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 23 0.05% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 20 0.04% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 10 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 11 0.02% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 8 0.02% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 16 0.03% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 8 0.02% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 7 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 17 0.03% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 7 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 10 0.02% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 8 0.02% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 7 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 8 0.02% 99.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 5 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 6 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 3 0.01% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 8 0.02% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 13 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 5 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 9 0.02% 99.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 5 0.01% 99.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 10 0.02% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 165 0.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 49789 # Bytes accessed per row activation +system.physmem.totQLat 6526905250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 8951626500 # Sum of mem lat for all requests +system.physmem.totBusLat 831550000 # Total cycles spent in databus access +system.physmem.totBankLat 1593171250 # Total cycles spent in bank access +system.physmem.avgQLat 39245.42 # Average queueing delay per request +system.physmem.avgBankLat 9579.53 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58879.59 # Average memory access latency -system.physmem.avgRdBW 444.76 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 304.91 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 444.76 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 304.91 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 53824.94 # Average memory access latency +system.physmem.avgRdBW 426.73 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 292.53 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 426.73 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 292.53 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 5.86 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.41 # Average read queue length over time -system.physmem.avgWrQLen 9.84 # Average write queue length over time -system.physmem.readRowHits 149147 # Number of row buffer hits during reads -system.physmem.writeRowHits 70867 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.16 # Row buffer hit rate for writes -system.physmem.avgGap 85370.67 # Average gap between requests -system.cpu.branchPred.lookups 16571170 # Number of BP lookups -system.cpu.branchPred.condPredicted 10694499 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 427048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11996955 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7368452 # Number of BTB hits +system.physmem.busUtil 5.62 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.36 # Average read queue length over time +system.physmem.avgWrQLen 10.09 # Average write queue length over time +system.physmem.readRowHits 154174 # Number of row buffer hits during reads +system.physmem.writeRowHits 76335 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.70 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.95 # Row buffer hit rate for writes +system.physmem.avgGap 88979.16 # Average gap between requests +system.membus.throughput 719268568 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 35517 # Transaction distribution +system.membus.trans_dist::ReadResp 35517 # Transaction distribution +system.membus.trans_dist::Writeback 114010 # Transaction distribution +system.membus.trans_dist::ReadExReq 130795 # Transaction distribution +system.membus.trans_dist::ReadExResp 130795 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 446634 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 446634 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17940608 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17940608 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1221780000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 1527507000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.1 # Layer utilization (%) +system.cpu.branchPred.lookups 16555988 # Number of BP lookups +system.cpu.branchPred.condPredicted 10692092 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 419935 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11595461 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7351910 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.419352 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1995064 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 41482 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 63.403344 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990234 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 41425 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22414538 # DTB read hits -system.cpu.dtb.read_misses 219003 # DTB read misses -system.cpu.dtb.read_acv 44 # DTB read access violations -system.cpu.dtb.read_accesses 22633541 # DTB read accesses -system.cpu.dtb.write_hits 15711620 # DTB write hits -system.cpu.dtb.write_misses 41172 # DTB write misses +system.cpu.dtb.read_hits 22410816 # DTB read hits +system.cpu.dtb.read_misses 219473 # DTB read misses +system.cpu.dtb.read_acv 42 # DTB read access violations +system.cpu.dtb.read_accesses 22630289 # DTB read accesses +system.cpu.dtb.write_hits 15705108 # DTB write hits +system.cpu.dtb.write_misses 41065 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 15752792 # DTB write accesses -system.cpu.dtb.data_hits 38126158 # DTB hits -system.cpu.dtb.data_misses 260175 # DTB misses -system.cpu.dtb.data_acv 46 # DTB access violations -system.cpu.dtb.data_accesses 38386333 # DTB accesses -system.cpu.itb.fetch_hits 13959521 # ITB hits -system.cpu.itb.fetch_misses 35718 # ITB misses +system.cpu.dtb.write_accesses 15746173 # DTB write accesses +system.cpu.dtb.data_hits 38115924 # DTB hits +system.cpu.dtb.data_misses 260538 # DTB misses +system.cpu.dtb.data_acv 44 # DTB access violations +system.cpu.dtb.data_accesses 38376462 # DTB accesses +system.cpu.itb.fetch_hits 13936543 # ITB hits +system.cpu.itb.fetch_misses 35109 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13995239 # ITB accesses +system.cpu.itb.fetch_accesses 13971652 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,139 +361,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 47863646 # number of cpu cycles simulated +system.cpu.numCycles 49885704 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15840434 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 105551509 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16571170 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9363516 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 19590320 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2026285 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6404003 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7727 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 314524 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13959521 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 209834 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43625903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.419469 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.136822 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15828757 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 105472202 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16555988 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9342144 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 19569330 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2015634 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7564714 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 312127 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13936543 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 209148 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44745227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.357172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.120107 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24035583 55.09% 55.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538195 3.53% 58.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1379254 3.16% 61.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1510848 3.46% 65.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4145444 9.50% 74.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1853786 4.25% 79.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 680324 1.56% 80.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070140 2.45% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7412329 16.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25175897 56.26% 56.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1533640 3.43% 59.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1372500 3.07% 62.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1510966 3.38% 66.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4145174 9.26% 75.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1852523 4.14% 79.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 674526 1.51% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069811 2.39% 83.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7410190 16.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43625903 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346216 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.205254 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16922417 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5946391 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18583818 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 809277 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1364000 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3756330 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 107588 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 103803150 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 305479 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1364000 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 17385205 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3661755 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 85469 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18882151 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2247323 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102504062 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 474 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2634 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2121433 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 61730148 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123523109 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123071072 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 452037 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44745227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.331878 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.114277 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16915257 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7099488 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18565359 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 807394 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1357729 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3748109 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 107416 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 103728039 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 304294 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1357729 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 17378057 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4787405 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 84706 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18857243 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2280087 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102449322 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 562 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2762 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2150788 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 61699088 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 123470125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123020099 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 450026 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9183267 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5533 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4628434 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23258454 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16285736 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1194307 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 458239 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90833658 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5326 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88506663 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 99992 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10775029 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4713260 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43625903 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.028764 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.109591 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9152207 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5534 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 4701242 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23248702 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16281518 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1196604 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 458974 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 90797694 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5272 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 88473068 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 98121 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10747304 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4709427 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 689 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44745227 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.977263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.106527 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15319091 35.11% 35.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 6943764 15.92% 51.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5619916 12.88% 63.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4753240 10.90% 74.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4687288 10.74% 85.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2648310 6.07% 91.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1927283 4.42% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1307141 3.00% 99.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 419870 0.96% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 16442789 36.75% 36.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 6947095 15.53% 52.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5617294 12.55% 64.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4751397 10.62% 75.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4688341 10.48% 85.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2649423 5.92% 91.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1924303 4.30% 96.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1305783 2.92% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 418802 0.94% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43625903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44745227 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 126036 6.75% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 786436 42.09% 48.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 955888 51.16% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 126164 6.77% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 785807 42.18% 48.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 951202 51.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49401565 55.82% 55.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43900 0.05% 55.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49382358 55.82% 55.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 43890 0.05% 55.87% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121291 0.14% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121091 0.14% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 38958 0.04% 56.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121219 0.14% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121003 0.14% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued @@ -373,84 +515,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.18% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22873159 25.84% 82.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15906558 17.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 22865563 25.84% 82.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 15899938 17.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88506663 # Type of FU issued -system.cpu.iq.rate 1.849142 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1868360 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021110 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 222003769 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101216135 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86588999 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 603812 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 415953 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 294156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90073048 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 301975 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1468681 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 88473068 # Type of FU issued +system.cpu.iq.rate 1.773515 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1863173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021059 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 223048793 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 101154216 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86567905 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 603864 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 414189 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 294216 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90034241 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 302000 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1467603 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2981816 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4834 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18324 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1672359 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2972064 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5071 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18375 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1668141 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2816 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 91767 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2922 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 100269 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1364000 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2689383 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 74209 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100326423 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 230599 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23258454 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16285736 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5326 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 60174 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 487 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18324 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 205931 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161115 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 367046 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87639637 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22636834 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 867026 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1357729 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3744152 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 78814 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100285943 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 219681 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23248702 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16281518 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5272 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 60147 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 593 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18375 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 199378 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 160408 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 359786 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 87617560 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22633363 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 855508 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9487439 # number of nop insts executed -system.cpu.iew.exec_refs 38389952 # number of memory reference insts executed -system.cpu.iew.exec_branches 15091410 # Number of branches executed -system.cpu.iew.exec_stores 15753118 # Number of stores executed -system.cpu.iew.exec_rate 1.831027 # Inst execution rate -system.cpu.iew.wb_sent 87274889 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86883155 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33355142 # num instructions producing a value -system.cpu.iew.wb_consumers 43763107 # num instructions consuming a value +system.cpu.iew.exec_nop 9482977 # number of nop insts executed +system.cpu.iew.exec_refs 38379854 # number of memory reference insts executed +system.cpu.iew.exec_branches 15087965 # Number of branches executed +system.cpu.iew.exec_stores 15746491 # Number of stores executed +system.cpu.iew.exec_rate 1.756366 # Inst execution rate +system.cpu.iew.wb_sent 87252732 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86862121 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33357056 # num instructions producing a value +system.cpu.iew.wb_consumers 43763173 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.815222 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762175 # average fanout of values written-back +system.cpu.iew.wb_rate 1.741223 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.762217 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8976597 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8947131 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 322215 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42261903 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.090315 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.803165 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 315269 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43387498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.036086 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.786442 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19374336 45.84% 45.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7031479 16.64% 62.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3426891 8.11% 70.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2063946 4.88% 75.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2064090 4.88% 80.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1160431 2.75% 83.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1098411 2.60% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 723960 1.71% 87.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5318359 12.58% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 20491808 47.23% 47.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7040185 16.23% 63.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3430647 7.91% 71.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2065344 4.76% 76.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2060078 4.75% 80.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1160326 2.67% 83.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1096269 2.53% 86.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 719123 1.66% 87.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5323718 12.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42261903 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43387498 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,192 +603,212 @@ system.cpu.commit.branches 13754477 # Nu system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5318359 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5323718 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 132943471 # The number of ROB reads -system.cpu.rob.rob_writes 196001226 # The number of ROB writes -system.cpu.timesIdled 70501 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 4237743 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 134034241 # The number of ROB reads +system.cpu.rob.rob_writes 195936054 # The number of ROB writes +system.cpu.timesIdled 84426 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5140477 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.601364 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.601364 # CPI: Total CPI of All Threads -system.cpu.ipc 1.662885 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.662885 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 115989230 # number of integer regfile reads -system.cpu.int_regfile_writes 57546941 # number of integer regfile writes -system.cpu.fp_regfile_reads 249538 # number of floating regfile reads -system.cpu.fp_regfile_writes 239891 # number of floating regfile writes -system.cpu.misc_regfile_reads 38020 # number of misc regfile reads +system.cpu.cpi 0.626770 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.626770 # CPI: Total CPI of All Threads +system.cpu.ipc 1.595482 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.595482 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 115957750 # number of integer regfile reads +system.cpu.int_regfile_writes 57532597 # number of integer regfile writes +system.cpu.fp_regfile_reads 249573 # number of floating regfile reads +system.cpu.fp_regfile_writes 239887 # number of floating regfile writes +system.cpu.misc_regfile_reads 38017 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 91116 # number of replacements -system.cpu.icache.tagsinuse 1928.908016 # Cycle average of tags in use -system.cpu.icache.total_refs 13854125 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 93164 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 148.706850 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 19689670000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1928.908016 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.941850 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.941850 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 13854125 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13854125 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13854125 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13854125 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13854125 # number of overall hits -system.cpu.icache.overall_hits::total 13854125 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 105395 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 105395 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 105395 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 105395 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 105395 # number of overall misses -system.cpu.icache.overall_misses::total 105395 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1863166499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1863166499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1863166499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1863166499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1863166499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1863166499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13959520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13959520 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13959520 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13959520 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13959520 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13959520 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007550 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007550 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007550 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007550 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007550 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007550 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.940120 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17677.940120 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.940120 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17677.940120 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.940120 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17677.940120 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 817 # number of cycles access was blocked +system.cpu.toL2Bus.throughput 1201112463 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 155760 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 155759 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143412 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 187195 # 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number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166314 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 406509618 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1270706940 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1677216558 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10579175855 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10579175855 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406509618 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11849882795 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12256392413 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406509618 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11849882795 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12256392413 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082188 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448038 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.228627 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912075 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912075 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082188 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771727 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556696 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912023 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.081893 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771732 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.555911 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.081893 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771732 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.555911 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69542.857143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63490.844792 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64796.905794 # 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number of replacements -system.cpu.dcache.tagsinuse 4076.541723 # Cycle average of tags in use -system.cpu.dcache.total_refs 34211115 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 205587 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 166.406996 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 178802000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4076.541723 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.995249 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.995249 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 20636989 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20636989 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13574068 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13574068 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 58 # 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number of replacements +system.cpu.dcache.tagsinuse 4074.502987 # Cycle average of tags in use +system.cpu.dcache.total_refs 34204494 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 205574 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 166.385311 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 214402000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4074.502987 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994752 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994752 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 20630348 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20630348 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13574089 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13574089 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # 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number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 58 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35517552 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35517552 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35517552 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35517552 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012781 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012781 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036784 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036784 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036784 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036784 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45045.363530 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 45045.363530 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76081.403874 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76081.403874 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69734.348986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69734.348986 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4381626 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 112316 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35510616 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35510616 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35510616 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35510616 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012772 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012772 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071119 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071119 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036783 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036783 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036783 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036783 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58582.685441 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58582.685441 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86560.535625 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 86560.535625 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80843.833387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80843.833387 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5220473 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 159 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 112927 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.011592 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.228741 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 159 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168939 # number of writebacks -system.cpu.dcache.writebacks::total 168939 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205002 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 205002 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895906 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 895906 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1100908 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1100908 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1100908 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1100908 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62184 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62184 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143403 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143403 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205587 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205587 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205587 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205587 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2020761500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2020761500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12440224991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12440224991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14460986491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14460986491 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14460986491 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14460986491 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168941 # number of writebacks +system.cpu.dcache.writebacks::total 168941 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204728 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 204728 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895877 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 895877 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1100605 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1100605 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1100605 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1100605 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62163 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62163 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143411 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143411 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 205574 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205574 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205574 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205574 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2517427002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2517427002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14256184493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14256184493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16773611495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16773611495 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16773611495 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16773611495 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005788 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005788 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32496.486234 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32496.486234 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86750.102794 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86750.102794 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40497.192896 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40497.192896 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99407.887073 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99407.887073 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index e11282e38..db9503e0b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2426632 # Simulator instruction rate (inst/s) -host_op_rate 2426631 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1214706702 # Simulator tick rate (ticks/s) -host_mem_usage 272072 # Number of bytes of host memory used -host_seconds 36.40 # Real time elapsed on the host +host_inst_rate 2564036 # Simulator instruction rate (inst/s) +host_op_rate 2564035 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1283487470 # Simulator tick rate (ticks/s) +host_mem_usage 224620 # Number of bytes of host memory used +host_seconds 34.45 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 2072610067 # Wr system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 12937468537 # Throughput (bytes/s) +system.membus.data_through_bus 572107835 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index a53da63fa..9b4737e22 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu sim_ticks 133634727000 # Number of ticks simulated final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 996502 # Simulator instruction rate (inst/s) -host_op_rate 996501 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1507427540 # Simulator tick rate (ticks/s) -host_mem_usage 280652 # Number of bytes of host memory used -host_seconds 88.65 # Real time elapsed on the host +host_inst_rate 671194 # Simulator instruction rate (inst/s) +host_op_rate 671194 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1015328507 # Simulator tick rate (ticks/s) +host_mem_usage 233108 # Number of bytes of host memory used +host_seconds 131.62 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 54587966 # To system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 133682617 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 34272 # Transaction distribution +system.membus.trans_dist::ReadResp 34272 # Transaction distribution +system.membus.trans_dist::Writeback 113982 # Transaction distribution +system.membus.trans_dist::ReadExReq 130881 # Transaction distribution +system.membus.trans_dist::ReadExResp 130881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 444288 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 17864640 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -405,5 +421,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 215108158 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 152872 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577063 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 729935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 4891904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23854016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 28745920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 5f2b5197b..419a13ff5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.025535 # Number of seconds simulated -sim_ticks 25534556000 # Number of ticks simulated -final_tick 25534556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.026649 # Number of seconds simulated +sim_ticks 26649062500 # Number of ticks simulated +final_tick 26649062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 124211 # Simulator instruction rate (inst/s) -host_op_rate 176271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44729688 # Simulator tick rate (ticks/s) -host_mem_usage 254184 # Number of bytes of host memory used -host_seconds 570.86 # Real time elapsed on the host +host_inst_rate 95593 # Simulator instruction rate (inst/s) +host_op_rate 135659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35926621 # Simulator tick rate (ticks/s) +host_mem_usage 255136 # Number of bytes of host memory used +host_seconds 741.76 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 297536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7943488 # Number of bytes read from this memory -system.physmem.bytes_read::total 8241024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 297536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 297536 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory -system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4649 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124117 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128766 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 11652288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 311087767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 322740055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 11652288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 11652288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 210400369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 210400369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 210400369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 11652288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 311087767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 533140424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128767 # Total number of read requests seen -system.physmem.writeReqs 83945 # Total number of write requests seen -system.physmem.cpureqs 213037 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 8241024 # Total number of bytes read from memory -system.physmem.bytesWritten 5372480 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 8241024 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 5372480 # bytesWritten derated as per pkt->getSize() +system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory +system.physmem.bytes_read::total 8240768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory +system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128762 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 11193790 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 298039152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 309232942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 11193790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 11193790 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 201613096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 201613096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 201613096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 11193790 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 298039152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 510846038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128763 # Total number of read requests seen +system.physmem.writeReqs 83950 # Total number of write requests seen +system.physmem.cpureqs 213025 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 8240768 # Total number of bytes read from memory +system.physmem.bytesWritten 5372800 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 8240768 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 5372800 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 325 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 7974 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 8181 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 8060 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8166 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 8116 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 8007 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8002 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 7985 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 8125 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 8030 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 7988 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 7949 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 5143 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 5260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 5374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5312 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 8141 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 8383 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 8250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8168 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 8450 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 8090 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 7962 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8062 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 7609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 7789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 7813 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 7880 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 7885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 7974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8005 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 5180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 5377 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 5289 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 5268 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 5208 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5031 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5089 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 5145 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 5343 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 25534539500 # Total gap between requests +system.physmem.totGap 26649044000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 128767 # Categorize read packet sizes +system.physmem.readPktSize::6 128763 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 83945 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 70152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2075 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 83950 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 75538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,11 +124,11 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3648 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see @@ -142,50 +142,196 @@ system.physmem.wrQLenPdf::14 3650 # Wh system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 3209361000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 5253486000 # Sum of mem lat for all requests -system.physmem.totBusLat 643825000 # Total cycles spent in databus access -system.physmem.totBankLat 1400300000 # Total cycles spent in bank access -system.physmem.avgQLat 24924.17 # Average queueing delay per request -system.physmem.avgBankLat 10874.85 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 40799.02 # Average memory access latency -system.physmem.avgRdBW 322.74 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 210.40 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 322.74 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 210.40 # Average consumed write bandwidth in MB/s +system.physmem.bytesPerActivate::samples 34891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 390.104497 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.978164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 858.430673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 13421 38.47% 38.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 5383 15.43% 53.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 3065 8.78% 62.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2226 6.38% 69.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1625 4.66% 73.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1388 3.98% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 1071 3.07% 80.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 870 2.49% 83.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 590 1.69% 84.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 488 1.40% 86.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 448 1.28% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 588 1.69% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 296 0.85% 90.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 306 0.88% 91.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 186 0.53% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 205 0.59% 92.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 126 0.36% 92.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 210 0.60% 93.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 103 0.30% 93.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 233 0.67% 94.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 114 0.33% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 336 0.96% 95.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 140 0.40% 95.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 305 0.87% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 63 0.18% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 139 0.40% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 46 0.13% 97.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 83 0.24% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 24 0.07% 97.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 56 0.16% 97.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 58 0.17% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 11 0.03% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 27 0.08% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 19 0.05% 98.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 23 0.07% 98.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 10 0.03% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 17 0.05% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 8 0.02% 98.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 14 0.04% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 16 0.05% 98.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 16 0.05% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 9 0.03% 98.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 15 0.04% 98.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 7 0.02% 98.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 7 0.02% 98.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 12 0.03% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 11 0.03% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 7 0.02% 98.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 3 0.01% 98.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 9 0.03% 98.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 3 0.01% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 7 0.02% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.01% 98.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.01% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 7 0.02% 98.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 2 0.01% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 5 0.01% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.01% 98.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 4 0.01% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.00% 98.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 3 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 7 0.02% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.01% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.00% 98.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 3 0.01% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 1 0.00% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 3 0.01% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 4 0.01% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 4 0.01% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 2 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 2 0.01% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.01% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 2 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 2 0.01% 99.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 3 0.01% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 3 0.01% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 3 0.01% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 3 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 2 0.01% 99.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 2 0.01% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 2 0.01% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 4 0.01% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 238 0.68% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 34891 # Bytes accessed per row activation +system.physmem.totQLat 2799338750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4801886250 # Sum of mem lat for all requests +system.physmem.totBusLat 643800000 # Total cycles spent in databus access +system.physmem.totBankLat 1358747500 # Total cycles spent in bank access +system.physmem.avgQLat 21740.58 # Average queueing delay per request +system.physmem.avgBankLat 10552.48 # Average bank access latency per request +system.physmem.avgBusLat 4999.96 # Average bus latency per request +system.physmem.avgMemAccLat 37293.02 # Average memory access latency +system.physmem.avgRdBW 309.23 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 201.61 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 309.23 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 201.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 4.17 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.21 # Average read queue length over time -system.physmem.avgWrQLen 9.90 # Average write queue length over time -system.physmem.readRowHits 116738 # Number of row buffer hits during reads -system.physmem.writeRowHits 52892 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.01 # Row buffer hit rate for writes -system.physmem.avgGap 120042.78 # Average gap between requests -system.cpu.branchPred.lookups 16612549 # Number of BP lookups -system.cpu.branchPred.condPredicted 12751503 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 599939 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10534593 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7757405 # Number of BTB hits +system.physmem.busUtil 3.99 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.18 # Average read queue length over time +system.physmem.avgWrQLen 10.01 # Average write queue length over time +system.physmem.readRowHits 120254 # Number of row buffer hits during reads +system.physmem.writeRowHits 57565 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.39 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 68.57 # Row buffer hit rate for writes +system.physmem.avgGap 125281.69 # Average gap between requests +system.membus.throughput 510846038 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 26509 # Transaction distribution +system.membus.trans_dist::ReadResp 26508 # Transaction distribution +system.membus.trans_dist::Writeback 83950 # Transaction distribution +system.membus.trans_dist::UpgradeReq 312 # Transaction distribution +system.membus.trans_dist::UpgradeResp 312 # Transaction distribution +system.membus.trans_dist::ReadExReq 102254 # Transaction distribution +system.membus.trans_dist::ReadExResp 102254 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 342099 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 342099 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13613568 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 13613568 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13613568 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 926784500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1200135938 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 4.5 # Layer utilization (%) +system.cpu.branchPred.lookups 16620839 # Number of BP lookups +system.cpu.branchPred.condPredicted 12757336 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 602395 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10635009 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7765773 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.637444 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1822464 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 113740 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 73.020841 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1824331 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 113161 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,136 +375,136 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 51069113 # number of cpu cycles simulated +system.cpu.numCycles 53298126 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12514697 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85141272 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16612549 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9579869 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21174766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2353264 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 10532727 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 498 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11663165 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 178973 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 45949088 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.594403 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.336122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12535190 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 85154971 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16620839 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9590104 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21184086 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2355794 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10829442 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 551 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11674707 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 181091 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46276167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.576733 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.331391 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24794811 53.96% 53.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2137100 4.65% 58.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1960912 4.27% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2040333 4.44% 67.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1467005 3.19% 70.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1375299 2.99% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 957293 2.08% 75.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1188429 2.59% 78.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10027906 21.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25111993 54.27% 54.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2139332 4.62% 58.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1963886 4.24% 63.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2043329 4.42% 67.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1467358 3.17% 70.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1375070 2.97% 73.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 956833 2.07% 75.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1188482 2.57% 78.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10029884 21.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 45949088 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.325295 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.667177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14598304 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8880725 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19456140 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1390682 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1623237 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3327841 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 105063 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116768795 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 361627 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1623237 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16304724 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2541710 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 873068 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19090805 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5515544 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 114897326 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 145 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 17204 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4661371 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115217977 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 529361609 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 529355204 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6405 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46276167 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.311847 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.597710 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14619512 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9177970 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19466340 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1388431 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1623914 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3328977 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 104776 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116789336 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 361687 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1623914 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16330804 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2680643 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1000847 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19093672 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5546287 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 114905556 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 219 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 17136 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4693151 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1312 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115218637 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 529387920 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 529379803 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8117 # Number of floating rename lookups system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16085305 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 20097 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 20095 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13032825 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29592002 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22430174 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3871274 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4372916 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111465960 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 35763 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 107205680 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272682 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10729594 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 25689497 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1977 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 45949088 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.333141 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.988541 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 16085965 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 20302 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 20297 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13065620 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29609265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22417131 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3885027 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4397806 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 111472584 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35916 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 107208843 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 271699 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10738438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 25737967 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2130 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46276167 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.316718 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.989507 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10727082 23.35% 23.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8071187 17.57% 40.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7423916 16.16% 57.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7121409 15.50% 72.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5405071 11.76% 84.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3914661 8.52% 92.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1842461 4.01% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 872329 1.90% 98.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 570972 1.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11020528 23.81% 23.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8094858 17.49% 41.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7429249 16.05% 57.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7154901 15.46% 72.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5386733 11.64% 84.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3906460 8.44% 92.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1842144 3.98% 96.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 871664 1.88% 98.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 569630 1.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 45949088 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46276167 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112030 4.53% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1365113 55.14% 59.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 998480 40.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 112593 4.57% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1348878 54.73% 59.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1003122 40.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 56613296 52.81% 52.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91558 0.09% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 56608598 52.80% 52.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91438 0.09% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 214 0.00% 52.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued @@ -384,84 +530,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 28880685 26.94% 79.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21619920 20.17% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 28894537 26.95% 79.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21614012 20.16% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 107205680 # Type of FU issued -system.cpu.iq.rate 2.099227 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2475625 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023092 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 263108167 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 122259769 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 105531182 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 588 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 948 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 171 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 109681012 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2183832 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 107208843 # Type of FU issued +system.cpu.iq.rate 2.011494 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2464595 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.022989 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 263429476 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 122274650 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 105524045 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 671 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1168 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 196 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 109673111 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2189921 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2284894 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30581 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1874436 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2302157 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6684 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29801 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1861393 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 495 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 27 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 724 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1623237 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1048241 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 45255 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 111511491 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 294294 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29592002 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22430174 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19843 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6298 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5233 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30581 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 389128 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 180293 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 569421 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 106181674 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28584421 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1024006 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1623914 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1145014 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 48197 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 111518283 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 295309 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29609265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22417131 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 19996 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6449 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 5406 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29801 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 392238 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 181031 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 573269 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 106181942 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28595303 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1026901 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9768 # number of nop insts executed -system.cpu.iew.exec_refs 49919693 # number of memory reference insts executed -system.cpu.iew.exec_branches 14596236 # Number of branches executed -system.cpu.iew.exec_stores 21335272 # Number of stores executed -system.cpu.iew.exec_rate 2.079176 # Inst execution rate -system.cpu.iew.wb_sent 105750982 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 105531353 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53247115 # num instructions producing a value -system.cpu.iew.wb_consumers 103478594 # num instructions consuming a value +system.cpu.iew.exec_nop 9783 # number of nop insts executed +system.cpu.iew.exec_refs 49924361 # number of memory reference insts executed +system.cpu.iew.exec_branches 14597950 # Number of branches executed +system.cpu.iew.exec_stores 21329058 # Number of stores executed +system.cpu.iew.exec_rate 1.992227 # Inst execution rate +system.cpu.iew.wb_sent 105744224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 105524241 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53247487 # num instructions producing a value +system.cpu.iew.wb_consumers 103444790 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.066442 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514571 # average fanout of values written-back +system.cpu.iew.wb_rate 1.979887 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.514743 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10879947 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10886753 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 496884 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 44325851 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.270288 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.765576 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 499558 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 44652253 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.253692 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.763005 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 15270109 34.45% 34.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11622339 26.22% 60.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3461273 7.81% 68.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2876315 6.49% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1875935 4.23% 79.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1955485 4.41% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 687541 1.55% 85.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 562645 1.27% 86.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6014209 13.57% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15559873 34.85% 34.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11688259 26.18% 61.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3454288 7.74% 68.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2872185 6.43% 75.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1868727 4.19% 79.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1932277 4.33% 83.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 683931 1.53% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 562545 1.26% 86.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6030168 13.50% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 44325851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 44652253 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -472,204 +618,226 @@ system.cpu.commit.branches 13741485 # Nu system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6014209 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6030168 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 149798718 # The number of ROB reads -system.cpu.rob.rob_writes 224657070 # The number of ROB writes -system.cpu.timesIdled 74104 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5120025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 150115967 # The number of ROB reads +system.cpu.rob.rob_writes 224671489 # The number of ROB writes +system.cpu.timesIdled 79206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7021959 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated -system.cpu.cpi 0.720220 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.720220 # CPI: Total CPI of All Threads -system.cpu.ipc 1.388464 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.388464 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 511419502 # number of integer regfile reads -system.cpu.int_regfile_writes 103305182 # number of integer regfile writes -system.cpu.fp_regfile_reads 846 # number of floating regfile reads -system.cpu.fp_regfile_writes 738 # number of floating regfile writes -system.cpu.misc_regfile_reads 49163804 # number of misc regfile reads +system.cpu.cpi 0.751656 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.751656 # CPI: Total CPI of All Threads +system.cpu.ipc 1.330396 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.330396 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 511415343 # number of integer regfile reads +system.cpu.int_regfile_writes 103300902 # number of integer regfile writes +system.cpu.fp_regfile_reads 1012 # number of floating regfile reads +system.cpu.fp_regfile_writes 876 # number of floating regfile writes +system.cpu.misc_regfile_reads 49160884 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.icache.replacements 28595 # number of replacements -system.cpu.icache.tagsinuse 1814.564534 # Cycle average of tags in use -system.cpu.icache.total_refs 11628419 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 30629 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 379.653890 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 776266857 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 87116 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 87115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 129077 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 62962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454559 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 517521 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1998208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18655488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 20653696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 20653696 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 33088 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 290859995 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 47617981 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 243817935 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.icache.replacements 29381 # number of replacements +system.cpu.icache.tagsinuse 1810.408207 # Cycle average of tags in use +system.cpu.icache.total_refs 11639182 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 31418 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 370.462219 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.564534 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.886018 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.886018 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11628429 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11628429 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11628429 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11628429 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11628429 # number of overall hits -system.cpu.icache.overall_hits::total 11628429 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 34736 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 34736 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 34736 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 34736 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 34736 # number of overall misses -system.cpu.icache.overall_misses::total 34736 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 739850999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 739850999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 739850999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 739850999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 739850999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 739850999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11663165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11663165 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11663165 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11663165 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11663165 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11663165 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002978 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002978 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002978 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002978 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002978 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002978 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21299.257226 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21299.257226 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21299.257226 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21299.257226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21299.257226 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21299.257226 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1371 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1810.408207 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.883988 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.883988 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11639193 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11639193 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11639193 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 845054999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 845054999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11674706 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11674706 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11674706 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11674706 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11674706 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11674706 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003042 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003042 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003042 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003042 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003042 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003042 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23795.652268 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23795.652268 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23795.652268 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23795.652268 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1082 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # 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number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3776 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3776 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30960 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 30960 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 30960 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 30960 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 30960 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 30960 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 598675499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 598675499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 598675499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 598675499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 598675499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 598675499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002655 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002655 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002655 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19337.063921 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19337.063921 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19337.063921 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19337.063921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19337.063921 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19337.063921 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31740 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 31740 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 31740 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 31740 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 31740 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 31740 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 686303518 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 686303518 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 686303518 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 686303518 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 686303518 # 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average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21622.669124 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 95632 # number of replacements -system.cpu.l2cache.tagsinuse 30087.760177 # Cycle average of tags in use -system.cpu.l2cache.total_refs 88021 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 126747 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.694462 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 95633 # number of replacements +system.cpu.l2cache.tagsinuse 29922.978563 # Cycle average of tags in use +system.cpu.l2cache.total_refs 88824 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 126744 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.700814 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 26926.191457 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1374.986838 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1786.581881 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.821722 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.041961 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.054522 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.918206 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 25771 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33436 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71752.121921 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68911.961879 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68911.961879 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158300 # number of replacements -system.cpu.dcache.tagsinuse 4072.274733 # Cycle average of tags in use -system.cpu.dcache.total_refs 44344926 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162396 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 273.066615 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 284501000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4072.274733 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994208 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994208 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 26045310 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 26045310 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18267055 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18267055 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15985 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15985 # number of LoadLockedReq hits +system.cpu.dcache.replacements 158319 # number of replacements +system.cpu.dcache.tagsinuse 4069.477080 # Cycle average of tags in use +system.cpu.dcache.total_refs 44347755 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162415 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 273.052089 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 350225000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4069.477080 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.993525 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.993525 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26048553 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26048553 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18266688 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18266688 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15980 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15980 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 44312365 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 44312365 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 44312365 # number of overall hits -system.cpu.dcache.overall_hits::total 44312365 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 124675 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 124675 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1582846 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1582846 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1707521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1707521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1707521 # number of overall misses -system.cpu.dcache.overall_misses::total 1707521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4257063500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4257063500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 98390759981 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 98390759981 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 860000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 860000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102647823481 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102647823481 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102647823481 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102647823481 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 26169985 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 26169985 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 44315241 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44315241 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44315241 # number of overall hits +system.cpu.dcache.overall_hits::total 44315241 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 125407 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 125407 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1583213 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1583213 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1708620 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1708620 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1708620 # number of overall misses +system.cpu.dcache.overall_misses::total 1708620 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5134620500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5134620500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 123147327479 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 123147327479 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 951500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 951500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 128281947979 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 128281947979 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 128281947979 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 128281947979 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26173960 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26173960 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16024 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 16024 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46019886 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46019886 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46019886 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46019886 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079741 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079741 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002621 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002621 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037104 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037104 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037104 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037104 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34145.285743 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34145.285743 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62160.665018 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62160.665018 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20476.190476 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20476.190476 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60115.116289 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60115.116289 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3743 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 131 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.572519 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 46023861 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46023861 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46023861 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46023861 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004791 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004791 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002746 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002746 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037125 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037125 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037125 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037125 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40943.651471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40943.651471 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77783.170981 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77783.170981 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21625 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21625 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75079.273319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75079.273319 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5184 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1288 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.751724 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 80.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 129075 # number of writebacks -system.cpu.dcache.writebacks::total 129075 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69278 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69278 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475504 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1475504 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # 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number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162739 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878555500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878555500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6809217490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6809217490 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8687772990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8687772990 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8687772990 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8687772990 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 129077 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10709332055 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10709332055 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10709332055 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10709332055 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33910.780367 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33910.780367 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.792439 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.792439 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.773918 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.773918 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78876.243711 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78876.243711 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 0248ad642..9f4bab8c0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932157000 # Number of ticks simulated final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1242714 # Simulator instruction rate (inst/s) -host_op_rate 1763527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 945130731 # Simulator tick rate (ticks/s) -host_mem_usage 286616 # Number of bytes of host memory used -host_seconds 57.06 # Real time elapsed on the host +host_inst_rate 2080365 # Simulator instruction rate (inst/s) +host_op_rate 2952231 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1582195312 # Simulator tick rate (ticks/s) +host_mem_usage 241268 # Number of bytes of host memory used +host_seconds 34.09 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 100632428 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1458502967 # Wr system.physmem.bw_total::cpu.inst 5795805126 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3434566060 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9230371187 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9230371187 # Throughput (bytes/s) +system.membus.data_through_bus 497813828 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index ddc9fbf9d..9c1dc992d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.132689 # Nu sim_ticks 132689045000 # Number of ticks simulated final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 652363 # Simulator instruction rate (inst/s) -host_op_rate 925068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1230026759 # Simulator tick rate (ticks/s) -host_mem_usage 295072 # Number of bytes of host memory used -host_seconds 107.88 # Real time elapsed on the host +host_inst_rate 438025 # Simulator instruction rate (inst/s) +host_op_rate 621131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 825892843 # Simulator tick rate (ticks/s) +host_mem_usage 249772 # Number of bytes of host memory used +host_seconds 160.66 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 40471887 # To system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 102119538 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 25532 # Transaction distribution +system.membus.trans_dist::ReadResp 25532 # Transaction distribution +system.membus.trans_dist::Writeback 83909 # Transaction distribution +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 339533 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 339533 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13550144 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 148145463 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 37816 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 448235 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 486051 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1210112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18447168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 19657280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 4cce8cf2a..0c3e0f3fc 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu sim_ticks 68148672000 # Number of ticks simulated final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2091817 # Simulator instruction rate (inst/s) -host_op_rate 2118902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1060681468 # Simulator tick rate (ticks/s) -host_mem_usage 281256 # Number of bytes of host memory used -host_seconds 64.25 # Real time elapsed on the host +host_inst_rate 2813738 # Simulator instruction rate (inst/s) +host_op_rate 2850169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1426739476 # Simulator tick rate (ticks/s) +host_mem_usage 233072 # Number of bytes of host memory used +host_seconds 47.77 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory @@ -35,6 +35,9 @@ system.physmem.bw_write::total 1318924454 # Wr system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11383698247 # Throughput (bytes/s) +system.membus.data_through_bus 775783918 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 136297345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 97e5107ce..4b553d931 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.202242 # Nu sim_ticks 202242260000 # Number of ticks simulated final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1033030 # Simulator instruction rate (inst/s) -host_op_rate 1046406 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1554493166 # Simulator tick rate (ticks/s) -host_mem_usage 289840 # Number of bytes of host memory used -host_seconds 130.10 # Real time elapsed on the host +host_inst_rate 840510 # Simulator instruction rate (inst/s) +host_op_rate 851393 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1264790801 # Simulator tick rate (ticks/s) +host_mem_usage 241580 # Number of bytes of host memory used +host_seconds 159.90 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 26223758 # To system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 67847660 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 30277 # Transaction distribution +system.membus.trans_dist::ReadResp 30277 # Transaction distribution +system.membus.trans_dist::Writeback 82868 # Transaction distribution +system.membus.trans_dist::ReadExReq 101256 # Transaction distribution +system.membus.trans_dist::ReadExResp 101256 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 345934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 345934 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 13721664 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 404484520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -393,5 +409,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 146097102 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374048 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 425326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 799374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11969536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 17577472 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 29547008 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index e0742a983..24ed3058e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,102 +1,102 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.993430 # Number of seconds simulated -sim_ticks 993429839500 # Number of ticks simulated -final_tick 993429839500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.015958 # Number of seconds simulated +sim_ticks 1015958135500 # Number of ticks simulated +final_tick 1015958135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61068 # Simulator instruction rate (inst/s) -host_op_rate 61068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33337374 # Simulator tick rate (ticks/s) -host_mem_usage 271484 # Number of bytes of host memory used -host_seconds 29799.28 # Real time elapsed on the host +host_inst_rate 102863 # Simulator instruction rate (inst/s) +host_op_rate 102863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57427110 # Simulator tick rate (ticks/s) +host_mem_usage 225152 # Number of bytes of host memory used +host_seconds 17691.26 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory -system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125365184 # Number of bytes read from this memory +system.physmem.bytes_read::total 125420160 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65155584 # Number of bytes written to this memory -system.physmem.bytes_written::total 65155584 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory +system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018056 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018056 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 55340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 126194172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 126249512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 55340 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 55340 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 65586498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 65586498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 65586498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 55340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 126194172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 191836009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1959688 # Total number of read requests seen -system.physmem.writeReqs 1018056 # Total number of write requests seen -system.physmem.cpureqs 2977747 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125420032 # Total number of bytes read from memory -system.physmem.bytesWritten 65155584 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65155584 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 583 # Number of read reqs serviced by write Q +system.physmem.num_reads::cpu.data 1958831 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1959690 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 54112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 123396014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 123450126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 54112 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 54112 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 64132280 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 64132280 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 64132280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 54112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 123396014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 187582407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1959690 # Total number of read requests seen +system.physmem.writeReqs 1018058 # Total number of write requests seen +system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125420160 # Total number of bytes read from memory +system.physmem.bytesWritten 65155712 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125420160 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 578 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122178 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 121799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 121645 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 123762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123293 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122178 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 121053 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 121887 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 121114 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125176 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 123788 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 122723 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 123934 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63764 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 64028 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63369 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 63391 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63723 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63292 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 63646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64277 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 116204 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 117698 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 117773 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 117508 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 119859 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 124486 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 126960 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 130063 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 128617 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 130264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 125937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 125207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122563 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123183 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61224 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 61467 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 60558 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 61216 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 61647 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63085 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 64137 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 65614 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 65334 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 65770 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65297 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 65611 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64203 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 64552 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64187 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry -system.physmem.totGap 993429787500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1015958077500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1959688 # Categorize read packet sizes +system.physmem.readPktSize::6 1959690 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1018056 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1630073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 205372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 87756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018058 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1654417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 206034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 74348 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -124,15 +124,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 41526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 42719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44264 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see @@ -147,65 +147,214 @@ system.physmem.wrQLenPdf::19 44263 # Wh system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see -system.physmem.totQLat 35756114000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 104195196500 # Sum of mem lat for all requests -system.physmem.totBusLat 9795525000 # Total cycles spent in databus access -system.physmem.totBankLat 58643557500 # Total cycles spent in bank access -system.physmem.avgQLat 18251.25 # Average queueing delay per request -system.physmem.avgBankLat 29933.85 # Average bank access latency per request +system.physmem.wrQLenPdf::23 1545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1724238 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.484683 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.063313 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.326643 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1380958 80.09% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 190861 11.07% 91.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 56628 3.28% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 27570 1.60% 96.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15749 0.91% 96.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10044 0.58% 97.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6620 0.38% 97.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6559 0.38% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3696 0.21% 98.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 2923 0.17% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2676 0.16% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2682 0.16% 99.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1400 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1070 0.06% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1040 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 917 0.05% 99.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 816 0.05% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 821 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 760 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 561 0.03% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 626 0.04% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 841 0.05% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3634 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 546 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 235 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 177 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 137 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 143 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 89 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 86 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 92 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 67 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 60 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 57 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 45 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 52 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 29 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 31 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 19 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 27 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 23 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 16 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 31 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 31 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 24 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 13 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 19 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 18 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 23 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 24 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 19 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 13 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 24 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 11 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 18 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 9 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 19 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 19 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 20 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 7 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 14 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 14 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 18 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 115 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 10 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 19 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 14 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1430 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1724238 # Bytes accessed per row activation +system.physmem.totQLat 33987005500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 98689973000 # Sum of mem lat for all requests +system.physmem.totBusLat 9795560000 # Total cycles spent in databus access +system.physmem.totBankLat 54907407500 # Total cycles spent in bank access +system.physmem.avgQLat 17348.17 # Average queueing delay per request +system.physmem.avgBankLat 28026.68 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 53185.10 # Average memory access latency -system.physmem.avgRdBW 126.25 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 65.59 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 126.25 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 65.59 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 50374.85 # Average memory access latency +system.physmem.avgRdBW 123.45 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 64.13 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 123.45 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 64.13 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 1.50 # Data bus utilization in percentage +system.physmem.busUtil 1.47 # Data bus utilization in percentage system.physmem.avgRdQLen 0.10 # Average read queue length over time -system.physmem.avgWrQLen 10.25 # Average write queue length over time -system.physmem.readRowHits 770910 # Number of row buffer hits during reads -system.physmem.writeRowHits 285915 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.08 # Row buffer hit rate for writes -system.physmem.avgGap 333618.27 # Average gap between requests -system.cpu.branchPred.lookups 326686623 # Number of BP lookups -system.cpu.branchPred.condPredicted 252728421 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 138236618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 220072192 # Number of BTB lookups -system.cpu.branchPred.BTBHits 135769528 # Number of BTB hits +system.physmem.avgWrQLen 10.57 # Average write queue length over time +system.physmem.readRowHits 900967 # Number of row buffer hits during reads +system.physmem.writeRowHits 351956 # Number of row buffer hits during writes +system.physmem.readRowHitRate 45.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.57 # Row buffer hit rate for writes +system.physmem.avgGap 341183.36 # Average gap between requests +system.membus.throughput 187582407 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178392 # Transaction distribution +system.membus.trans_dist::ReadResp 1178392 # Transaction distribution +system.membus.trans_dist::Writeback 1018058 # Transaction distribution +system.membus.trans_dist::ReadExReq 781298 # Transaction distribution +system.membus.trans_dist::ReadExResp 781298 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4937438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4937438 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575872 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190575872 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575872 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11748266000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 18466425750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.cpu.branchPred.lookups 326521750 # Number of BP lookups +system.cpu.branchPred.condPredicted 252556520 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 138229412 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 220084071 # Number of BTB lookups +system.cpu.branchPred.BTBHits 135399986 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 61.693177 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 61.521938 # BTB Hit Percentage system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444795652 # DTB read hits +system.cpu.dtb.read_hits 444838557 # DTB read hits system.cpu.dtb.read_misses 4897078 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449692730 # DTB read accesses -system.cpu.dtb.write_hits 160833314 # DTB write hits +system.cpu.dtb.read_accesses 449735635 # DTB read accesses +system.cpu.dtb.write_hits 160846849 # DTB write hits system.cpu.dtb.write_misses 1701304 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162534618 # DTB write accesses -system.cpu.dtb.data_hits 605628966 # DTB hits +system.cpu.dtb.write_accesses 162548153 # DTB write accesses +system.cpu.dtb.data_hits 605685406 # DTB hits system.cpu.dtb.data_misses 6598382 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 612227348 # DTB accesses -system.cpu.itb.fetch_hits 231949721 # ITB hits +system.cpu.dtb.data_accesses 612283788 # DTB accesses +system.cpu.itb.fetch_hits 231915406 # ITB hits system.cpu.itb.fetch_misses 22 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 231949743 # ITB accesses +system.cpu.itb.fetch_accesses 231915428 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,34 +368,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1986859680 # number of cpu cycles simulated +system.cpu.numCycles 2031916272 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 172586758 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 154099865 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 1667601840 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 172213740 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 154308010 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 1667655233 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 3043804457 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 3043857850 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 651738878 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 617884917 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 120537665 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 11100495 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 131638160 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 83561944 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 61.170119 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 1139346059 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 651713796 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 617884761 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 120483996 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 11146958 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 131630954 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 83569020 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.166808 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 1139383608 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 1741702087 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 1742160374 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 7484450 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 415164157 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 1571695523 # Number of cycles cpu stages are processed. -system.cpu.activity 79.104505 # Percentage of cycles cpu is active +system.cpu.timesIdled 7533550 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 460194055 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 1571722217 # Number of cycles cpu stages are processed. +system.cpu.activity 77.351722 # Percentage of cycles cpu is active system.cpu.comLoads 444595663 # Number of Load instructions committed system.cpu.comStores 160728502 # Number of Store instructions committed system.cpu.comBranches 214632552 # Number of Branches instructions committed @@ -258,191 +407,211 @@ system.cpu.committedInsts 1819780127 # Nu system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total) -system.cpu.cpi 1.091813 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 1.116572 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 1.091813 # CPI: Total CPI of All Threads -system.cpu.ipc 0.915908 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 1.116572 # CPI: Total CPI of All Threads +system.cpu.ipc 0.895598 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.915908 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 800109422 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 1186750258 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 59.729948 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 1053226597 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 933633083 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 46.990389 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 1014475629 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 972384051 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 48.940751 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 1577240024 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 409619656 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 20.616436 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 965534852 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 1021324828 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 51.403974 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.895598 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 845299879 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 1186616393 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 58.398882 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 1098097789 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 933818483 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 45.957528 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 1059529924 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 972386348 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 47.855631 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 1622292075 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 409624197 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 20.159502 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 1010582157 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 1021334115 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 50.264577 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 667.831181 # Cycle average of tags in use -system.cpu.icache.total_refs 231948615 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 668.704565 # Cycle average of tags in use +system.cpu.icache.total_refs 231914267 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 859 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 270021.670547 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 269981.684517 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 667.831181 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.326089 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.326089 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 231948615 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 231948615 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 231948615 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 231948615 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 231948615 # number of overall hits -system.cpu.icache.overall_hits::total 231948615 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1106 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1106 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1106 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1106 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1106 # number of overall misses -system.cpu.icache.overall_misses::total 1106 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 62073500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 62073500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 62073500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 62073500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 62073500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 62073500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 231949721 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 231949721 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 231949721 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 231949721 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 231949721 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 231949721 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 668.704565 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.326516 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.326516 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 231914267 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 231914267 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 231914267 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 231914267 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 231914267 # number of overall hits +system.cpu.icache.overall_hits::total 231914267 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1139 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1139 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1139 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1139 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1139 # number of overall misses +system.cpu.icache.overall_misses::total 1139 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 82633000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 82633000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 82633000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 82633000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 82633000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 82633000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 231915406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 231915406 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 231915406 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 231915406 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 231915406 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 231915406 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56124.321881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56124.321881 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56124.321881 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56124.321881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56124.321881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56124.321881 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72548.726953 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72548.726953 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72548.726953 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72548.726953 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72548.726953 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 247 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 247 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 247 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 247 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 247 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39688224 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 124881981137 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 124921669361 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39688224 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 124881981137 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 124921669361 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 1958831 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1959690 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 53393500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 89166260000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89219653500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69332641250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69332641250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158498901250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 158552294750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53393500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158498901250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 158552294750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163051 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413469 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413469 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.215060 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46202.821886 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58109.520364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58100.840849 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72259.521352 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72259.521352 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46202.821886 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63753.385894 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63745.692866 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46202.821886 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63753.385894 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63745.692866 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214986 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.215060 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62157.741560 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75722.939400 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75713.050920 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88740.328594 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88740.328594 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62157.741560 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62157.741560 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80915.046398 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80906.824421 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9107366 # number of replacements -system.cpu.dcache.tagsinuse 4082.260687 # Cycle average of tags in use -system.cpu.dcache.total_refs 593512555 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9111462 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 65.139113 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 12624962000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4082.260687 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.996646 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.996646 # Average percentage of cache occupancy +system.cpu.dcache.replacements 9107352 # number of replacements +system.cpu.dcache.tagsinuse 4082.468819 # Cycle average of tags in use +system.cpu.dcache.total_refs 593298146 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 65.115682 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 12678178000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4082.468819 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.996696 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.996696 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 437268759 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268759 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 156243796 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 156243796 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 593512555 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 593512555 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 593512555 # number of overall hits -system.cpu.dcache.overall_hits::total 593512555 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 156029387 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 156029387 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 593298146 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 593298146 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 593298146 # number of overall hits +system.cpu.dcache.overall_hits::total 593298146 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 7326904 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 7326904 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4484706 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4484706 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 11811610 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 11811610 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11811610 # number of overall misses -system.cpu.dcache.overall_misses::total 11811610 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 167226851000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 167226851000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 202255523500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 202255523500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 369482374500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 369482374500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 369482374500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 369482374500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 4699115 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4699115 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 449106891000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) @@ -541,54 +710,54 @@ system.cpu.dcache.overall_accesses::cpu.data 605324165 system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027902 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027902 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.019513 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.019513 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019513 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019513 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22823.671635 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22823.671635 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45098.948181 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45098.948181 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31281.288029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31281.288029 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13468960 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4773919 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 372025 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65739 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.204449 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.619282 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029236 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.029236 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25692.506344 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25692.506344 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55512.657915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55512.657915 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37344.601817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37344.601817 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15563445 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7313446 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 432083 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 73150 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.019573 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 99.978756 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693289 # number of writebacks -system.cpu.dcache.writebacks::total 3693289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104624 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104624 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595524 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2595524 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2700148 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2700148 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2700148 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2700148 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111462 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111462 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111462 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111462 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150904604500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 150904604500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79287604500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 79287604500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230192209000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230192209000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230192209000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230192209000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks +system.cpu.dcache.writebacks::total 3693280 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809939 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2809939 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2914571 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2914571 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2914571 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2914571 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222272 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222272 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889176 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889176 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171613180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171613180000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92147472000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92147472000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263760652000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 263760652000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263760652000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 263760652000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses @@ -597,14 +766,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20894.316545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20894.316545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41969.277973 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41969.277973 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23761.661150 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23761.661150 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48776.541730 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48776.541730 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 19663f540..88a7eaf62 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.665535 # Number of seconds simulated -sim_ticks 665534636500 # Number of ticks simulated -final_tick 665534636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.693021 # Number of seconds simulated +sim_ticks 693021015500 # Number of ticks simulated +final_tick 693021015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68112 # Simulator instruction rate (inst/s) -host_op_rate 68112 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26111525 # Simulator tick rate (ticks/s) -host_mem_usage 272636 # Number of bytes of host memory used -host_seconds 25488.16 # Real time elapsed on the host +host_inst_rate 172458 # Simulator instruction rate (inst/s) +host_op_rate 172458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68844519 # Simulator tick rate (ticks/s) +host_mem_usage 228224 # Number of bytes of host memory used +host_seconds 10066.47 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 62080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125797184 # Number of bytes read from this memory -system.physmem.bytes_read::total 125859264 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 62080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 62080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65262656 # Number of bytes written to this memory -system.physmem.bytes_written::total 65262656 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 970 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1965581 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1966551 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1019729 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1019729 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 189016735 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 189110013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98060495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98060495 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98060495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 189016735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 287170509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1966551 # Total number of read requests seen -system.physmem.writeReqs 1019729 # Total number of write requests seen -system.physmem.cpureqs 2986294 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 125859264 # Total number of bytes read from memory -system.physmem.bytesWritten 65262656 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 125859264 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 65262656 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 565 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125798976 # Number of bytes read from this memory +system.physmem.bytes_read::total 125860352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65263616 # Number of bytes written to this memory +system.physmem.bytes_written::total 65263616 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1965609 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1966568 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1019744 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1019744 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 88563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 181522599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 181611162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 88563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 88563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 94172636 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 94172636 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 94172636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 88563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 181522599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 275783798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1966568 # Total number of read requests seen +system.physmem.writeReqs 1019744 # Total number of write requests seen +system.physmem.cpureqs 2986322 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 125860352 # Total number of bytes read from memory +system.physmem.bytesWritten 65263616 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 125860352 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 65263616 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 585 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 122670 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 122308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 124219 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 123641 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 122574 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 120687 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 121413 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 121604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 122268 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 121464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 123454 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 125591 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 124312 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 123151 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 124443 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 63482 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 62396 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 63113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 63858 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 63872 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 63465 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 63448 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 63476 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 63820 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 63370 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 64242 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 64662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 64289 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 63740 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 64359 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 119008 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 114438 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 116555 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 118046 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 118149 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 117808 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 120225 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 124916 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 127564 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 130488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 129072 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 130765 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 126644 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 125671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 122973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 123661 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 61280 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 61566 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 60655 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 61327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 61759 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 63170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 64220 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 65701 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 65486 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 65876 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 65409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 65716 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 64323 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 64319 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 64636 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 64301 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry -system.physmem.totGap 665534568000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry +system.physmem.totGap 693020927000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 1966551 # Categorize read packet sizes +system.physmem.readPktSize::6 1966568 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1019729 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1625924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 77512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1019744 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1645883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 229621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 69862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 20600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,22 +124,22 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 42282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 43951 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 44243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 44314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 44319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 44320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 44321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 43412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 44152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 44291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 44320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 44325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 44326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 44327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 44327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 44337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 44337 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see @@ -147,65 +147,214 @@ system.physmem.wrQLenPdf::19 44336 # Wh system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see -system.physmem.totQLat 34329674750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 102455589750 # Sum of mem lat for all requests -system.physmem.totBusLat 9829930000 # Total cycles spent in databus access -system.physmem.totBankLat 58295985000 # Total cycles spent in bank access -system.physmem.avgQLat 17461.81 # Average queueing delay per request -system.physmem.avgBankLat 29652.29 # Average bank access latency per request +system.physmem.wrQLenPdf::23 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1725071 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 110.744307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 80.207489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.283228 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1378927 79.93% 79.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 191993 11.13% 91.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 57386 3.33% 94.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 28102 1.63% 96.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15937 0.92% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 9770 0.57% 97.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6740 0.39% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 6906 0.40% 98.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 3659 0.21% 98.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3018 0.17% 98.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2639 0.15% 98.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2655 0.15% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1401 0.08% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1109 0.06% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 1069 0.06% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 819 0.05% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 853 0.05% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 845 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 758 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 637 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 729 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 683 0.04% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3600 0.21% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 572 0.03% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 238 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 183 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 143 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 137 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 83 0.00% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 102 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 118 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 69 0.00% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 71 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 61 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 55 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 46 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 41 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 53 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 34 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 52 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 44 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 22 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 36 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 29 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 20 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 30 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 16 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 10 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 20 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 21 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 25 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 16 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 13 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 10 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 23 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 7 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 9 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 5 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 8 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 17 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 4 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 9 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 26 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 12 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 15 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 118 0.01% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 12 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 16 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1427 0.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1725071 # Bytes accessed per row activation +system.physmem.totQLat 33871310750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 97989140750 # Sum of mem lat for all requests +system.physmem.totBusLat 9829915000 # Total cycles spent in databus access +system.physmem.totBankLat 54287915000 # Total cycles spent in bank access +system.physmem.avgQLat 17228.69 # Average queueing delay per request +system.physmem.avgBankLat 27613.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 52114.10 # Average memory access latency -system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 49842.31 # Average memory access latency +system.physmem.avgRdBW 181.61 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 94.17 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 181.61 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 94.17 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.24 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.52 # Average write queue length over time -system.physmem.readRowHits 776084 # Number of row buffer hits during reads -system.physmem.writeRowHits 286116 # Number of row buffer hits during writes -system.physmem.readRowHitRate 39.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes -system.physmem.avgGap 222864.09 # Average gap between requests -system.cpu.branchPred.lookups 381314788 # Number of BP lookups -system.cpu.branchPred.condPredicted 296330051 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16069549 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 262009169 # Number of BTB lookups -system.cpu.branchPred.BTBHits 259516575 # Number of BTB hits +system.physmem.busUtil 2.15 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.14 # Average read queue length over time +system.physmem.avgWrQLen 11.24 # Average write queue length over time +system.physmem.readRowHits 907929 # Number of row buffer hits during reads +system.physmem.writeRowHits 352711 # Number of row buffer hits during writes +system.physmem.readRowHitRate 46.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.59 # Row buffer hit rate for writes +system.physmem.avgGap 232065.81 # Average gap between requests +system.membus.throughput 275783798 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1191455 # Transaction distribution +system.membus.trans_dist::ReadResp 1191455 # Transaction distribution +system.membus.trans_dist::Writeback 1019744 # Transaction distribution +system.membus.trans_dist::ReadExReq 775113 # Transaction distribution +system.membus.trans_dist::ReadExResp 775113 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4952880 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4952880 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191123968 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 191123968 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 191123968 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11815530000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 18578292500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu.branchPred.lookups 381829258 # Number of BP lookups +system.cpu.branchPred.condPredicted 296791594 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16090940 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 262534664 # Number of BTB lookups +system.cpu.branchPred.BTBHits 259935463 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.048662 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 24704658 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2987 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.009959 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 24706233 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3077 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 613784934 # DTB read hits -system.cpu.dtb.read_misses 11255491 # DTB read misses +system.cpu.dtb.read_hits 613998993 # DTB read hits +system.cpu.dtb.read_misses 11257757 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 625040425 # DTB read accesses -system.cpu.dtb.write_hits 212268072 # DTB write hits -system.cpu.dtb.write_misses 7147147 # DTB write misses +system.cpu.dtb.read_accesses 625256750 # DTB read accesses +system.cpu.dtb.write_hits 212346659 # DTB write hits +system.cpu.dtb.write_misses 7132839 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 219415219 # DTB write accesses -system.cpu.dtb.data_hits 826053006 # DTB hits -system.cpu.dtb.data_misses 18402638 # DTB misses +system.cpu.dtb.write_accesses 219479498 # DTB write accesses +system.cpu.dtb.data_hits 826345652 # DTB hits +system.cpu.dtb.data_misses 18390596 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 844455644 # DTB accesses -system.cpu.itb.fetch_hits 390718533 # ITB hits -system.cpu.itb.fetch_misses 44 # ITB misses +system.cpu.dtb.data_accesses 844736248 # DTB accesses +system.cpu.itb.fetch_hits 391092043 # ITB hits +system.cpu.itb.fetch_misses 41 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 390718577 # ITB accesses +system.cpu.itb.fetch_accesses 391092084 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,139 +368,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1331069274 # number of cpu cycles simulated +system.cpu.numCycles 1386042032 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 402166078 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3159376011 # Number of instructions fetch has processed -system.cpu.fetch.Branches 381314788 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 284221233 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 574162316 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 140275246 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 173581201 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1319 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 390718533 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8058234 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1266376452 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.494816 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 402569601 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3162430835 # Number of instructions fetch has processed +system.cpu.fetch.Branches 381829258 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 284641696 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 574759222 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 140771117 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 196436536 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1508 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 391092043 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8064861 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1290645563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.450271 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.141948 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 692214136 54.66% 54.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42617572 3.37% 58.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 21747694 1.72% 59.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 39672890 3.13% 62.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 129244053 10.21% 73.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 61517613 4.86% 77.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38549434 3.04% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 28120980 2.22% 83.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 212692080 16.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 715886341 55.47% 55.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42669337 3.31% 58.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 21804756 1.69% 60.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 39713212 3.08% 63.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 129418344 10.03% 73.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 61537126 4.77% 78.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38572706 2.99% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 28132820 2.18% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 212910921 16.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1266376452 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286473 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.373562 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 433844233 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 155093027 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 542385824 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18588672 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 116464696 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 58295749 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 820 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3086840549 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2050 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 116464696 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 456708081 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 101341646 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 4855 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 535414758 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56442416 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3004830564 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 566431 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1735808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 50354826 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2246618583 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3897053047 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3895813174 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1239873 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1290645563 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.275482 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.281627 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 434522823 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 177728995 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 542687123 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18828896 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 116877726 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 58348631 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 887 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3089538872 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2030 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 116877726 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 457522679 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 122552150 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7258 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 535724767 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 57960983 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3007258855 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 610716 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1836419 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 51661727 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2248310547 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3900270173 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3899027162 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1243011 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 870415620 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 152 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 150 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121369541 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 679327249 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 255330910 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 67787749 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 36895317 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2723405811 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 116 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2508867042 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3090361 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 978262694 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 414978517 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 87 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1266376452 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981138 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.973034 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 872107584 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 171 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 169 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 123506231 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 679721710 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 255512825 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 67679975 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 36990562 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2725376863 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 131 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2509736857 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3186715 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 980131211 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 416747410 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 102 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1290645563 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.944559 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.970905 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 426237987 33.66% 33.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201818534 15.94% 49.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 185298881 14.63% 64.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 153239824 12.10% 76.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 133194400 10.52% 86.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 81007004 6.40% 93.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 65236623 5.15% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 15246676 1.20% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5096523 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 448740391 34.77% 34.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 203240605 15.75% 50.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 185935244 14.41% 64.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 153422938 11.89% 76.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 133053941 10.31% 87.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 80846786 6.26% 93.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65044265 5.04% 98.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 15249478 1.18% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 5111915 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1266376452 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1290645563 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2152645 11.65% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11915798 64.49% 76.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4409146 23.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2163556 11.71% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11907011 64.43% 76.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4409853 23.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1643427997 65.50% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1643982989 65.50% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 257 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 155 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 24 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 270 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 158 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued @@ -373,84 +522,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.50% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 641412571 25.57% 91.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 224025892 8.93% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 641664411 25.57% 91.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 224088858 8.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2508867042 # Type of FU issued -system.cpu.iq.rate 1.884851 # Inst issue rate -system.cpu.iq.fu_busy_cnt 18477589 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007365 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6303778600 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3700560143 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2412458758 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1899886 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1215836 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 851322 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2526405516 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 939115 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62596425 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2509736857 # Type of FU issued +system.cpu.iq.rate 1.810722 # Inst issue rate +system.cpu.iq.fu_busy_cnt 18480420 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.007363 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6329888754 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3704398033 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2413211688 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1897658 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1216996 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 850977 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2527279284 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 937993 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 62596809 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 234731586 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 264011 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 109067 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94602408 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 235126047 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 263685 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 108576 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94784323 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 66 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1508918 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1583083 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 116464696 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 45220798 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1155063 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2865407567 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 8873020 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 679327249 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 255330910 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 116 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 297140 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 16951 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 109067 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10347954 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8554699 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18902653 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2461486866 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 625041025 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 47380176 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 116877726 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 58990263 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1298967 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2867530467 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 8941640 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 679721710 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 255512825 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 325521 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 17838 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 108576 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10366897 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8557633 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18924530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2462313409 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 625257301 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 47423448 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 142001640 # number of nop insts executed -system.cpu.iew.exec_refs 844456273 # number of memory reference insts executed -system.cpu.iew.exec_branches 300755716 # Number of branches executed -system.cpu.iew.exec_stores 219415248 # Number of stores executed -system.cpu.iew.exec_rate 1.849255 # Inst execution rate -system.cpu.iew.wb_sent 2441275432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2413310080 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1388594213 # num instructions producing a value -system.cpu.iew.wb_consumers 1764461796 # num instructions consuming a value +system.cpu.iew.exec_nop 142153473 # number of nop insts executed +system.cpu.iew.exec_refs 844736823 # number of memory reference insts executed +system.cpu.iew.exec_branches 300880868 # Number of branches executed +system.cpu.iew.exec_stores 219479522 # Number of stores executed +system.cpu.iew.exec_rate 1.776507 # Inst execution rate +system.cpu.iew.wb_sent 2442002538 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2414062665 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1388567182 # num instructions producing a value +system.cpu.iew.wb_consumers 1764588303 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.813061 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786979 # average fanout of values written-back +system.cpu.iew.wb_rate 1.741695 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 824506637 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 827045847 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16068781 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1149911756 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.582539 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.513361 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16090137 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1173767837 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.550375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.495661 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 636560643 55.36% 55.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174447924 15.17% 70.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 86151555 7.49% 78.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 53744022 4.67% 82.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 34427444 2.99% 85.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 25274936 2.20% 87.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 21893247 1.90% 89.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22942792 2.00% 91.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94469193 8.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 659878599 56.22% 56.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174801477 14.89% 71.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 86143733 7.34% 78.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 53556827 4.56% 83.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 34704625 2.96% 85.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26036675 2.22% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 21629651 1.84% 90.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22889079 1.95% 91.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94127171 8.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1149911756 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1173767837 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,189 +610,209 @@ system.cpu.commit.branches 214632552 # Nu system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94469193 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94127171 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3613950126 # The number of ROB reads -system.cpu.rob.rob_writes 5405135678 # The number of ROB writes -system.cpu.timesIdled 818095 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64692822 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3640687439 # The number of ROB reads +system.cpu.rob.rob_writes 5410628429 # The number of ROB writes +system.cpu.timesIdled 939185 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 95396469 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.766726 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.766726 # CPI: Total CPI of All Threads -system.cpu.ipc 1.304248 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.304248 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3317233936 # number of integer regfile reads -system.cpu.int_regfile_writes 1931587557 # number of integer regfile writes -system.cpu.fp_regfile_reads 30073 # number of floating regfile reads -system.cpu.fp_regfile_writes 508 # number of floating regfile writes +system.cpu.cpi 0.798391 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.798391 # CPI: Total CPI of All Threads +system.cpu.ipc 1.252519 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.252519 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3318270268 # number of integer regfile reads +system.cpu.int_regfile_writes 1932125497 # number of integer regfile writes +system.cpu.fp_regfile_reads 30353 # number of floating regfile reads +system.cpu.fp_regfile_writes 534 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes +system.cpu.toL2Bus.throughput 1191881478 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7297634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7297634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3724968 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1918 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085580 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22087498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825937536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 825998912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 825998912 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10178169165 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1438500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13770459000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 775.031780 # Cycle average of tags in use -system.cpu.icache.total_refs 390717051 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 970 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 402801.083505 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 768.731270 # Cycle average of tags in use +system.cpu.icache.total_refs 391090558 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 959 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 407810.800834 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 775.031780 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.378433 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.378433 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 390717051 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 390717051 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 390717051 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 390717051 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 390717051 # number of overall hits -system.cpu.icache.overall_hits::total 390717051 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses -system.cpu.icache.overall_misses::total 1482 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 88954499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 88954499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 88954499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 88954499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 88954499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 88954499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 390718533 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 390718533 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 390718533 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 390718533 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 390718533 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 390718533 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 768.731270 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.375357 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.375357 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 391090558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 391090558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 391090558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 391090558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 391090558 # number of overall hits +system.cpu.icache.overall_hits::total 391090558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1484 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1484 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses +system.cpu.icache.overall_misses::total 1484 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 114408499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 114408499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 114408499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 114408499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 114408499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 114408499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 391092042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 391092042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 391092042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 391092042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 391092042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 391092042 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60023.278677 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60023.278677 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60023.278677 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60023.278677 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60023.278677 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60023.278677 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1152 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77094.675876 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77094.675876 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77094.675876 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77094.675876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77094.675876 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77094.675876 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1730 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 288 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 346 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 512 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 512 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 512 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 512 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 512 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 970 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 970 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 970 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 970 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 970 # 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mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163156 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163266 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.411499 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.411499 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214187 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.214194 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214104 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214187 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49083.032990 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63242.036708 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63230.509178 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62416.290890 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62416.290890 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49083.032990 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62916.405889 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62909.582587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49083.032990 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62916.405889 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62909.582587 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214111 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.214194 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70526.329510 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81054.887627 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 81046.413209 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79976.634697 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79976.634697 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70526.329510 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80629.692248 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80624.765327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70526.329510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80629.692248 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80624.765327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 9176393 # number of replacements -system.cpu.dcache.tagsinuse 4087.522074 # Cycle average of tags in use -system.cpu.dcache.total_refs 694329819 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 9180489 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 75.631028 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 5069314000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4087.522074 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.997930 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 538683298 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 538683298 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155646519 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155646519 # number of WriteReq hits +system.cpu.dcache.replacements 9176210 # number of replacements +system.cpu.dcache.tagsinuse 4087.713956 # Cycle average of tags in use +system.cpu.dcache.total_refs 694263707 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 9180306 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 75.625334 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 5139692000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4087.713956 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.997977 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.997977 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 538720806 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 538720806 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155542899 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155542899 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 694329817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 694329817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 694329817 # number of overall hits -system.cpu.dcache.overall_hits::total 694329817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11282174 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11282174 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5081983 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5081983 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 694263705 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 694263705 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 694263705 # number of overall hits +system.cpu.dcache.overall_hits::total 694263705 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11385401 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11385401 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5185603 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5185603 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 16364157 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 16364157 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 16364157 # number of overall misses -system.cpu.dcache.overall_misses::total 16364157 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 295231740500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 295231740500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 224040653758 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 224040653758 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 49500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 49500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 519272394258 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 519272394258 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 519272394258 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 519272394258 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 549965472 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 549965472 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 16571004 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 16571004 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 16571004 # number of overall misses +system.cpu.dcache.overall_misses::total 16571004 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 352412462500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 352412462500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 293618457575 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 293618457575 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 71500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 71500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 646030920075 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 646030920075 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 646030920075 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 646030920075 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 550106207 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 550106207 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 710693974 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 710693974 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 710693974 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 710693974 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020514 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.020514 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.031618 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.031618 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 710834709 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 710834709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 710834709 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 710834709 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020697 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.020697 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032263 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032263 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.333333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.333333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023026 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023026 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023026 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023026 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26167.983272 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26167.983272 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44085.282016 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44085.282016 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31732.303366 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31732.303366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31732.303366 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31732.303366 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12263483 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5814647 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 736139 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 65133 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.659195 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.273440 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.023312 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023312 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023312 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023312 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30953.012766 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 30953.012766 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56621.854310 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56621.854310 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38985.623326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38985.623326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38985.623326 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 13659344 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 8231616 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 745438 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65134 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.323917 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 126.379710 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3725155 # number of writebacks -system.cpu.dcache.writebacks::total 3725155 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3985249 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3985249 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3198420 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3198420 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7183669 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7183669 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7183669 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7183669 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296925 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7296925 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1883563 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1883563 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3724968 # number of writebacks +system.cpu.dcache.writebacks::total 3724968 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4088719 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4088719 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3301980 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3301980 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7390699 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7390699 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7390699 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7390699 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7296682 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7296682 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 71462908450 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230721382950 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 230721382950 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230721382950 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 230721382950 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9180305 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9180305 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9180305 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9180305 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180470424000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180470424000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85065304522 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85065304522 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265535728522 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 265535728522 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265535728522 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 265535728522 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012918 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012918 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.422969 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.422969 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37940.280442 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37940.280442 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25131.712274 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25131.712274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25131.712274 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25131.712274 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24733.217646 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24733.217646 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45160.472410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45160.472410 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 4f12f01d2..87abf8a8a 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2288605 # Simulator instruction rate (inst/s) -host_op_rate 2288605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1148451794 # Simulator tick rate (ticks/s) -host_mem_usage 263992 # Number of bytes of host memory used -host_seconds 795.15 # Real time elapsed on the host +host_inst_rate 4050769 # Simulator instruction rate (inst/s) +host_op_rate 4050768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2032728095 # Simulator tick rate (ticks/s) +host_mem_usage 217548 # Number of bytes of host memory used +host_seconds 449.24 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 906468506 # Wr system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11068994882 # Throughput (bytes/s) +system.membus.data_through_bus 10108087278 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 56da2f7b0..4fe8387b5 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1056521 # Simulator instruction rate (inst/s) -host_op_rate 1056521 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1523075909 # Simulator tick rate (ticks/s) -host_mem_usage 272444 # Number of bytes of host memory used -host_seconds 1722.43 # Real time elapsed on the host +host_inst_rate 781919 # Simulator instruction rate (inst/s) +host_op_rate 781919 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1127211275 # Simulator tick rate (ticks/s) +host_mem_usage 225028 # Number of bytes of host memory used +host_seconds 2327.32 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 24836956 # To system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 72644797 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1178362 # Transaction distribution +system.membus.trans_dist::ReadResp 1178362 # Transaction distribution +system.membus.trans_dist::Writeback 1018077 # Transaction distribution +system.membus.trans_dist::ReadExReq 781301 # Transaction distribution +system.membus.trans_dist::ReadExResp 781301 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4937403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4937403 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190575360 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -402,5 +418,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 312415345 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1604 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916965 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21918569 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819534784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 819586112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 2a4746f89..48447911f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,103 +1,103 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.517355 # Number of seconds simulated -sim_ticks 517355353500 # Number of ticks simulated -final_tick 517355353500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.540696 # Number of seconds simulated +sim_ticks 540696400000 # Number of ticks simulated +final_tick 540696400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80961 # Simulator instruction rate (inst/s) -host_op_rate 90318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27118174 # Simulator tick rate (ticks/s) -host_mem_usage 288124 # Number of bytes of host memory used -host_seconds 19077.81 # Real time elapsed on the host +host_inst_rate 169038 # Simulator instruction rate (inst/s) +host_op_rate 188575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59174301 # Simulator tick rate (ticks/s) +host_mem_usage 246336 # Number of bytes of host memory used +host_seconds 9137.35 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 143726656 # Number of bytes read from this memory -system.physmem.bytes_read::total 143774272 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 70431232 # Number of bytes written to this memory -system.physmem.bytes_written::total 70431232 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2245729 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2246473 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1100488 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1100488 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 92037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277810319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 277902357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 92037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 92037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136137051 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136137051 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136137051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 92037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277810319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 414039407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2246473 # Total number of read requests seen -system.physmem.writeReqs 1100488 # Total number of write requests seen -system.physmem.cpureqs 3346979 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 143774272 # Total number of bytes read from memory -system.physmem.bytesWritten 70431232 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 143774272 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 70431232 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 670 # Number of read reqs serviced by write Q +system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 143740608 # Number of bytes read from this memory +system.physmem.bytes_read::total 143788736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70441600 # Number of bytes written to this memory +system.physmem.bytes_written::total 70441600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2245947 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2246699 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1100650 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1100650 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 89011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 265843471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 265932483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89011 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 130279395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 130279395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 130279395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 265843471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 396211878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2246699 # Total number of read requests seen +system.physmem.writeReqs 1100650 # Total number of write requests seen +system.physmem.cpureqs 3347359 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 143788736 # Total number of bytes read from memory +system.physmem.bytesWritten 70441600 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 143788736 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 70441600 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 675 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 141489 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 139656 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 141525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 141936 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 142251 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 140152 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 141094 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 140745 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 138661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 136342 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 140561 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 140724 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 141098 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 138976 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 138964 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 141629 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 69092 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 68439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 69113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 69523 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 69288 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 69039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 68977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 68383 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 67923 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 67021 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 69461 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 69311 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 69094 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 68543 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 68433 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 68848 # Track writes on a per bank basis +system.physmem.perBankRdReqs::0 139594 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 136159 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 133894 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 136244 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 134956 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 135313 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 136207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 136262 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 143860 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 146526 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 144286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 146187 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 145855 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 146147 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 142095 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 142439 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 69117 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 67412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 65719 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 66245 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 66183 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 66419 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 67973 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 68813 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 70394 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 70993 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 70492 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 70984 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 70346 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 70810 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 69619 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 69131 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 18 # Number of times wr buffer was full causing retry -system.physmem.totGap 517355284500 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry +system.physmem.totGap 540696152000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 2246473 # Categorize read packet sizes +system.physmem.readPktSize::6 2246699 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 1100488 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1563773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 450876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 162701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 68433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1100650 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1614963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 444775 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 139732 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -124,68 +124,217 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 44051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 47144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 47800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 47824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 47830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 47847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see -system.physmem.totQLat 51860326500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 131350914000 # Sum of mem lat for all requests -system.physmem.totBusLat 11229015000 # Total cycles spent in databus access -system.physmem.totBankLat 68261572500 # Total cycles spent in bank access -system.physmem.avgQLat 23092.11 # Average queueing delay per request -system.physmem.avgBankLat 30395.17 # Average bank access latency per request +system.physmem.wrQLenPdf::0 45615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 47508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 47801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 47831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 47837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 47839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 47840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 47843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 47844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 47854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1997676 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.204860 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 79.811800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 283.656472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 1593756 79.78% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 230264 11.53% 91.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 68043 3.41% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 32667 1.64% 96.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 17678 0.88% 97.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 10939 0.55% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7434 0.37% 98.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7476 0.37% 98.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 4079 0.20% 98.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3182 0.16% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 2817 0.14% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 2754 0.14% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1425 0.07% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 1138 0.06% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 999 0.05% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 880 0.04% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 791 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 732 0.04% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 642 0.03% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 540 0.03% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 574 0.03% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 838 0.04% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 3581 0.18% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 454 0.02% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 187 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 173 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 114 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 112 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 90 0.00% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 76 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 95 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 66 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 55 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 44 0.00% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 45 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 44 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 34 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 42 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 31 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 27 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 29 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 30 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 32 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 28 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 35 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 28 0.00% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 31 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 33 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 18 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 20 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 12 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 21 0.00% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 11 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 16 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 19 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 10 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 29 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 20 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 29 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4225 15 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 13 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 6 0.00% 99.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 10 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 9 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4737 15 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 15 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4929 8 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 18 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5249 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 5 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 17 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 11 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5569 7 0.00% 99.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 11 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6081 21 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6209 17 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6337 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 9 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6465 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 15 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 6 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 16 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 7 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7233 15 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7297 8 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7425 3 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7553 9 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 9 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7681 124 0.01% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7745 13 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 13 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 8 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 8 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8065 12 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 22 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 1443 0.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1997676 # Bytes accessed per row activation +system.physmem.totQLat 50306526000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 124453758500 # Sum of mem lat for all requests +system.physmem.totBusLat 11230120000 # Total cycles spent in databus access +system.physmem.totBankLat 62917112500 # Total cycles spent in bank access +system.physmem.avgQLat 22398.04 # Average queueing delay per request +system.physmem.avgBankLat 28012.66 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 58487.28 # Average memory access latency -system.physmem.avgRdBW 277.90 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 277.90 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 55410.70 # Average memory access latency +system.physmem.avgRdBW 265.93 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 130.28 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 265.93 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 130.28 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.23 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.25 # Average read queue length over time -system.physmem.avgWrQLen 11.18 # Average write queue length over time -system.physmem.readRowHits 827290 # Number of row buffer hits during reads -system.physmem.writeRowHits 270800 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 24.61 # Row buffer hit rate for writes -system.physmem.avgGap 154574.64 # Average gap between requests -system.cpu.branchPred.lookups 303238356 # Number of BP lookups -system.cpu.branchPred.condPredicted 249416285 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15213179 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 173189005 # Number of BTB lookups -system.cpu.branchPred.BTBHits 161485027 # Number of BTB hits +system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.23 # Average read queue length over time +system.physmem.avgWrQLen 10.44 # Average write queue length over time +system.physmem.readRowHits 1005962 # Number of row buffer hits during reads +system.physmem.writeRowHits 343028 # Number of row buffer hits during writes +system.physmem.readRowHitRate 44.79 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes +system.physmem.avgGap 161529.66 # Average gap between requests +system.membus.throughput 396211878 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1420214 # Transaction distribution +system.membus.trans_dist::ReadResp 1420214 # Transaction distribution +system.membus.trans_dist::Writeback 1100650 # Transaction distribution +system.membus.trans_dist::ReadExReq 826485 # Transaction distribution +system.membus.trans_dist::ReadExResp 826485 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 5594048 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 5594048 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214230336 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 214230336 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 214230336 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 12859707750 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 21134071500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.9 # Layer utilization (%) +system.cpu.branchPred.lookups 304230401 # Number of BP lookups +system.cpu.branchPred.condPredicted 250450611 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15192997 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 172575058 # Number of BTB lookups +system.cpu.branchPred.BTBHits 162497547 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.242078 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 17562220 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.160506 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 17547944 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 207 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -229,237 +378,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1034710708 # number of cpu cycles simulated +system.cpu.numCycles 1081392801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 298243506 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2186139129 # Number of instructions fetch has processed -system.cpu.fetch.Branches 303238356 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 179047247 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 435102558 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 87842368 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155357657 # Number of cycles fetch has spent blocked -system.cpu.fetch.PendingTrapStallCycles 150 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 288597285 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5732219 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 958597013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.523325 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.213142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 300338229 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2194868023 # Number of instructions fetch has processed +system.cpu.fetch.Branches 304230401 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 180045491 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 436913465 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 88946702 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 165329116 # Number of cycles fetch has spent blocked +system.cpu.fetch.PendingTrapStallCycles 33 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 290586210 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6069176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 973112936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.494450 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.204820 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 523494535 54.61% 54.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 25506855 2.66% 57.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 39100627 4.08% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 48361324 5.05% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 43019358 4.49% 70.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 46453211 4.85% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 38427133 4.01% 79.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18718773 1.95% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175515197 18.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 536199557 55.10% 55.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 25797166 2.65% 57.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 39079992 4.02% 61.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 48369850 4.97% 66.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 43937617 4.52% 71.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 46464611 4.77% 76.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38405061 3.95% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 19061800 1.96% 81.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175797282 18.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 958597013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.293066 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.112802 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 329802987 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 133619813 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 405201175 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20080558 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 69892480 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46072656 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2366906963 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2456 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 69892480 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 353335624 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63410713 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18651 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 400220631 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 71718914 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2304481635 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 133374 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5031151 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 58581263 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 68 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2279812946 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10642278370 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10642275398 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2972 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973112936 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.281332 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.029668 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 332624022 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 143219561 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 406441589 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20296480 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 70531284 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46039188 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 865 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2374316328 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2545 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 70531284 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 356409274 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 71650111 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21139 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 401304268 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 73196860 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2310523412 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 156231 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5060521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 60179356 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 18 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2286636992 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10669420338 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10669417166 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3172 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 573493016 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 743 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 740 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 158758361 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 624481311 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 220974466 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 86299107 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 71333452 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2201408276 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 781 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2018173722 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4013043 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 473803931 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1125355707 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 611 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 958597013 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.105341 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.906395 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 580317062 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 904 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 901 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 161063694 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 625481573 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 221078320 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 85817344 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 70539912 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2205002740 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 913 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2019903116 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4041921 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 477338341 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1137890497 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973112936 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.075713 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.906230 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 277575373 28.96% 28.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 151381497 15.79% 44.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 161170411 16.81% 61.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 119836935 12.50% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 123952521 12.93% 86.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 73863494 7.71% 94.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38468068 4.01% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 9785076 1.02% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2563638 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 289817184 29.78% 29.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 153400597 15.76% 45.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161373326 16.58% 62.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 120291643 12.36% 74.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 123812966 12.72% 87.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 73732869 7.58% 94.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38377982 3.94% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 9754115 1.00% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2552254 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 958597013 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973112936 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 884210 3.70% 3.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5702 0.02% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.72% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18296872 76.51% 80.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4728009 19.77% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 873823 3.65% 3.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5574 0.02% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18262233 76.32% 80.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4786578 20.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236704914 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 925192 0.05% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 4 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 587491999 29.11% 90.43% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193051561 9.57% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1237523467 61.27% 61.27% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 925246 0.05% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 44 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588384414 29.13% 90.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193069911 9.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2018173722 # Type of FU issued -system.cpu.iq.rate 1.950471 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23914793 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011850 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5022872024 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2675402581 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1957467931 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 269 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 546 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2042088379 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64652420 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2019903116 # Type of FU issued +system.cpu.iq.rate 1.867872 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23928208 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011846 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5040888987 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2682531512 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1957653574 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 310 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 122 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2043831169 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 155 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 64629118 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 138554542 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 270922 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 192724 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 46127421 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 139554804 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 275861 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 192692 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 46231275 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4683320 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 5362990 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 69892480 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28879520 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1498948 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2201409154 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6144718 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 624481311 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 220974466 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 719 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 474123 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 89366 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 192724 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8152988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9608721 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 17761709 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1988146149 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 573921356 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 30027573 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 70531284 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 34407025 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1609544 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2205003765 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 7646058 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 625481573 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 221078320 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 851 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 482587 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 96102 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 192692 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8138129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 9602458 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 17740587 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1988966025 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574553789 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30937091 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 97 # number of nop insts executed -system.cpu.iew.exec_refs 764085836 # number of memory reference insts executed -system.cpu.iew.exec_branches 238329441 # Number of branches executed -system.cpu.iew.exec_stores 190164480 # Number of stores executed -system.cpu.iew.exec_rate 1.921451 # Inst execution rate -system.cpu.iew.wb_sent 1965914335 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1957468025 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296382145 # num instructions producing a value -system.cpu.iew.wb_consumers 2061123370 # num instructions consuming a value +system.cpu.iew.exec_nop 112 # number of nop insts executed +system.cpu.iew.exec_refs 764737764 # number of memory reference insts executed +system.cpu.iew.exec_branches 238303653 # Number of branches executed +system.cpu.iew.exec_stores 190183975 # Number of stores executed +system.cpu.iew.exec_rate 1.839263 # Inst execution rate +system.cpu.iew.wb_sent 1966073864 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1957653696 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1295701173 # num instructions producing a value +system.cpu.iew.wb_consumers 2059307469 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.891802 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.628969 # average fanout of values written-back +system.cpu.iew.wb_rate 1.810308 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.629193 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 478433603 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 482029293 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15212517 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 888704533 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.938860 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.728045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15192188 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 902581652 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.909050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.715598 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 401292741 45.15% 45.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 192157168 21.62% 66.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72538162 8.16% 74.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35233922 3.96% 78.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 18967934 2.13% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30755514 3.46% 84.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20061647 2.26% 86.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11460153 1.29% 88.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106237292 11.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 414112551 45.88% 45.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193170118 21.40% 67.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72777120 8.06% 75.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35259342 3.91% 79.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 18942446 2.10% 81.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30787152 3.41% 84.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19991978 2.21% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11413503 1.26% 88.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106127442 11.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 888704533 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 902581652 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -470,192 +619,212 @@ system.cpu.commit.branches 213462426 # Nu system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106237292 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106127442 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2983974098 # The number of ROB reads -system.cpu.rob.rob_writes 4473052836 # The number of ROB writes -system.cpu.timesIdled 1016894 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76113695 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3001556757 # The number of ROB reads +system.cpu.rob.rob_writes 4480884032 # The number of ROB writes +system.cpu.timesIdled 1155619 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 108279865 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated -system.cpu.cpi 0.669905 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.669905 # CPI: Total CPI of All Threads -system.cpu.ipc 1.492749 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.492749 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9956441643 # number of integer regfile reads -system.cpu.int_regfile_writes 1937434969 # number of integer regfile writes -system.cpu.fp_regfile_reads 88 # number of floating regfile reads -system.cpu.fp_regfile_writes 99 # number of floating regfile writes -system.cpu.misc_regfile_reads 737571197 # number of misc regfile reads +system.cpu.cpi 0.700129 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.700129 # CPI: Total CPI of All Threads +system.cpu.ipc 1.428309 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.428309 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9959942925 # number of integer regfile reads +system.cpu.int_regfile_writes 1937523681 # number of integer regfile writes +system.cpu.fp_regfile_reads 126 # number of floating regfile reads +system.cpu.fp_regfile_writes 125 # number of floating regfile writes +system.cpu.misc_regfile_reads 737562736 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.icache.replacements 21 # number of replacements -system.cpu.icache.tagsinuse 624.513050 # Cycle average of tags in use -system.cpu.icache.total_refs 288596120 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 772 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 373829.170984 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 1584099202 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7708436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7708436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3781153 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1893485 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1893485 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1562 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22983433 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 22984995 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 49984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856466752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 856516736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10472863577 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1171999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 14401713992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu.icache.replacements 22 # number of replacements +system.cpu.icache.tagsinuse 627.830229 # Cycle average of tags in use +system.cpu.icache.total_refs 290585017 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 781 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 372067.883483 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 624.513050 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.304938 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.304938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 288596120 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 288596120 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 288596120 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 288596120 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 288596120 # number of overall hits -system.cpu.icache.overall_hits::total 288596120 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1165 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1165 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1165 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1165 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1165 # number of overall misses -system.cpu.icache.overall_misses::total 1165 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 63973500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 63973500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 63973500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 63973500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 63973500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 63973500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 288597285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 288597285 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 288597285 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 288597285 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 288597285 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 288597285 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 627.830229 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.306558 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.306558 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 290585017 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 290585017 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 290585017 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 290585017 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 290585017 # number of overall hits +system.cpu.icache.overall_hits::total 290585017 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1193 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1193 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1193 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1193 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1193 # number of overall misses +system.cpu.icache.overall_misses::total 1193 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 86035500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 86035500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 86035500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 86035500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 86035500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 86035500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 290586210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 290586210 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 290586210 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 290586210 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 290586210 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 290586210 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54912.875536 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54912.875536 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54912.875536 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54912.875536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54912.875536 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54912.875536 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 195 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72116.932104 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72116.932104 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72116.932104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72116.932104 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72116.932104 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 49.750000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 393 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 393 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 393 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 393 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 393 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 772 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 772 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 772 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 772 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 772 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 772 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 45298000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 45298000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 45298000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 45298000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45298000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 45298000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59384001 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59384001 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59384001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59384001 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59384001 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59384001 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58676.165803 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58676.165803 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58676.165803 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 58676.165803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58676.165803 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 58676.165803 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76035.852753 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76035.852753 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76035.852753 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76035.852753 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76035.852753 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76035.852753 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 2213784 # number of replacements -system.cpu.l2cache.tagsinuse 31531.827043 # Cycle average of tags in use -system.cpu.l2cache.total_refs 9244985 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 2243559 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 4.120678 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 20448147251 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 14438.568410 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 20.286933 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 17072.971700 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.440630 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.000619 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.521026 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.962275 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6287849 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6287876 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3781426 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3781426 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1066921 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1066921 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965026 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.233919 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.233977 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965026 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.233919 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.233977 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59395.973154 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80126.820172 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 80115.943616 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85425.694250 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85425.694250 # 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miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.436489 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964149 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.233926 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.233985 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964149 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.233926 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.233985 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77444.887118 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 97362.294730 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 97351.734552 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101681.521746 # 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number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 11474951 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 11474951 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5538571 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5538571 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 655932667 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 655932667 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 655932667 # number of overall hits +system.cpu.dcache.overall_hits::total 655932667 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 11505709 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 11505709 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5626409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5626409 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17013522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17013522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17013522 # number of overall misses -system.cpu.dcache.overall_misses::total 17013522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 323064220500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 323064220500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 229479325824 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 229479325824 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 552543546324 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 552543546324 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 552543546324 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 552543546324 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500504809 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500504809 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 17132118 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 17132118 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 17132118 # number of overall misses +system.cpu.dcache.overall_misses::total 17132118 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 379498751500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 379498751500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 307395824029 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 307395824029 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 651000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 651000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 686894575529 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 686894575529 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 686894575529 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 686894575529 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 500478738 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 500478738 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 68 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 68 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 673090856 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 673090856 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 673090856 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 673090856 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022927 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022927 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025277 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025277 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025277 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025277 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28153.864927 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28153.864927 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41432.948286 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41432.948286 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32476.729176 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32476.729176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32476.729176 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32476.729176 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26385368 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1054130 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1182490 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 64549 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.313396 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 16.330695 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 673064785 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 673064785 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 673064785 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 673064785 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032601 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032601 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025454 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025454 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025454 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025454 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32983.517270 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32983.517270 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54634.461169 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54634.461169 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 217000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 217000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40093.967105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40093.967105 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29400681 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3494014 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1217576 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.146896 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 53.645121 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3781426 # number of writebacks -system.cpu.dcache.writebacks::total 3781426 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767868 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3767868 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645146 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3645146 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3781153 # number of writebacks +system.cpu.dcache.writebacks::total 3781153 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798054 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3798054 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732924 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3732924 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7413014 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7413014 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7413014 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7413014 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707083 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7707083 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893425 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893425 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9600508 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9600508 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9600508 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9600508 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186133873500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 186133873500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83704359724 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83704359724 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269838233224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 269838233224 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269838233224 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 269838233224 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7530978 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7530978 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7530978 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7530978 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707655 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7707655 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893485 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893485 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9601140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9601140 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9601140 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9601140 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210632290508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 210632290508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97135590826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 97135590826 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 307767881334 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 307767881334 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 307767881334 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 307767881334 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24151.014528 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24151.014528 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44207.908802 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44207.908802 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27327.674955 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27327.674955 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51299.899828 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51299.899828 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index bf810ed1c..c05db510c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538200000 # Number of ticks simulated final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1602478 # Simulator instruction rate (inst/s) -host_op_rate 1787682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 893842215 # Simulator tick rate (ticks/s) -host_mem_usage 278712 # Number of bytes of host memory used -host_seconds 963.86 # Real time elapsed on the host +host_inst_rate 2812355 # Simulator instruction rate (inst/s) +host_op_rate 3137389 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1568696760 # Simulator tick rate (ticks/s) +host_mem_usage 234512 # Number of bytes of host memory used +host_seconds 549.21 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1723073853 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 724469782 # Wr system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 9731209155 # Throughput (bytes/s) +system.membus.data_through_bus 8383808419 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 8d9905464..7f261f2f5 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 809589 # Simulator instruction rate (inst/s) -host_op_rate 903509 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1258086461 # Simulator tick rate (ticks/s) -host_mem_usage 287292 # Number of bytes of host memory used -host_seconds 1900.67 # Real time elapsed on the host +host_inst_rate 1401168 # Simulator instruction rate (inst/s) +host_op_rate 1563717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2177389973 # Simulator tick rate (ticks/s) +host_mem_usage 243008 # Number of bytes of host memory used +host_seconds 1098.20 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -34,6 +34,22 @@ system.physmem.bw_total::writebacks 27225047 # To system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 79651138 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1177898 # Transaction distribution +system.membus.trans_dist::ReadResp 1177898 # Transaction distribution +system.membus.trans_dist::Writeback 1017198 # Transaction distribution +system.membus.trans_dist::ReadExReq 780876 # Transaction distribution +system.membus.trans_dist::ReadExResp 780876 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 4934746 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 4934746 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 190462208 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190462208 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -423,5 +439,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21927890 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21929166 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 820009856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 820050688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 545751e41..09bbb2360 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 542745211 # Wr system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13588998587 # Throughput (bytes/s) +system.membus.data_through_bus 38674388193 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 5692014456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 225f011f6..136c3d430 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -34,6 +34,26 @@ system.physmem.bw_total::writebacks 11079992 # To system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 32392097 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 1177614 # Transaction distribution +system.membus.trans_dist::ReadResp 1177614 # Transaction distribution +system.membus.trans_dist::Writeback 1018421 # Transaction distribution +system.membus.trans_dist::ReadExReq 781295 # Transaction distribution +system.membus.trans_dist::ReadExResp 781295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 190549120 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 11765161052 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -370,5 +390,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1350 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21923310 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21924660 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 43200 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819880512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 819923712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 44b065dab..4f9464f49 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.041622 # Number of seconds simulated -sim_ticks 41622221000 # Number of ticks simulated -final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.041671 # Number of seconds simulated +sim_ticks 41671058000 # Number of ticks simulated +final_tick 41671058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47594 # Simulator instruction rate (inst/s) -host_op_rate 47594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21554846 # Simulator tick rate (ticks/s) -host_mem_usage 275256 # Number of bytes of host memory used -host_seconds 1930.99 # Real time elapsed on the host +host_inst_rate 79080 # Simulator instruction rate (inst/s) +host_op_rate 79080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35856814 # Simulator tick rate (ticks/s) +host_mem_usage 228800 # Number of bytes of host memory used +host_seconds 1162.15 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 178816 # Nu system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 4296167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3296701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7592867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4296167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4296167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4296167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3296701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7592867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 4291132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3292837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7583969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4291132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4291132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4291132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3292837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7583969 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 4938 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 316032 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 311 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 293 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 259 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 294 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 345 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 351 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 333 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 382 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 295 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 499 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 209 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 212 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 265 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 236 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 379 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 469 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 423 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 41622168000 # Total gap between requests +system.physmem.totGap 41670985500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 440 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3344 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,56 +149,135 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 23362750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 122110250 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 858.311111 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 328.631203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1420.533351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 87 24.17% 24.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 46 12.78% 36.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 36 10.00% 46.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 14 3.89% 50.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 20 5.56% 56.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 14 3.89% 60.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 9 2.50% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 7 1.94% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 8 2.22% 66.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3 0.83% 67.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 8 2.22% 70.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 5 1.39% 71.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 1.67% 73.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 7 1.94% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 4 1.11% 76.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 2 0.56% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 5 1.39% 78.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 1 0.28% 78.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.83% 79.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 5 1.39% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.28% 80.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.83% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 4 1.11% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 2 0.56% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.83% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.83% 85.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.56% 85.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 4 1.11% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.28% 86.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 4 1.11% 88.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.56% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 3 0.83% 89.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.28% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.28% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 3 0.83% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 2 0.56% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.28% 91.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 2 0.56% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.28% 92.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 2 0.56% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.28% 93.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.28% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 1 0.28% 93.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.56% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.28% 94.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 1 0.28% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.28% 95.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.28% 95.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.28% 95.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.56% 96.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.28% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.28% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.28% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 1 0.28% 97.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.28% 97.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.28% 98.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation +system.physmem.totQLat 21938250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 110827000 # Sum of mem lat for all requests system.physmem.totBusLat 24690000 # Total cycles spent in databus access -system.physmem.totBankLat 74057500 # Total cycles spent in bank access -system.physmem.avgQLat 4731.22 # Average queueing delay per request -system.physmem.avgBankLat 14997.47 # Average bank access latency per request +system.physmem.totBankLat 64198750 # Total cycles spent in bank access +system.physmem.avgQLat 4442.74 # Average queueing delay per request +system.physmem.avgBankLat 13000.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24728.69 # Average memory access latency -system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22443.70 # Average memory access latency +system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4243 # Number of row buffer hits during reads +system.physmem.readRowHits 4578 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads +system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8428952.61 # Average gap between requests -system.cpu.branchPred.lookups 13412628 # Number of BP lookups -system.cpu.branchPred.condPredicted 9650145 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits +system.physmem.avgGap 8438838.70 # Average gap between requests +system.membus.throughput 7583969 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3216 # Transaction distribution +system.membus.trans_dist::ReadResp 3216 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 9876 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 9876 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 316032 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 5804000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 46092250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.branchPred.lookups 13412467 # Number of BP lookups +system.cpu.branchPred.condPredicted 9649930 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4269365 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 7424694 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3768519 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.757723 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 50.756556 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996247 # DTB read hits +system.cpu.dtb.read_hits 19996249 # DTB read hits system.cpu.dtb.read_misses 10 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996257 # DTB read accesses -system.cpu.dtb.write_hits 6501860 # DTB write hits +system.cpu.dtb.read_accesses 19996259 # DTB read accesses +system.cpu.dtb.write_hits 6501862 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501883 # DTB write accesses -system.cpu.dtb.data_hits 26498107 # DTB hits +system.cpu.dtb.write_accesses 6501885 # DTB write accesses +system.cpu.dtb.data_hits 26498111 # DTB hits system.cpu.dtb.data_misses 33 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26498140 # DTB accesses -system.cpu.itb.fetch_hits 9956943 # ITB hits +system.cpu.dtb.data_accesses 26498144 # DTB accesses +system.cpu.itb.fetch_hits 9957259 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 9956992 # ITB accesses +system.cpu.itb.fetch_accesses 9957308 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,34 +291,34 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 83244443 # number of cpu cycles simulated +system.cpu.numCycles 83342117 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 73570548 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedTaken 5905707 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 7506760 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 73570716 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 136146020 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File +system.cpu.regfile_manager.intRegFileAccesses 136146188 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.floatRegFileReads 2206130 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 38521871 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 26722393 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 57404029 # Number of Instructions Executed. +system.cpu.regfile_manager.floatRegFileAccesses 8058018 # Total Accesses (Read+Write) to the FP Register File +system.cpu.regfile_manager.regForwards 38521724 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 26722400 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 3469281 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 799226 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 4268507 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 5972195 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 41.681781 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 57404114 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 82970150 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 82971475 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 10684 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7636716 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 75607727 # Number of cycles cpu stages are processed. -system.cpu.activity 90.826155 # Percentage of cycles cpu is active +system.cpu.timesIdled 10802 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7733735 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 75608382 # Number of cycles cpu stages are processed. +system.cpu.activity 90.720496 # Percentage of cycles cpu is active system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.comBranches 10240685 # Number of Branches instructions committed @@ -251,72 +330,72 @@ system.cpu.committedInsts 91903056 # Nu system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total) -system.cpu.cpi 0.905785 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 0.906848 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 0.905785 # CPI: Total CPI of All Threads -system.cpu.ipc 1.104014 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 0.906848 # CPI: Total CPI of All Threads +system.cpu.ipc 1.102720 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 1.104014 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 27564085 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 55680358 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 66.887778 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33992749 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 49251694 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 59.165143 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33393108 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 49851335 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 59.885481 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 65217942 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 18026501 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 21.654900 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29384710 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 53859733 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 64.700695 # Percentage of cycles stage was utilized (processing insts). -system.cpu.icache.replacements 7635 # number of replacements -system.cpu.icache.tagsinuse 1492.649281 # Cycle average of tags in use -system.cpu.icache.total_refs 9945578 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 9520 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1044.703571 # Average number of references to valid blocks. +system.cpu.ipc_total 1.102720 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27661043 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 55681074 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 66.810247 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34090230 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 49251887 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 59.096035 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33490685 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 49851432 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 59.815414 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 65315589 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 18026528 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 21.629554 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29482268 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 53859849 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 64.625007 # Percentage of cycles stage was utilized (processing insts). +system.cpu.icache.replacements 7633 # number of replacements +system.cpu.icache.tagsinuse 1492.272065 # Cycle average of tags in use +system.cpu.icache.total_refs 9945862 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 9518 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1044.952931 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1492.649281 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.728833 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.728833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 9945578 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 9945578 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 9945578 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 9945578 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 9945578 # number of overall hits -system.cpu.icache.overall_hits::total 9945578 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 11365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 11365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 11365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 11365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 11365 # number of overall misses -system.cpu.icache.overall_misses::total 11365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 259163500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 259163500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 259163500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 259163500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 259163500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 259163500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9956943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9956943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9956943 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9956943 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9956943 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9956943 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001141 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001141 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001141 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001141 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001141 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001141 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22803.651562 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22803.651562 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22803.651562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22803.651562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22803.651562 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1492.272065 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.728648 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.728648 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 9945862 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 9945862 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 9945862 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 9945862 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 9945862 # number of overall hits +system.cpu.icache.overall_hits::total 9945862 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 11397 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 11397 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 11397 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 11397 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 11397 # number of overall misses +system.cpu.icache.overall_misses::total 11397 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 317452000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 317452000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 317452000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 317452000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 317452000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 317452000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9957259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9957259 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9957259 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9957259 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9957259 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9957259 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27853.996666 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27853.996666 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27853.996666 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27853.996666 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27853.996666 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -325,63 +404,83 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 7 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1845 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1845 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1845 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1845 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1845 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1845 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 209587500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 209587500 # 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Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 9993 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 9993 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 19036 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 23589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 609152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 758272 # 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Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 2.069775 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.069165 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 17.839003 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1821.325102 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 351.099198 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000544 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.055582 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.010715 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.066842 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits +system.cpu.l2cache.occ_blocks::writebacks 17.843612 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 1820.867359 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 351.006398 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.055568 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.010712 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.066825 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6724 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6777 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # 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miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 11741 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293549 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.888421 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.321761 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.321825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293487 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.293549 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.420506 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66410.591333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65517.895490 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 67573.927239 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66410.591333 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -458,73 +557,73 @@ system.cpu.l2cache.demand_mshr_misses::total 4938 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4938 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 148372000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 118657250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 267029250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.420506 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.420577 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293549 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.420506 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35008.919470 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44544.672986 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36260.190609 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36692.181765 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36692.181765 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35008.919470 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38237.774720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36410.836371 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.420577 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53103.793844 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59098.341232 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53890.391791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54423.780488 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54423.780488 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53103.793844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55343.866604 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54076.397327 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 157 # number of replacements -system.cpu.dcache.tagsinuse 1441.801421 # Cycle average of tags in use -system.cpu.dcache.total_refs 26488625 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.455577 # Cycle average of tags in use +system.cpu.dcache.total_refs 26488507 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11915.710751 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11915.657670 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1441.801421 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.352002 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.352002 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 19995623 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995623 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493002 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493002 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26488625 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26488625 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26488625 # number of overall hits -system.cpu.dcache.overall_hits::total 26488625 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 575 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 575 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8101 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8101 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 8676 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8676 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8676 # number of overall misses -system.cpu.dcache.overall_misses::total 8676 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31369500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31369500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 346048500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 346048500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 377418000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 377418000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 377418000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 377418000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 1441.455577 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.351918 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 19995622 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995622 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492885 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492885 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26488507 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26488507 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26488507 # number of overall hits +system.cpu.dcache.overall_hits::total 26488507 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 576 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 576 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8218 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8218 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 8794 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8794 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8794 # number of overall misses +system.cpu.dcache.overall_misses::total 8794 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 38984000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 38984000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 463524000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 463524000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 502508000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 502508000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 502508000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 502508000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) @@ -535,38 +634,38 @@ system.cpu.dcache.overall_accesses::cpu.data 26497301 system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000029 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54555.652174 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54555.652174 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42716.763363 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42716.763363 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 43501.383126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 43501.383126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 43501.383126 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 13712 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001264 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001264 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000332 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000332 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000332 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000332 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67680.555556 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67680.555556 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56403.504502 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56403.504502 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57142.142370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57142.142370 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21765 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 825 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.681265 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.381818 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 107 # number of writebacks system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6353 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6353 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6453 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6453 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6453 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6453 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6470 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6470 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6571 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6571 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6571 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6571 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses @@ -575,14 +674,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2223 system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25078500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25078500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111244000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 111244000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111244000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 111244000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 31213000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116706500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 147919500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147919500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 147919500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses @@ -591,14 +690,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52796.842105 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52796.842105 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65711.578947 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65711.578947 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66765.732265 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66765.732265 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 557ecc886..183d79059 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.023380 # Number of seconds simulated -sim_ticks 23379948000 # Number of ticks simulated -final_tick 23379948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.023497 # Number of seconds simulated +sim_ticks 23497413000 # Number of ticks simulated +final_tick 23497413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61366 # Simulator instruction rate (inst/s) -host_op_rate 61366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17043654 # Simulator tick rate (ticks/s) -host_mem_usage 277304 # Number of bytes of host memory used -host_seconds 1371.77 # Real time elapsed on the host +host_inst_rate 127551 # Simulator instruction rate (inst/s) +host_op_rate 127551 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35603882 # Simulator tick rate (ticks/s) +host_mem_usage 231880 # Number of bytes of host memory used +host_seconds 659.97 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory -system.physmem.bytes_read::total 334528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195840 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8376409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 5931921 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14308330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8376409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8376409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8376409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5931921 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 14308330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5227 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 195392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory +system.physmem.bytes_read::total 334016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 195392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 195392 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3053 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5219 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8315469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 5899543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14215012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8315469 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8315469 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8315469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5899543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 14215012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5219 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5227 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 334528 # Total number of bytes read from memory +system.physmem.cpureqs 5219 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 334016 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 334528 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 334016 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 362 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 327 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 311 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 286 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 297 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 308 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 281 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 365 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 354 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 400 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 519 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 218 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 288 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 446 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23379842000 # Total gap between requests +system.physmem.totGap 23497287000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5227 # Categorize read packet sizes +system.physmem.readPktSize::6 5219 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 3182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,56 +149,139 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 29390250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 134711500 # Sum of mem lat for all requests -system.physmem.totBusLat 26135000 # Total cycles spent in databus access -system.physmem.totBankLat 79186250 # Total cycles spent in bank access -system.physmem.avgQLat 5622.78 # Average queueing delay per request -system.physmem.avgBankLat 15149.46 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 779.330144 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 283.808293 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1370.086091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 124 29.67% 29.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 51 12.20% 41.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 42 10.05% 51.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 20 4.78% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 15 3.59% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 19 4.55% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 7 1.67% 66.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 9 2.15% 68.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 7 1.67% 70.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 3 0.72% 71.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 8 1.91% 72.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 7 1.67% 74.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 6 1.44% 76.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 5 1.20% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 4 0.96% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 1 0.24% 78.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 6 1.44% 79.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 5 1.20% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 3 0.72% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.72% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.72% 86.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 3 0.72% 89.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 2 0.48% 89.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 2 0.48% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.24% 91.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 2 0.48% 91.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.24% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.24% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.24% 93.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 1 0.24% 94.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 1 0.24% 95.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 1 0.24% 96.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.48% 96.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.24% 96.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.24% 97.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 1 0.24% 98.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.24% 98.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 418 # Bytes accessed per row activation +system.physmem.totQLat 22102000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 116465750 # Sum of mem lat for all requests +system.physmem.totBusLat 26095000 # Total cycles spent in databus access +system.physmem.totBankLat 68268750 # Total cycles spent in bank access +system.physmem.avgQLat 4234.91 # Average queueing delay per request +system.physmem.avgBankLat 13080.81 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25772.24 # Average memory access latency -system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22315.72 # Average memory access latency +system.physmem.avgRdBW 14.22 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 14.22 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.11 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.01 # Average read queue length over time +system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4448 # Number of row buffer hits during reads +system.physmem.readRowHits 4801 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 91.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4472898.79 # Average gap between requests -system.cpu.branchPred.lookups 14842140 # Number of BP lookups -system.cpu.branchPred.condPredicted 10766991 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 921197 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8255704 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6953438 # Number of BTB hits +system.physmem.avgGap 4502258.48 # Average gap between requests +system.membus.throughput 14215012 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3511 # Transaction distribution +system.membus.trans_dist::ReadResp 3511 # Transaction distribution +system.membus.trans_dist::ReadExReq 1708 # Transaction distribution +system.membus.trans_dist::ReadExResp 1708 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 10438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 10438 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334016 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 334016 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 334016 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 6341000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 48807250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu.branchPred.lookups 14862551 # Number of BP lookups +system.cpu.branchPred.condPredicted 10783549 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 926034 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8413875 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6968843 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 84.225864 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1467825 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3067 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.825607 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1469354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3121 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 23110097 # DTB read hits -system.cpu.dtb.read_misses 194589 # DTB read misses +system.cpu.dtb.read_hits 23132924 # DTB read hits +system.cpu.dtb.read_misses 192093 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 23304686 # DTB read accesses -system.cpu.dtb.write_hits 7067053 # DTB write hits -system.cpu.dtb.write_misses 1113 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 7068166 # DTB write accesses -system.cpu.dtb.data_hits 30177150 # DTB hits -system.cpu.dtb.data_misses 195702 # DTB misses -system.cpu.dtb.data_acv 8 # DTB access violations -system.cpu.dtb.data_accesses 30372852 # DTB accesses -system.cpu.itb.fetch_hits 14723480 # ITB hits -system.cpu.itb.fetch_misses 97 # ITB misses +system.cpu.dtb.read_accesses 23325017 # DTB read accesses +system.cpu.dtb.write_hits 7072345 # DTB write hits +system.cpu.dtb.write_misses 1094 # DTB write misses +system.cpu.dtb.write_acv 2 # DTB write access violations +system.cpu.dtb.write_accesses 7073439 # DTB write accesses +system.cpu.dtb.data_hits 30205269 # DTB hits +system.cpu.dtb.data_misses 193187 # DTB misses +system.cpu.dtb.data_acv 4 # DTB access violations +system.cpu.dtb.data_accesses 30398456 # DTB accesses +system.cpu.itb.fetch_hits 14755058 # ITB hits +system.cpu.itb.fetch_misses 101 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 14723577 # ITB accesses +system.cpu.itb.fetch_accesses 14755159 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -212,139 +295,139 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 46759897 # number of cpu cycles simulated +system.cpu.numCycles 46994827 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15452025 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 126885771 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14842140 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 8421263 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22118402 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4462593 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 5523983 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2725 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 15489149 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 127098752 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14862551 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 8438197 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22157137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4490975 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 5583322 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2356 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14723480 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 324121 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 46604653 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.722599 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14755058 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 326188 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 46762472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.717965 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.375306 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24486251 52.54% 52.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2361565 5.07% 57.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1190149 2.55% 60.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1742976 3.74% 63.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2754417 5.91% 69.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1149365 2.47% 72.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1217917 2.61% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 773119 1.66% 76.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10928894 23.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24605335 52.62% 52.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2364392 5.06% 57.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1192796 2.55% 60.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1746753 3.74% 63.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2761574 5.91% 69.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1153115 2.47% 72.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1218931 2.61% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 773556 1.65% 76.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10946020 23.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 46604653 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.317412 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.713560 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17272805 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4225851 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20520611 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1089695 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3495691 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2514029 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12278 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 123910172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 32104 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3495691 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18413803 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 951839 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20446933 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3289037 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 121090735 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 399536 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2410998 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 88918567 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 157348562 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 147674536 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 9674026 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 46762472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.316259 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.704526 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17321703 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4276623 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20543509 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1101986 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3518651 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2516350 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12158 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 124100512 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 31524 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3518651 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18468008 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 966877 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7668 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20476490 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3324778 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 121264521 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 82 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 403236 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 2443262 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 89058236 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 157582364 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 147884300 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 9698064 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20491206 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 720 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 712 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8742624 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 25345876 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8236695 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2569867 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 913943 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 105383195 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1656 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 96551560 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178239 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 20729473 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15559619 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1267 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 46604653 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.071715 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.877215 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 20630875 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 727 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 718 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8817740 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 25385211 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8251770 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2611914 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 924495 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 105530247 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1715 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 96635335 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178536 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 20879466 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 15657073 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1326 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 46762472 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.066515 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.875135 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 12094878 25.95% 25.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 9328666 20.02% 45.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8376475 17.97% 63.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6286526 13.49% 77.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4922367 10.56% 87.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2863469 6.14% 94.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1727619 3.71% 97.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 799385 1.72% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 205268 0.44% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12166038 26.02% 26.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 9374565 20.05% 46.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8425963 18.02% 64.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6292522 13.46% 77.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4920709 10.52% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2854864 6.11% 94.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1726414 3.69% 97.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 795538 1.70% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 205859 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 46604653 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 46762472 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 187515 11.95% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 174 0.01% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 7228 0.46% 12.43% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 5644 0.36% 12.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 843061 53.75% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 446254 28.45% 94.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78748 5.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 190796 12.16% 12.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 179 0.01% 12.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 7128 0.45% 12.62% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 5650 0.36% 12.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 843178 53.72% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 444699 28.33% 95.03% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 77939 4.97% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58727382 60.82% 60.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 479803 0.50% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58779410 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 479944 0.50% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2798335 2.90% 64.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115384 0.12% 64.34% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2386573 2.47% 66.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 311072 0.32% 67.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 760041 0.79% 67.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2800605 2.90% 64.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115340 0.12% 64.34% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2387840 2.47% 66.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 311019 0.32% 67.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 760059 0.79% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued @@ -366,84 +449,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.92% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23822951 24.67% 92.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7149693 7.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23845244 24.68% 92.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7155548 7.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 96551560 # Type of FU issued -system.cpu.iq.rate 2.064837 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1568624 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016246 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 226343159 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 117415886 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87055232 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15111477 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8732806 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7062055 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90134309 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7985868 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1517472 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 96635335 # Type of FU issued +system.cpu.iq.rate 2.056297 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1569569 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.016242 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 226659120 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 117679968 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87126809 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15122127 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 8766253 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7066480 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 90213613 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7991284 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1520773 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5349678 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 18734 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34491 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1735592 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5389013 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18483 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 34901 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1750667 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10525 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1599 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 10533 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1986 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3495691 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 132330 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18056 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 115618245 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 370442 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 25345876 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8236695 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1656 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2792 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34491 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 533607 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 495069 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1028676 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 95323071 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23305173 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1228489 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3518651 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 134178 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18459 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 115772618 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 373350 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 25385211 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8251770 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1715 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3175 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 34901 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 538953 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 495548 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1034501 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 95401130 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23325510 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1234205 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10233394 # number of nop insts executed -system.cpu.iew.exec_refs 30373541 # number of memory reference insts executed -system.cpu.iew.exec_branches 12020857 # Number of branches executed -system.cpu.iew.exec_stores 7068368 # Number of stores executed -system.cpu.iew.exec_rate 2.038565 # Inst execution rate -system.cpu.iew.wb_sent 94638543 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 94117287 # cumulative count of insts written-back -system.cpu.iew.wb_producers 64469301 # num instructions producing a value -system.cpu.iew.wb_consumers 89849772 # num instructions consuming a value +system.cpu.iew.exec_nop 10240656 # number of nop insts executed +system.cpu.iew.exec_refs 30399148 # number of memory reference insts executed +system.cpu.iew.exec_branches 12029434 # Number of branches executed +system.cpu.iew.exec_stores 7073638 # Number of stores executed +system.cpu.iew.exec_rate 2.030035 # Inst execution rate +system.cpu.iew.wb_sent 94712572 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 94193289 # cumulative count of insts written-back +system.cpu.iew.wb_producers 64506867 # num instructions producing a value +system.cpu.iew.wb_consumers 89893282 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.012778 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717523 # average fanout of values written-back +system.cpu.iew.wb_rate 2.004333 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717594 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 23716139 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23870674 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 909447 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43108962 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.131878 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.747863 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 914298 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43243821 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.125230 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.743207 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16687185 38.71% 38.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 9891500 22.95% 61.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4481461 10.40% 72.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2260770 5.24% 77.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1601496 3.71% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1124303 2.61% 83.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 719465 1.67% 85.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 820222 1.90% 87.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5522560 12.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16770420 38.78% 38.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 9933071 22.97% 61.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4488153 10.38% 72.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2264318 5.24% 77.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1614513 3.73% 81.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1126501 2.60% 83.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 722210 1.67% 85.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 820173 1.90% 87.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5504462 12.73% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43108962 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43243821 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -454,192 +537,212 @@ system.cpu.commit.branches 10240685 # Nu system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5522560 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5504462 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153204556 # The number of ROB reads -system.cpu.rob.rob_writes 234757733 # The number of ROB writes -system.cpu.timesIdled 5297 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 155244 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 153512048 # The number of ROB reads +system.cpu.rob.rob_writes 235089898 # The number of ROB writes +system.cpu.timesIdled 5458 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 232355 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.555477 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.555477 # CPI: Total CPI of All Threads -system.cpu.ipc 1.800254 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.800254 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 129030140 # number of integer regfile reads -system.cpu.int_regfile_writes 70506108 # number of integer regfile writes -system.cpu.fp_regfile_reads 6188141 # number of floating regfile reads -system.cpu.fp_regfile_writes 6043644 # number of floating regfile writes -system.cpu.misc_regfile_reads 714512 # number of misc regfile reads +system.cpu.cpi 0.558268 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.558268 # CPI: Total CPI of All Threads +system.cpu.ipc 1.791255 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.791255 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 129137938 # number of integer regfile reads +system.cpu.int_regfile_writes 70566847 # number of integer regfile writes +system.cpu.fp_regfile_reads 6190616 # number of floating regfile reads +system.cpu.fp_regfile_writes 6048237 # number of floating regfile writes +system.cpu.misc_regfile_reads 714522 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.icache.replacements 9682 # number of replacements -system.cpu.icache.tagsinuse 1594.464074 # Cycle average of tags in use -system.cpu.icache.total_refs 14709198 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 11615 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1266.396728 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 38347030 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12236 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12236 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23446 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4603 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 28049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 750272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 901056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 901056 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 7148500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 17584500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3370500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 9791 # number of replacements +system.cpu.icache.tagsinuse 1591.709559 # Cycle average of tags in use +system.cpu.icache.total_refs 14740526 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 11723 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 1257.402201 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1594.464074 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.778547 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.778547 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14709198 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14709198 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14709198 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14709198 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14709198 # number of overall hits -system.cpu.icache.overall_hits::total 14709198 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14281 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14281 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14281 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14281 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14281 # number of overall misses -system.cpu.icache.overall_misses::total 14281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 321909000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 321909000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 321909000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 321909000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 321909000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 321909000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14723479 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14723479 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14723479 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14723479 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14723479 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14723479 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000970 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000970 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000970 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000970 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000970 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000970 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22541.068553 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22541.068553 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22541.068553 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22541.068553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22541.068553 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22541.068553 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 93 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1591.709559 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.777202 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.777202 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14740526 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14740526 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14740526 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14740526 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14740526 # number of overall hits +system.cpu.icache.overall_hits::total 14740526 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14531 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14531 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14531 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14531 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14531 # number of overall misses +system.cpu.icache.overall_misses::total 14531 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 399004500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 399004500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 399004500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 399004500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 399004500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 399004500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14755057 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14755057 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14755057 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14755057 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14755057 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14755057 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000985 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000985 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000985 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000985 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000985 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000985 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27458.846604 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27458.846604 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27458.846604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27458.846604 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27458.846604 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 306 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.714286 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2666 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2666 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2666 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2666 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2666 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2666 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11615 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11615 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11615 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11615 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11615 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11615 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242799000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242799000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242799000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242799000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242799000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242799000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000789 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000789 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000789 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000789 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000789 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000789 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20903.917348 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20903.917348 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20903.917348 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 20903.917348 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20903.917348 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 20903.917348 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2808 # 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number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3053 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2166 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5219 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3053 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2166 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5219 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161149500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 28038250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 189187750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93560500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93560500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161149500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121598750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 282748250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161149500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121598750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 282748250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.260428 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.286940 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.260428 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.373586 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.260428 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963952 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.373586 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52783.982968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61218.886463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53884.292224 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54777.810304 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54777.810304 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52783.982968 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56139.773777 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54176.710098 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52783.982968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56139.773777 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54176.710098 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 159 # number of replacements -system.cpu.dcache.tagsinuse 1459.922825 # Cycle average of tags in use -system.cpu.dcache.total_refs 28072747 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 2248 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12487.876779 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 1461.104213 # Cycle average of tags in use +system.cpu.dcache.total_refs 28091806 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 2247 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12501.916333 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1459.922825 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.356426 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.356426 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 21579507 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21579507 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6493005 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6493005 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 235 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 235 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28072512 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28072512 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28072512 # number of overall hits -system.cpu.dcache.overall_hits::total 28072512 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1007 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1007 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8098 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8098 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1461.104213 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.356715 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.356715 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 21598707 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492881 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492881 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 218 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 218 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28091588 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28091588 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28091588 # number of overall hits +system.cpu.dcache.overall_hits::total 28091588 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 971 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 971 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8222 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8222 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9105 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9105 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9105 # number of overall misses -system.cpu.dcache.overall_misses::total 9105 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 50924000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 50924000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 356653797 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 356653797 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 72000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 407577797 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 407577797 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 407577797 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 407577797 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21580514 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21580514 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9193 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 535128778 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21599678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21599678 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 236 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 236 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28081617 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28081617 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28081617 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28081617 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001246 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001246 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004237 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004237 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50570.009930 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50570.009930 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44042.207582 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44042.207582 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44764.173202 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44764.173202 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44764.173202 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44764.173202 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14165 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 219 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 219 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28100781 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28100781 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28100781 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28100781 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001265 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001265 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004566 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004566 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61365.087539 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61365.087539 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57837.907808 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57837.907808 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 58210.462091 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 58210.462091 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21885 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 330 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 353 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.924242 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.997167 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 109 # number of writebacks system.cpu.dcache.writebacks::total 109 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 491 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 491 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6367 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6367 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6858 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6858 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6858 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6858 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 516 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 516 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6488 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6488 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 6947 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6947 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6947 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6947 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 512 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 88590998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119010498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 119010498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119010498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 119010498 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34660000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34660000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116538997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 116538997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151198997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 151198997 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151198997 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 151198997 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004237 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004237 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004566 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004566 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58952.519380 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58952.519380 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51179.086077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51179.086077 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67695.312500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67695.312500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67208.187428 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67208.187428 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index e64f41702..31612b0d4 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1141309 # Simulator instruction rate (inst/s) -host_op_rate 1141309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 570654979 # Simulator tick rate (ticks/s) -host_mem_usage 267644 # Number of bytes of host memory used -host_seconds 80.52 # Real time elapsed on the host +host_inst_rate 3944537 # Simulator instruction rate (inst/s) +host_op_rate 3944535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1972268010 # Simulator tick rate (ticks/s) +host_mem_usage 220188 # Number of bytes of host memory used +host_seconds 23.30 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 672903574 # Wr system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11030545389 # Throughput (bytes/s) +system.membus.data_through_bus 506870851 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index aead393ef..b57d95ab0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316000 # Number of ticks simulated final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1044383 # Simulator instruction rate (inst/s) -host_op_rate 1044383 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1349235521 # Simulator tick rate (ticks/s) -host_mem_usage 276220 # Number of bytes of host memory used -host_seconds 88.00 # Real time elapsed on the host +host_inst_rate 852211 # Simulator instruction rate (inst/s) +host_op_rate 852211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1100968725 # Simulator tick rate (ticks/s) +host_mem_usage 228676 # Number of bytes of host memory used +host_seconds 107.84 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 1412827 # In system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 2568532 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3043 # Transaction distribution +system.membus.trans_dist::ReadResp 3043 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 9530 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 304960 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -396,5 +411,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 5843207 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 17020 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 21573 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 544640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 693760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 0198a0866..e580bbf9c 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.074157 # Number of seconds simulated -sim_ticks 74157495500 # Number of ticks simulated -final_tick 74157495500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.074184 # Number of seconds simulated +sim_ticks 74184344000 # Number of ticks simulated +final_tick 74184344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51189 # Simulator instruction rate (inst/s) -host_op_rate 56047 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22031117 # Simulator tick rate (ticks/s) -host_mem_usage 291420 # Number of bytes of host memory used -host_seconds 3366.03 # Real time elapsed on the host +host_inst_rate 120810 # Simulator instruction rate (inst/s) +host_op_rate 132276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52014122 # Simulator tick rate (ticks/s) +host_mem_usage 249648 # Number of bytes of host memory used +host_seconds 1426.23 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 111936 # Number of bytes read from this memory -system.physmem.bytes_read::total 243712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1749 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3808 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1776975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1509436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3286411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1776975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1776975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1776975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1509436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3286411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3809 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 131136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory +system.physmem.bytes_read::total 242944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 131136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 131136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2049 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3796 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1767705 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1507164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3274869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1767705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1767705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1767705 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1507164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3274869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3796 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 3811 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 243712 # Total number of bytes read from memory +system.physmem.cpureqs 3798 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 242944 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 243712 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 242944 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 323 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 239 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 197 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 252 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 309 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 297 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 262 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 288 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 201 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 199 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 248 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 274 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 189 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 206 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 219 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 199 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 74157477000 # Total gap between requests +system.physmem.totGap 74184191000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 3809 # Categorize read packet sizes +system.physmem.readPktSize::6 3796 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 2784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2837 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,36 +149,114 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 17510750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 103435750 # Sum of mem lat for all requests -system.physmem.totBusLat 19045000 # Total cycles spent in databus access -system.physmem.totBankLat 66880000 # Total cycles spent in bank access -system.physmem.avgQLat 4597.20 # Average queueing delay per request -system.physmem.avgBankLat 17558.41 # Average bank access latency per request +system.physmem.bytesPerActivate::samples 376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 621.446809 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 226.720612 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1211.628472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 135 35.90% 35.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 51 13.56% 49.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 26 6.91% 56.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 29 7.71% 64.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 14 3.72% 67.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 14 3.72% 71.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 6 1.60% 73.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 5 1.33% 74.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 7 1.86% 76.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 7 1.86% 78.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 5 1.33% 79.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 1.60% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 1 0.27% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 5 1.33% 82.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 3 0.80% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 4 1.06% 84.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 2 0.53% 85.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 3 0.80% 85.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 3 0.80% 86.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 1 0.27% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 1 0.27% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 5 1.33% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 2 0.53% 89.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 1 0.27% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.80% 90.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 3 0.80% 90.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 1 0.27% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.27% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 1 0.27% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 1 0.27% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 2 0.53% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.27% 92.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 1 0.27% 93.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.27% 93.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 1 0.27% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 1 0.27% 93.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 1 0.27% 94.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.27% 94.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.27% 94.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 1 0.27% 94.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.27% 95.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 1 0.27% 95.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 1 0.27% 95.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3265 3 0.80% 96.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 1 0.27% 96.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 1 0.27% 97.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 1 0.27% 97.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.27% 97.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4801 1 0.27% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5121 1 0.27% 98.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.27% 98.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.27% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6849 1 0.27% 99.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.27% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 2 0.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 376 # Bytes accessed per row activation +system.physmem.totQLat 13471250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 86310000 # Sum of mem lat for all requests +system.physmem.totBusLat 18980000 # Total cycles spent in databus access +system.physmem.totBankLat 53858750 # Total cycles spent in bank access +system.physmem.avgQLat 3548.80 # Average queueing delay per request +system.physmem.avgBankLat 14188.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27155.62 # Average memory access latency -system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 22737.09 # Average memory access latency +system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 3021 # Number of row buffer hits during reads +system.physmem.readRowHits 3420 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.31 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 19469014.70 # Average gap between requests -system.cpu.branchPred.lookups 94703867 # Number of BP lookups -system.cpu.branchPred.condPredicted 74722053 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6280216 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 44664544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 43035053 # Number of BTB hits +system.physmem.avgGap 19542726.82 # Average gap between requests +system.membus.throughput 3274869 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2721 # Transaction distribution +system.membus.trans_dist::ReadResp 2721 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 1075 # Transaction distribution +system.membus.trans_dist::ReadExResp 1075 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 7596 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 7596 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 242944 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 242944 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 242944 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4823500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 35740248 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 94757540 # Number of BP lookups +system.cpu.branchPred.condPredicted 74764818 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6278340 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 44654246 # Number of BTB lookups +system.cpu.branchPred.BTBHits 43033777 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 96.351712 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 4359745 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88611 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 96.371075 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 4354951 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 88346 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -222,240 +300,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 148314992 # number of cpu cycles simulated +system.cpu.numCycles 148368689 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 39662414 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 380030694 # Number of instructions fetch has processed -system.cpu.fetch.Branches 94703867 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 47394798 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80357293 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 27270600 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7200009 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 5243 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 39647823 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 380146219 # Number of instructions fetch has processed +system.cpu.fetch.Branches 94757540 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 47388728 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80358140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 27268312 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7203967 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 5523 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 36857358 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1832427 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 148199476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.801422 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.152732 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 36843987 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1833209 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 148189615 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.802214 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.153150 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 68011684 45.89% 45.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5276203 3.56% 49.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10540688 7.11% 56.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10280783 6.94% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8654302 5.84% 69.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6554085 4.42% 73.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6244651 4.21% 77.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7982798 5.39% 83.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 24654282 16.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68000764 45.89% 45.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5268021 3.55% 49.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10540392 7.11% 56.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10285161 6.94% 63.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8646262 5.83% 69.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6545573 4.42% 73.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6244018 4.21% 77.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7997629 5.40% 83.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 24661795 16.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148199476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.638532 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.562322 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45512613 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5867522 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 74797201 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1201275 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 20820865 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14305085 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164111 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 392663870 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 738369 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 20820865 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 50901215 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 722150 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 593982 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70547488 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4613776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 371203156 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 343152 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3655877 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 631482556 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1581281661 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1563963855 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17317806 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 148189615 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.638663 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.562173 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45498061 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5874830 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 74793705 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1202536 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 20820483 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14321847 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164416 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 392715815 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 749819 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 20820483 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 50886064 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 722985 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 600307 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 70546117 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4613659 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 371260855 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 344235 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3657023 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 27 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 631666093 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1581493948 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1564155420 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17338528 # Number of floating rename lookups system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 333438417 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25133 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25129 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13026907 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 42996111 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16422667 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5676383 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3667621 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 329112708 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47143 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 249432965 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 790911 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 139431014 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 361763997 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1927 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148199476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.683089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.761808 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 333621954 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25182 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25179 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13028807 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 42981884 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16417977 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5680787 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3667947 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 329134626 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 249422621 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 787073 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 139456652 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 361881130 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 148189615 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.683132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.761818 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 56042939 37.82% 37.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 22629719 15.27% 53.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 24820832 16.75% 69.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20320046 13.71% 83.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12535804 8.46% 92.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6521757 4.40% 96.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4030887 2.72% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1115815 0.75% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 181677 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 56042296 37.82% 37.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 22626121 15.27% 53.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 24808060 16.74% 69.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20320875 13.71% 83.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12548887 8.47% 92.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6516147 4.40% 96.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4031410 2.72% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1113540 0.75% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 182279 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148199476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 148189615 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 963057 38.38% 38.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5596 0.22% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 51 0.00% 38.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1167699 46.53% 85.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372909 14.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 962595 38.42% 38.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5594 0.22% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 107 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1164588 46.49% 85.14% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 372359 14.86% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 194880762 78.13% 78.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 980286 0.39% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33071 0.01% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 194884583 78.13% 78.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 979638 0.39% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33073 0.01% 78.54% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 254305 0.10% 78.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76429 0.03% 78.73% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 465674 0.19% 78.92% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38348799 15.37% 94.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13950639 5.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 164452 0.07% 78.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254844 0.10% 78.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76427 0.03% 78.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 465912 0.19% 78.93% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206449 0.08% 79.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71875 0.03% 79.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 79.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 38337954 15.37% 94.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13947091 5.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 249432965 # Type of FU issued -system.cpu.iq.rate 1.681779 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2509413 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010060 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 646629225 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 466421271 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237868779 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3736505 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2188097 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1840763 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 250067463 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1874915 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2006857 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 249422621 # Type of FU issued +system.cpu.iq.rate 1.681100 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2505291 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010044 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 646588556 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 466464832 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237860517 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3738665 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2192143 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1842020 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 250052019 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1875893 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2007355 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13146627 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11917 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18980 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3778033 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13132400 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11727 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18993 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 3773343 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 13 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 20820865 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17088 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 846 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 329176829 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 784787 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 42996111 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16422667 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 24735 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18980 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3891833 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3757719 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7649552 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 242934999 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 36843669 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6497966 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 20820483 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18849 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 902 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 329198829 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 786805 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 42981884 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16417977 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 191 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18993 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3888167 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3760327 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7648494 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 242926605 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 36835264 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6496016 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 16978 # number of nop insts executed -system.cpu.iew.exec_refs 50492106 # number of memory reference insts executed -system.cpu.iew.exec_branches 53412943 # Number of branches executed -system.cpu.iew.exec_stores 13648437 # Number of stores executed -system.cpu.iew.exec_rate 1.637967 # Inst execution rate -system.cpu.iew.wb_sent 240767037 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 239709542 # cumulative count of insts written-back -system.cpu.iew.wb_producers 148457899 # num instructions producing a value -system.cpu.iew.wb_consumers 267241195 # num instructions consuming a value +system.cpu.iew.exec_nop 17000 # number of nop insts executed +system.cpu.iew.exec_refs 50481074 # number of memory reference insts executed +system.cpu.iew.exec_branches 53424163 # Number of branches executed +system.cpu.iew.exec_stores 13645810 # Number of stores executed +system.cpu.iew.exec_rate 1.637317 # Inst execution rate +system.cpu.iew.wb_sent 240758455 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 239702537 # cumulative count of insts written-back +system.cpu.iew.wb_producers 148455856 # num instructions producing a value +system.cpu.iew.wb_consumers 267256641 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.616219 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.555520 # average fanout of values written-back +system.cpu.iew.wb_rate 1.615587 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.555481 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 140505920 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 140527929 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6126595 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 127378611 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481182 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.186353 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6124743 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 127369132 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.481292 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186316 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57698651 45.30% 45.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 31675595 24.87% 70.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13783953 10.82% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7631475 5.99% 86.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4374952 3.43% 90.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1321227 1.04% 91.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1703973 1.34% 92.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1307096 1.03% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7881689 6.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 57689921 45.29% 45.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 31670367 24.87% 70.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13785643 10.82% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7636266 6.00% 86.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4374586 3.43% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1321093 1.04% 91.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1699680 1.33% 92.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1314057 1.03% 93.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7877519 6.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 127378611 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 127369132 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -466,200 +544,220 @@ system.cpu.commit.branches 40300311 # Nu system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. system.cpu.commit.int_insts 150106217 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7881689 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7877519 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 448668532 # The number of ROB reads -system.cpu.rob.rob_writes 679284219 # The number of ROB writes -system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 115516 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 448685232 # The number of ROB reads +system.cpu.rob.rob_writes 679327064 # The number of ROB writes +system.cpu.timesIdled 2810 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 179074 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated -system.cpu.cpi 0.860780 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.860780 # CPI: Total CPI of All Threads -system.cpu.ipc 1.161737 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.161737 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1079304778 # number of integer regfile reads -system.cpu.int_regfile_writes 384845307 # number of integer regfile writes -system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads -system.cpu.fp_regfile_writes 2496150 # number of floating regfile writes -system.cpu.misc_regfile_reads 54492663 # number of misc regfile reads +system.cpu.cpi 0.861092 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.861092 # CPI: Total CPI of All Threads +system.cpu.ipc 1.161317 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.161317 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1079239284 # number of integer regfile reads +system.cpu.int_regfile_writes 384835773 # number of integer regfile writes +system.cpu.fp_regfile_reads 2913699 # number of floating regfile reads +system.cpu.fp_regfile_writes 2498274 # number of floating regfile writes +system.cpu.misc_regfile_reads 54487026 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.icache.replacements 2376 # number of replacements -system.cpu.icache.tagsinuse 1350.566241 # Cycle average of tags in use -system.cpu.icache.total_refs 36852122 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4106 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8975.188018 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 5142648 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 4861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 4861 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3727 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 11907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 261696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 381376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 381376 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2998500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 6138496 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2786987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 2359 # number of replacements +system.cpu.icache.tagsinuse 1350.344535 # Cycle average of tags in use +system.cpu.icache.total_refs 36838706 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4089 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 9009.221326 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1350.566241 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.659456 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.659456 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 36852123 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 36852123 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 36852123 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 36852123 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 36852123 # number of overall hits -system.cpu.icache.overall_hits::total 36852123 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5235 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5235 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5235 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5235 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5235 # number of overall misses -system.cpu.icache.overall_misses::total 5235 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 167149000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 167149000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 167149000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 167149000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 167149000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 167149000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 36857358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 36857358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 36857358 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 36857358 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 36857358 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 36857358 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000142 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000142 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000142 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000142 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000142 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000142 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31929.130850 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31929.130850 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31929.130850 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31929.130850 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31929.130850 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31929.130850 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 608 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1350.344535 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.659348 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.659348 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 36838706 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 36838706 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 36838706 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 36838706 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 36838706 # number of overall hits +system.cpu.icache.overall_hits::total 36838706 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5281 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5281 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5281 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5281 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5281 # number of overall misses +system.cpu.icache.overall_misses::total 5281 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 212968998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 212968998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 212968998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 212968998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 212968998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 212968998 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 36843987 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 36843987 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 36843987 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 36843987 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 36843987 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 36843987 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000143 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000143 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000143 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000143 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000143 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000143 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40327.399735 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40327.399735 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40327.399735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40327.399735 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40327.399735 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1167 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 38 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58.350000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1123 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1123 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1123 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1123 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4112 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4112 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4112 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4112 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4112 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4112 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 128908500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 128908500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 128908500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 128908500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 128908500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 128908500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000112 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000112 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000112 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31349.343385 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31349.343385 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31349.343385 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 31349.343385 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31349.343385 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 31349.343385 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1190 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1190 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1190 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1190 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1190 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1190 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161081503 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 161081503 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161081503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 161081503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161081503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 161081503 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000111 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000111 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000111 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000111 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39374.603520 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39374.603520 # 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Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 2730 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.777656 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 4.024044 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1429.621147 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 536.884097 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.043629 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.060136 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 2045 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 90 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 204130250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.872727 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.559992 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992613 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.638842 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.501101 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.638842 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54145.802831 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57300.967262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54925.027563 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33475.716806 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33475.716806 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38106.668447 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38060.950829 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38085.676030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38106.668447 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38060.950829 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38085.676030 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50864.418605 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50864.418605 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54145.802831 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53340.297653 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53775.092202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54145.802831 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53340.297653 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53775.092202 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 61 # number of replacements -system.cpu.dcache.tagsinuse 1409.645291 # Cycle average of tags in use -system.cpu.dcache.total_refs 46783527 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1860 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25152.433871 # Average number of references to valid blocks. +system.cpu.dcache.replacements 57 # number of replacements +system.cpu.dcache.tagsinuse 1407.131551 # Cycle average of tags in use +system.cpu.dcache.total_refs 46775584 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1853 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25243.164598 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1409.645291 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.344152 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.344152 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34382093 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34382093 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356549 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356549 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22473 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22473 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 1407.131551 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.343538 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.343538 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34374175 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34374175 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356535 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356535 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22465 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22465 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 46738642 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 46738642 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 46738642 # number of overall hits -system.cpu.dcache.overall_hits::total 46738642 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1903 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1903 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7738 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7738 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 46730710 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 46730710 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 46730710 # number of overall hits +system.cpu.dcache.overall_hits::total 46730710 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1909 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1909 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7752 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7752 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9641 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9641 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9641 # number of overall misses -system.cpu.dcache.overall_misses::total 9641 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 93214000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 93214000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 305598496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 305598496 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 398812496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 398812496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 398812496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 398812496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34383996 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34383996 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9661 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9661 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9661 # number of overall misses +system.cpu.dcache.overall_misses::total 9661 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 115578500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 115578500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 443691996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 443691996 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 141000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 141000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 559270496 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 559270496 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 559270496 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 559270496 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34376084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34376084 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22475 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22475 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22467 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 22467 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46748283 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46748283 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46748283 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46748283 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000055 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000626 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000626 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 46740371 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46740371 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46740371 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46740371 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000627 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000627 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000089 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000206 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000206 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000206 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000206 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48982.658960 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48982.658960 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39493.214784 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39493.214784 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 41366.299761 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 41366.299761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 41366.299761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 41366.299761 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 527 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 67 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.000207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000207 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60544.002095 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60544.002095 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57235.809598 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57235.809598 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57889.503778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57889.503778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57889.503778 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 581 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 112 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.538462 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 33.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.416667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 19 # number of writebacks -system.cpu.dcache.writebacks::total 19 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1128 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1128 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6648 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6648 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17 # number of writebacks +system.cpu.dcache.writebacks::total 17 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1137 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1137 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6669 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6669 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7776 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7776 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7776 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7776 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1090 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1865 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1865 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1865 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1865 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 41130000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 50620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 50620998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 91750998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 91750998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 91750998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 91750998 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 7806 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7806 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7806 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7806 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 772 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 772 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1083 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1083 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1855 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1855 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1855 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1855 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49331013 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 49331013 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69111498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 69111498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118442511 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 118442511 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118442511 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 118442511 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53070.967742 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53070.967742 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46441.282569 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46441.282569 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63900.275907 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63900.275907 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63814.864266 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63814.864266 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index b26eb976b..24cdef337 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106766000 # Number of ticks simulated final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1465257 # Simulator instruction rate (inst/s) -host_op_rate 1604314 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 876741604 # Simulator tick rate (ticks/s) -host_mem_usage 282008 # Number of bytes of host memory used -host_seconds 117.60 # Real time elapsed on the host +host_inst_rate 2813934 # Simulator instruction rate (inst/s) +host_op_rate 3080985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1683727447 # Simulator tick rate (ticks/s) +host_mem_usage 236772 # Number of bytes of host memory used +host_seconds 61.24 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 188670891 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 438893991 # Wr system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 8876496088 # Throughput (bytes/s) +system.membus.data_through_bus 915226805 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index b91e59a80..6b5d6bef1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232072 # Nu sim_ticks 232072304000 # Number of ticks simulated final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 817822 # Simulator instruction rate (inst/s) -host_op_rate 895603 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1104464333 # Simulator tick rate (ticks/s) -host_mem_usage 290584 # Number of bytes of host memory used -host_seconds 210.12 # Real time elapsed on the host +host_inst_rate 1198657 # Simulator instruction rate (inst/s) +host_op_rate 1312657 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618778979 # Simulator tick rate (ticks/s) +host_mem_usage 245268 # Number of bytes of host memory used +host_seconds 143.36 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 476817 # In system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 952255 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 2361 # Transaction distribution +system.membus.trans_dist::ReadResp 2361 # Transaction distribution +system.membus.trans_dist::ReadExReq 1092 # Transaction distribution +system.membus.trans_dist::ReadExResp 1092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 6906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 6906 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 220992 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 220992 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -414,5 +429,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1339169 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 6102 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3594 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 9696 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 195264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 115520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 310784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 8a8554f1f..806cadbfa 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1868868 # Simulator instruction rate (inst/s) -host_op_rate 1868870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 934440193 # Simulator tick rate (ticks/s) -host_mem_usage 277724 # Number of bytes of host memory used -host_seconds 103.51 # Real time elapsed on the host +host_inst_rate 3763101 # Simulator instruction rate (inst/s) +host_op_rate 3763105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1881563141 # Simulator tick rate (ticks/s) +host_mem_usage 229516 # Number of bytes of host memory used +host_seconds 51.41 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory @@ -35,6 +35,9 @@ system.physmem.bw_write::total 745070490 # Wr system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 11057254439 # Throughput (bytes/s) +system.membus.data_through_bus 1069490213 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 193445891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 75edc6876..a79e42f60 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.270563 # Nu sim_ticks 270563082000 # Number of ticks simulated final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1012263 # Simulator instruction rate (inst/s) -host_op_rate 1012264 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1415810765 # Simulator tick rate (ticks/s) -host_mem_usage 286308 # Number of bytes of host memory used -host_seconds 191.10 # Real time elapsed on the host +host_inst_rate 942019 # Simulator instruction rate (inst/s) +host_op_rate 942020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1317563963 # Simulator tick rate (ticks/s) +host_mem_usage 238020 # Number of bytes of host memory used +host_seconds 205.35 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 850848 # In system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1223641 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 4095 # Transaction distribution +system.membus.trans_dist::ReadResp 4095 # Transaction distribution +system.membus.trans_dist::ReadExReq 1078 # Transaction distribution +system.membus.trans_dist::ReadExResp 1078 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 10346 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 331072 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 541126164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -379,5 +394,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 3279915 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 24576 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 27730 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 786432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 100992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 887424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 682644ea7..18746b39c 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.144599 # Number of seconds simulated -sim_ticks 144599413000 # Number of ticks simulated -final_tick 144599413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.144456 # Number of seconds simulated +sim_ticks 144456233500 # Number of ticks simulated +final_tick 144456233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53694 # Simulator instruction rate (inst/s) -host_op_rate 89995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58787129 # Simulator tick rate (ticks/s) -host_mem_usage 325332 # Number of bytes of host memory used -host_seconds 2459.71 # Real time elapsed on the host +host_inst_rate 58579 # Simulator instruction rate (inst/s) +host_op_rate 98184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64072469 # Simulator tick rate (ticks/s) +host_mem_usage 278680 # Number of bytes of host memory used +host_seconds 2254.58 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221362962 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 217792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory -system.physmem.bytes_read::total 343104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 217792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 217792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3403 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 342592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1506175 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 866615 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2372790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1506175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1506175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1506175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 866615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2372790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5365 # Total number of read requests seen +system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1504123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 867474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2371597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1504123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1504123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1504123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 867474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2371597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5356 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 5519 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 343104 # Total number of bytes read from memory +system.physmem.cpureqs 5495 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 342592 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 343104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 279 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 290 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 322 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 281 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 370 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 382 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 374 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 377 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 349 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 366 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 344 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 249 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 139 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 290 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 357 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 448 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 333 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 397 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 380 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 277 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 283 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 144599380000 # Total gap between requests +system.physmem.totGap 144456205000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 5365 # Categorize read packet sizes +system.physmem.readPktSize::6 5356 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 4242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,14 +149,79 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 15365500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 134288000 # Sum of mem lat for all requests -system.physmem.totBusLat 26825000 # Total cycles spent in databus access -system.physmem.totBankLat 92097500 # Total cycles spent in bank access -system.physmem.avgQLat 2864.03 # Average queueing delay per request -system.physmem.avgBankLat 17166.36 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25030.38 # Average memory access latency +system.physmem.bytesPerActivate::samples 510 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 662.337255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 234.191565 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 1287.834177 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 176 34.51% 34.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 77 15.10% 49.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 39 7.65% 57.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 29 5.69% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 22 4.31% 67.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 12 2.35% 69.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 18 3.53% 73.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 5 0.98% 74.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 13 2.55% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 6 1.18% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 3 0.59% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 6 1.18% 79.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 3 0.59% 80.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 6 1.18% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 7 1.37% 82.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 1 0.20% 83.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 6 1.18% 85.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 2 0.39% 85.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 2 0.39% 85.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 2 0.39% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 6 1.18% 87.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 1 0.20% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 3 0.59% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 1 0.20% 89.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 2 0.39% 89.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 1 0.20% 89.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 2 0.39% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 3 0.59% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 3 0.59% 91.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 4 0.78% 92.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 3 0.59% 93.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 2 0.39% 93.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 4 0.78% 94.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 1 0.20% 94.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 2 0.39% 96.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4289 1 0.20% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4353 1 0.20% 97.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6273 1 0.20% 98.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8193 5 0.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 510 # Bytes accessed per row activation +system.physmem.totQLat 13729500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 120235750 # Sum of mem lat for all requests +system.physmem.totBusLat 26770000 # Total cycles spent in databus access +system.physmem.totBankLat 79736250 # Total cycles spent in bank access +system.physmem.avgQLat 2563.39 # Average queueing delay per request +system.physmem.avgBankLat 14887.28 # Average bank access latency per request +system.physmem.avgBusLat 4998.13 # Average bus latency per request +system.physmem.avgMemAccLat 22448.80 # Average memory access latency system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s @@ -165,251 +230,272 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.avgRdQLen 0.00 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 4467 # Number of row buffer hits during reads +system.physmem.readRowHits 4844 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26952354.15 # Average gap between requests -system.cpu.branchPred.lookups 18673504 # Number of BP lookups -system.cpu.branchPred.condPredicted 18673504 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1493262 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11432454 # Number of BTB lookups -system.cpu.branchPred.BTBHits 10793701 # Number of BTB hits +system.physmem.avgGap 26970912.06 # Average gap between requests +system.membus.throughput 2371597 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3826 # Transaction distribution +system.membus.trans_dist::ReadResp 3823 # Transaction distribution +system.membus.trans_dist::UpgradeReq 139 # Transaction distribution +system.membus.trans_dist::UpgradeResp 139 # Transaction distribution +system.membus.trans_dist::ReadExReq 1530 # Transaction distribution +system.membus.trans_dist::ReadExResp 1530 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 10987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10987 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 342592 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 7029500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 50887361 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.branchPred.lookups 18668412 # Number of BP lookups +system.cpu.branchPred.condPredicted 18668412 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1491215 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11464480 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10808529 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.412809 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1324082 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 23521 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.278406 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1321942 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 23508 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 289482612 # number of cpu cycles simulated +system.cpu.numCycles 289199941 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 23502455 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 207109778 # Number of instructions fetch has processed -system.cpu.fetch.Branches 18673504 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 12117783 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 54283022 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 15594841 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 178283916 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1444 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8051 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22396392 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 221801 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 269918552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.268498 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.756525 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 23489092 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 206857811 # Number of instructions fetch has processed +system.cpu.fetch.Branches 18668412 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 12130471 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 54260755 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 15560780 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 178047703 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 7863 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22383448 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 227467 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 269615649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.269321 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.757232 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 217073469 80.42% 80.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2850604 1.06% 81.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2315423 0.86% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2639736 0.98% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3229574 1.20% 84.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3384900 1.25% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3844403 1.42% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2562175 0.95% 88.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32018268 11.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 216795166 80.41% 80.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2848237 1.06% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2316890 0.86% 82.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640281 0.98% 83.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3221568 1.19% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3391687 1.26% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3836150 1.42% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2560999 0.95% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32004671 11.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269918552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064506 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.715448 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36985977 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 167209662 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 41646466 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10236820 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 13839627 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336463810 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 13839627 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45047343 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 116751427 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 32413 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 42745141 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51502601 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 330086802 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 10951 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 26152362 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 22736681 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 382815435 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 919037508 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 910796649 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8240859 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 269615649 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064552 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.715276 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36944387 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 167005183 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 41608261 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10249032 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 13808786 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336293429 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 13808786 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 45003701 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 116679127 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28084 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 42750473 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51345478 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 329924152 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10957 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 26042658 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 22711387 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 324 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 382665072 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 918469595 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 910237815 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 8231780 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259428606 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 123386829 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2258 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2296 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 105258591 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 84679198 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 30165066 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 58703856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 19098571 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 323202869 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4566 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 260671940 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116724 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 101460757 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 211331898 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3321 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 269918552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.965743 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.342643 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 123236466 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2077 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2071 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 105014998 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 84558511 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 30136347 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 58291555 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 18982732 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 322974285 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4304 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 260692143 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 115978 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 101227039 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 210564251 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3059 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 269615649 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.966903 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.344359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 143572602 53.19% 53.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 55645964 20.62% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 34208859 12.67% 86.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19077068 7.07% 93.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10849323 4.02% 97.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4139320 1.53% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1825268 0.68% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 469630 0.17% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 130518 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 143415763 53.19% 53.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 55488403 20.58% 73.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 34156757 12.67% 86.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19088088 7.08% 93.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10888681 4.04% 97.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4144802 1.54% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1820810 0.68% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 476392 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 135953 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 269918552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 269615649 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 131441 4.84% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2279294 83.91% 88.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 305503 11.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 130533 4.80% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2283697 84.00% 88.80% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 304445 11.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1210514 0.46% 0.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 162160673 62.21% 62.67% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 788045 0.30% 62.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7035797 2.70% 65.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1444934 0.55% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 65461399 25.11% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22570578 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1210883 0.46% 0.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 162146963 62.20% 62.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 788849 0.30% 62.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035772 2.70% 65.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1445624 0.55% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 65501773 25.13% 91.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22562279 8.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 260671940 # Type of FU issued -system.cpu.iq.rate 0.900475 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2716238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010420 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 789209442 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 421320217 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 255304788 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4885952 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3632838 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2349442 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 259718878 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2458786 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18858463 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 260692143 # Type of FU issued +system.cpu.iq.rate 0.901425 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2718675 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010429 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 788942081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 420863494 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 255312010 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4892507 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3626050 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2350305 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 259737433 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2462502 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18945833 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 28029611 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25725 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 290431 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9649349 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27908924 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 26612 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 289609 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9620630 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 49573 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 51419 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 13839627 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 84981347 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5427028 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 323207435 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 136147 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 84679198 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 30165066 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2231 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2677235 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14355 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 290431 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 637937 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 905599 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1543536 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 258899576 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64693791 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1772364 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 13808786 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 85007909 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5442016 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 322978589 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 134528 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 84558511 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 30136347 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2042 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2673918 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 13520 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 289609 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 642268 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 899522 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1541790 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 258904579 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64718726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1787564 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 87060323 # number of memory reference insts executed -system.cpu.iew.exec_branches 14273836 # Number of branches executed -system.cpu.iew.exec_stores 22366532 # Number of stores executed -system.cpu.iew.exec_rate 0.894353 # Inst execution rate -system.cpu.iew.wb_sent 258261406 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 257654230 # cumulative count of insts written-back -system.cpu.iew.wb_producers 206076672 # num instructions producing a value -system.cpu.iew.wb_consumers 369295783 # num instructions consuming a value +system.cpu.iew.exec_refs 87077956 # number of memory reference insts executed +system.cpu.iew.exec_branches 14272272 # Number of branches executed +system.cpu.iew.exec_stores 22359230 # Number of stores executed +system.cpu.iew.exec_rate 0.895244 # Inst execution rate +system.cpu.iew.wb_sent 258260440 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 257662315 # cumulative count of insts written-back +system.cpu.iew.wb_producers 206077428 # num instructions producing a value +system.cpu.iew.wb_consumers 369317966 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.890051 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.558026 # average fanout of values written-back +system.cpu.iew.wb_rate 0.890949 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557995 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 101920014 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 101692643 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1494473 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 256078925 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.864433 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.651734 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1492367 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 255806863 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.865352 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.655114 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 156603135 61.15% 61.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57289650 22.37% 83.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14093127 5.50% 89.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12068952 4.71% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4185763 1.63% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2969218 1.16% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 905577 0.35% 96.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1050426 0.41% 97.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6913077 2.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 156513813 61.18% 61.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57168789 22.35% 83.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14010033 5.48% 89.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12060678 4.71% 93.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4174757 1.63% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2964012 1.16% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 898257 0.35% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1048749 0.41% 97.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6967775 2.72% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 256078925 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 255806863 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -420,198 +506,220 @@ system.cpu.commit.branches 12326938 # Nu system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.int_insts 220339553 # Number of committed integer instructions. system.cpu.commit.function_calls 797818 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6913077 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6967775 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 572448824 # The number of ROB reads -system.cpu.rob.rob_writes 660431667 # The number of ROB writes -system.cpu.timesIdled 5928357 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19564060 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 571894693 # The number of ROB reads +system.cpu.rob.rob_writes 659945778 # The number of ROB writes +system.cpu.timesIdled 5917549 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19584292 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated -system.cpu.cpi 2.191868 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.191868 # CPI: Total CPI of All Threads -system.cpu.ipc 0.456232 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.456232 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 554310914 # number of integer regfile reads -system.cpu.int_regfile_writes 293915019 # number of integer regfile writes -system.cpu.fp_regfile_reads 3215317 # number of floating regfile reads -system.cpu.fp_regfile_writes 2009393 # number of floating regfile writes -system.cpu.misc_regfile_reads 133439176 # number of misc regfile reads +system.cpu.cpi 2.189728 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.189728 # CPI: Total CPI of All Threads +system.cpu.ipc 0.456678 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.456678 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 554359034 # number of integer regfile reads +system.cpu.int_regfile_writes 293931276 # number of integer regfile writes +system.cpu.fp_regfile_reads 3216619 # number of floating regfile reads +system.cpu.fp_regfile_writes 2010069 # number of floating regfile writes +system.cpu.misc_regfile_reads 133442201 # number of misc regfile reads system.cpu.misc_regfile_writes 845 # number of misc regfile writes -system.cpu.icache.replacements 4633 # number of replacements -system.cpu.icache.tagsinuse 1627.424900 # Cycle average of tags in use -system.cpu.icache.total_refs 22387705 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 6601 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3391.562642 # Average number of references to valid blocks. +system.cpu.toL2Bus.throughput 3896100 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 7248 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7244 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13426 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4292 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 17718 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 425152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 553920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 553920 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8896 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4481500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 10173000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3068000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.icache.replacements 4678 # number of replacements +system.cpu.icache.tagsinuse 1622.603356 # Cycle average of tags in use +system.cpu.icache.total_refs 22374543 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 6643 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3368.138341 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1627.424900 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.794641 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.794641 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 22387705 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22387705 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22387705 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22387705 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22387705 # number of overall hits -system.cpu.icache.overall_hits::total 22387705 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8687 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8687 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8687 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8687 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8687 # number of overall misses -system.cpu.icache.overall_misses::total 8687 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 264464000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 264464000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 264464000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 264464000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 264464000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 264464000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22396392 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22396392 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22396392 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22396392 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22396392 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22396392 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30443.651433 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30443.651433 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30443.651433 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30443.651433 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30443.651433 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30443.651433 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 666 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1622.603356 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.792287 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.792287 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 22374545 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22374545 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22374545 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22374545 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22374545 # number of overall hits +system.cpu.icache.overall_hits::total 22374545 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8903 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8903 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8903 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8903 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8903 # number of overall misses +system.cpu.icache.overall_misses::total 8903 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 349961000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 349961000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 349961000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 349961000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 349961000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 349961000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22383448 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22383448 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22383448 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22383448 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22383448 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22383448 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39308.210715 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39308.210715 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39308.210715 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39308.210715 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1033 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.625000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57.388889 # 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number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6756 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6756 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6756 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203573500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203573500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203573500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203573500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203573500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203573500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000302 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000302 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 122420067 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68838816 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 191258883 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 122420067 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68838816 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 191258883 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.515601 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.938865 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.543059 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 5357 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 181247500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25841000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 207088500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1390139 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1390139 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 181247500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 103203000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 284450500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 181247500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 103203000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 284450500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.511138 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926882 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.538332 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995449 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995449 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.515601 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.982465 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.623982 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.515601 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.982465 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.623982 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35963.591951 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47831.595349 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37294.640845 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995446 # 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average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31529.216199 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31529.216199 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35963.591951 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35103.934727 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35649.372414 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35963.591951 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35103.934727 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35649.372414 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50563.398693 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50563.398693 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 54 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45681294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 1435.278677 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.350410 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.350410 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 45616715 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45616715 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514054 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514054 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 66130769 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 66130769 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 66130769 # number of overall hits +system.cpu.dcache.overall_hits::total 66130769 # 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number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 66133379 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 66133379 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 66133379 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 66133379 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46667.641326 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46667.641326 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 170 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60273.847803 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60273.847803 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62513.714967 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62513.714967 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61713.026820 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61713.026820 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.666667 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 13 # number of writebacks system.cpu.dcache.writebacks::total 13 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 414 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 414 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 415 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 415 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 415 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 415 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 458 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1692 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1692 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2150 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2150 # 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number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 467 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 466 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 466 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1675 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1675 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32012500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101366000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 101366000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133378500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 133378500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133378500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 133378500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses @@ -772,14 +880,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58093.886463 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58093.886463 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42954.196217 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42954.196217 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46179.302326 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46179.302326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46179.302326 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46179.302326 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68696.351931 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68696.351931 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60517.014925 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60517.014925 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 817f7471e..4a8749fb9 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -33,6 +33,9 @@ system.physmem.bw_write::total 759721898 # Wr system.physmem.bw_total::cpu.inst 10563380223 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3122279959 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13685660183 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 13685660183 # Throughput (bytes/s) +system.membus.data_through_bus 1798200879 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 262786137 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index cfc0b5abb..de904232a 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -27,6 +27,25 @@ system.physmem.bw_inst_read::total 724276 # In system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 1207552 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 3160 # Transaction distribution +system.membus.trans_dist::ReadResp 3160 # Transaction distribution +system.membus.trans_dist::ReadExReq 1575 # Transaction distribution +system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 303040 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 501907914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -364,5 +383,25 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 1684707 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 9388 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3817 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 13205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 300416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 122368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 422784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |